ON Semiconductor NCV7446 User Manual

Dual CAN FD Transceiver,
High Speed, Low Power

NCV7446

Description

NCV7446 is a dual CAN FD physical layer transceiver. It allows
interfacing of two independent CAN physical buses and two
independent CAN protocol controllers. The transceivers provide
differential transmit capability to the bus and differential receive
capability to the CAN controllers.

It is consisted of two fully independent NCV7344 transceivers. The
NCV7446 guarantees additional timing parameters to ensure robust
communication at data rates beyond 1 Mbps to cope with CAN
flexible data rate requirements (CAN FD). These features make the
NCV7446 an excellent choice for all types of HS−CAN networks, in
nodes that require a low−power mode with wake−up capability via the
CAN bus.

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DFNW14

CASE 507AC

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MARKING
DIAGRAM

NV74

46−0

ALYW

G

Features

• Compliant with the ISO 11898−2:2016

• CAN FD Timing Specified up to 5 Mbps

• Very Low Current Standby Mode with Wake−up via the Bus

• Low Electromagnetic Emission (EME) and High Electromagnetic

Immunity

• No Disturbance of the Bus Lines with an Un−powered Node

• Transmit Data (TxD) Dominant Timeout Function

• Under All Supply Conditions the Chip Behaves Predictably

• Very High ESD Robustness of Bus Pins

• Thermal Protection

• Bus Pins Short Circuit Proof to Supply Voltage and Ground

• Bus Pins Protected Against Transients in an Automotive

Environment

Quality

• Wettable Flank Package for Enhanced Optical Inspection

• AEC−Q100 Qualified and PPAP Capable

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

Typical Applications

• Automotive

• Industrial Networks

NV7446−0 = Specific Device Code
A = Assembly Site
L = Wafer Lot
Y = Year of Production, Last Number
W = Work Week Number
G = Pb−Free Package

PIN CONNECTIONS

TxD1

GND1

VCC1

RxD1

TxD2

GND2

VCC2

1

2

3

4

5

6

7

NCV7446

14

STB1

13

CANH1

12

CANL1

11

STB2

10

CANH2

9

CANL2

8

RxD2

ORDERING INFORMATION

See detailed ordering and shipping information in the
package dimensions section on page 12 of this data sheet.

© Semiconductor Components Industries, LLC, 2018

December, 2019 − Rev. 2

1 Publication Order Number:

NCV7446/D

NCV7446

BLOCK DIAGRAM

V

CC1

3

V

CC1

NCV7446

TxD1

STB1

RxD1

GND1

14

Thermal

1

V

CC 1

4

2

Timer

Mode &

Wake −up

control

shutdown

Driver control

Wake −up

Filter

COMP

COMP

13

12

CANH1

CANL1

Channel 1

TxD2

GND2

V

CC2

5

6

7

Figure 1. NCV7446 Block Diagram

Channel2

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2

11

10

9

8

STB2

CANH2

CANL2

RxD2

NCV7446

TYPICAL APPLICATION DIAGRAM

VBAT

IN OUT

5V −reg

.

V

CC

Micro−

controller

GND

STB1

TxD1

RxD1

STB2

TxD2

RxD2

V

CC1

3

14

1

NCV7446

4

11

5

8

26

GND1

7

13

12

10

GND2

V

9

CC2

CANH1

CAN

BUS

CANL1

CANH2

CAN

BUS

CANL2

Figure 2. NCV7446 Application Diagram

Table 1. PIN FUNCTION DESCRIPTION

Pin Number Pin Name Description

1 TxD1

2 GND1 Ground for channel 1

3 V

4 RxD1

5 TxD2

6 GND2 Ground for channel 2

7 V

8 RxD2

9 CANL2 Low−level CAN bus line channel 2 (low in dominant mode)

10 CANH2 High−level CAN bus line channel 2 (high in dominant mode)

11 STB2 Standby mode control input for channel 2; internal pull−up current

12 CANL1 Low−level CAN bus line channel 1 (low in dominant mode)

13 CANH1 High−level CAN bus line channel 1 (high in dominant mode)

14 STB1 Standby mode control input for channel 1; internal pull−up current

EP Exposed Pad Recommended to connect to GND or left floating in application

CC1

CC2

Transmit data input for channel 1; low input Ù dominant driver; internal pull−up current

Supply voltage for channel 1

Receive data output for channel 1; dominant transmitter Ù low output

Transmit data input for channel 2; low input Ù dominant driver; internal pull−up current

Supply voltage for channel 2

Receive data output for channel 2; dominant transmitter Ù low output

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NCV7446

FUNCTIONAL DESCRIPTION

Operating Modes

NCV7446 provides two modes of operation per
transceiver as illustrated in Table 2. These modes are
selectable through pins STB1 and STB2 independently for
each transceiver.

Table 2. OPERATING MODES

Pins

STBx

Low Normal

High Standby

Normal Mode

Mode Pins RxDx

Low when bus
dominant

Follows the bus
when wake−up
detected

High when bus
recessive

High when no
wake−up re­quest detected

In the normal mode, the selected transceiver is able to
communicate via the bus lines. The signals are transmitted
and received to the CAN controller via the pins TxDx and
RxDx. The slopes on the bus lines outputs are optimized to
give low EME.

t

wake_filt

t

wake_filt

Standby Mode

In standby mode both the transmitter and receiver are
disabled and a very low−power differential receiver
monitors the bus lines for CAN bus activity. The bus lines
are biased to ground and supply current is reduced to a
minimum. When a wake−up request is detected by the
low−power differential receiver, the signal is first filtered
and then verified as a valid wake signal after a time period of
t

wake_filt, the corresponding RxDx pin is driven low by the

transceiver (following the bus) to inform the controller of
the wake−up request.

Wake−up

When a valid wake−up pattern (phase in order
dominant − recessive − dominant) is detected during the
standby mode the RxDx pins follows the bus. Minimum
length of each phase is t

wake_filt

Pattern must be received within t

– see Figure 3.

to be recognized

wake_to

as valid wake−up otherwise internal logic is reset.

t

wake_filt

CANHx

CANLx

RxDx

<t

wake_to

Figure 3. NCV7446 Wake−up behavior

t

dwakerdtdwakedr

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NCV7446

Overtemperature Detection

A thermal protection circuit protects the IC from damage

by switching off the affected transmitter if the junction
temperature exceeds a value of approximately 170°C.
Because the transmitter dissipates most of the power, the
power dissipation and temperature of the IC is reduced. All
other IC functions continue to operate. The transmitter
off−state resets when the temperature decreases below
the shutdown threshold and pins TxDx goes high.
The thermal protection circuit is particularly needed when
a bus line short circuits.

TxDx Dominant Timeout Function

A TxD dominant timeout timer circuit prevents the bus
lines being driven to a permanent dominant state (blocking
all network communication) if pins TxDx are forced
permanently low by a hardware and/or software application
failure. The timer is triggered by a negative edge on pins
TxDx. If the duration of the low−level on pins TxDx exceeds
the internal timer value t

dom(TxD)

, the transmitter is
disabled, driving the bus into a recessive state. The timer is
reset by a positive edge on pins TxDx.

This TxD dominant timeout time t

dom(TxD)

defines

the minimum possible bit rate to 17 kbps.

Fail Safe Features

A current−limiting circuit protects the transmitter output
stage from damage caused by accidental short circuit
to either positive or negative supply voltage, although
power dissipation increases during this fault condition.

Undervoltage on V
sending data on the bus when there is not enough V

CC1

or V

pins prevents the chip

CC2

CC

supply

voltage.

After supply is recovered, corresponding TxD pin must be
first released to high to allow sending dominant bits again.
Recovery time from undervoltage detection is equal to
td(stb−nm) time.

The pins CANHx and CANLx are protected from
automotive electrical transients (according to ISO 7637; see
Figure 5). Pins TxDx and STBx are pulled high internally
should the input become disconnected. Pins TxDx, STBx
and RxDx will be floating, preventing reverse supply should
the adjacent VCCx supply be removed.

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NCV7446

ELECTRICAL CHARACTERISTICS

Definitions

All voltages are referenced to GNDx (pin 2 or pin 6).

Positive currents flow into the IC. Sinking current means the

Table 3. ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Conditions Min Max Unit

V

SUP

V

CANH

V

CANL

V

CANH−CANL

V

IN

V

OUT

V

esdHBM

V

esdCDM

V

esdIEC

V

schaff

Supply voltage V

DC voltage at pins CANHx 0 < V

DC voltage at pins CANLx 0 < V

DC voltage between any two pins
(including CANHx and CANLx)

DC Voltage at pins TxDx, STBx −0.3 +6 V

DC Voltage at pin RxDx −0.3 V

Electrostatic discharge voltage at all pins,
Component HBM

Electrostatic discharge voltage at all pins,
Component CDM

Electrostatic discharge voltage at pins CANHx
and CANLx, System HBM (Note 4)

Voltage transients, pins CANHx, CANLx.
According to ISO7637−3, Class C (Note 4)

Latch−up Static latch−up at all pins (Note 5) 150 mA

T

stg

T

J

Storage temperature −55 +150 °C

Maximum junction temperature −40 +170 °C

MSL Moisture Sensitivity Level 1 −

T

SLD

Lead temperature Soldering − Reflow (Note 11) − 260 °C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.

1. Standardized human body model electrostatic discharge (ESD) pulses in accordance to EIA−JESD22. Equivalent to discharging a 100 pF
capacitor through a 1.5 kW resistor.

2. Standardized charged device model ESD pulses when tested according to AEC−Q100−011.

3. System human body model electrostatic discharge (ESD) pulses in accordance to IEC 61000−4−2. Equivalent to discharging a 150 pF
capacitor through a 330 W resistor referenced to GNDx.

4. Results were verified by external test house.

5. Static latch−up immunity: Static latch−up protection level when tested according to EIA/JESD78.

6. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D

Table 4. THERMAL CHARACTERISTICS

Symbol Parameter Conditions Value Unit

R

q

JA_1

R

q

JA_2

R

q

JA_3

R

q

JA_4

7. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.

8. Test board according to EIA/JEDEC Standard JESD51−3, signal layer with 10% trace coverage.

9. Test board according to EIA/JEDEC Standard JESD51−7, signal layers with 10% trace coverage.

10. Test board according to EIA/JEDEC Standard JESD51−3 and JESD51−5 , signal layer with 10% trace coverage and with thermal via array
under the exposed pad connected to the second copper layer.

11. Test board according to EIA/JEDEC Standard JESD51−5 and JESD51−7, signal layers with 10% trace coverage and thermal via array under
the exposed pad connected to the first inner copper layer.

Thermal Resistance Junction−to−Air, JEDEC 1S0P PCB Free air; (Note 8) 101 K/W

Thermal Resistance Junction−to−Air, JEDEC 2S2P PCB Free air; (Note 9) 53 K/W

Thermal Resistance Junction−to−Air Free air; (Note 10) 76 K/W

Thermal Resistance Junction−to−Air Free air; (Note 11) 46 K/W

CC1,

V

CC2

current is flowing into the pin; sourcing current means the
current is flowing out of the pin.

−0.3 +6 V

< 5.25 V; no time limit −42 +42 V

CCX

< 5.25 V; no time limit −42 +42 V

CCX

−42 +42 V

+ 0.3 V

CCx

(Note 1) −8 +8 kV

(Note 2) −750 +750 V

Without bus filter (Note 3) −7 +7 kV

With bus filter (Note 3) −11 +11 kV

test pulses 1 −100 V

test pulses 2a +75 V

test pulses 3a −150 V

test pulses 3b +100 V

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Table 5. ELECTRICAL CHARACTERISTICS

V

V

CC1,

SUPPLY (PINS V

V

UVD(VCC)(stby)

V

UVD(VCC)(swoff)

TRANSMITTER DATA INPUT (Pins TxDx)

TRANSMITTER MODE SELECT (Pins STBx)

RECEIVER DATA OUTPUT (Pins RxDx)

BUS LINES (Pins CANHx and CANLx)

V

V

V

V

V

V

V

= 4.75 V to 5.25 V; TJ = −40°C to +150°C; RLT = 60 W, C

CC2

Symbol

V

CCx

I

CCx

I

CCSx

)

CCX

Power supply voltage (Note 12) 4.75 5.0 5.25 V

Supply current on single channel

Supply current in standby mode on

single channel

Parameter Conditions Min Typ Max Unit

Standby undervoltage detection V

Switch−off undervoltage detection V

V

IH

V

IL

I

IH

I

IL

C

i

V

IH

V

IL

I

IH

I

IL

C

i

I

OH

I

OL

I

o(rec)

I

LI

o(rec)(CANH)

o(rec)(CANL)

o(off)(CANH)

o(off)(CANL)

o(off)(CANL)

o(dom)(CANH)

o(dom)(CANL)

High−level input voltage Output recessive 2.0 − − V

Low−level input voltage Output dominant − − +0.8 V

High−level input current V

Low−level input current V

Input capacitance (Note 13) − 5 10 pF

High−level input voltage Standby mode 2.0 − − V

Low−level input voltage Normal mode − − +0.8 V

High−level input current V

Low−level input current V

Input capacitance (Note 13) − 5 10 pF

High−level output current Normal mode

Low−level output current V

Recessive output current at pins
CANHx and CANLx

Input leakage current

Recessive output voltage at pins CANHx Normal mode, V

Recessive output voltage at pins CANLx Normal mode, V

Recessive output voltage at pin CANHx Standby mode; RLT and C

Recessive output voltage at pin CANLx Standby mode; RLT and C

Differential bus output voltage
(V

CANHx * VCANLx)

Dominant output voltage at pins CANHx V

Dominant output voltage at pins CANLx V

NCV7446

= 100 pF, C1 not used, C

LT

Dominant; V

Recessive; V

= Low 20 45 55 mA

TxDx

= Low 1.9 5.0 10 mA

TxDx

Normal mode, Dominant;
V

= 0 V; one of bus wires

TxDx

shorted; −3 V ≤ (V
V

) ≤ +18 V

CANLx

CANHx

TJ ≤ 100°C, (Note 13) − 10 15

pins 3.5 4.0 4.3 V

CCx

pins 2.0 2.3 2.6 V

CCx

= V

TxDx

CCx

= 0 V −300 −150 −70

TxDx

= V

STBx

STBx

V

RxDx

RxDx

−27 V < V
+32 V; Normal mode

0 W < R(V
1 MW; V

R

LT

R

LT

CCx

= 0 V −15 − −1.0

= V

– 0.4 V

CCx

= 0.4 V 1.0 6.0 12 mA

, V

CANHx

CCx

CANLx

and CLT not used

and CLT not used

CANLx

to GNDx) <

= V

CANHx

= High;

TxDx

= High;

TxDx

not used

not used

Standby mode; RLT and C
not used

= 0 V; t < tdom(TxD);

TxDx

50 W < R

TxDx

50 W < R

< 65 W

LT

= 0 V; t < tdom(TxD);

< 65 W

LT

= 15 pF, unless specified otherwise.

RxD

2.0 − 105 mA

,

−5.0 0 +5.0

−1.0 0 +1.0

−8.0 −3.0 −1.0 mA

<

−5.0 − +5.0 mA

−5.0 0 +5.0

= 5 V

2.0 2.5 3.0 V

2.0 2.5 3.0 V

LT

LT

LT

−0.1 − +0.1 V

−0.1 − +0.1 V

−0.2 − +0.2 V

2.75 3.5 4.5 V

0.5 1.5 2.25 V

mA

mA

mA

mA

mA

mA

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Table 5. ELECTRICAL CHARACTERISTICS

V

V

CC1,

BUS LINES (Pins CANHx and CANLx)

V

o(dom)(diff)_arb

V

V

V

V

V

V

i(diff)(th)_NORM

V

i(diff)(th)_NORM_H

V

i(diff)(th)_STDBY

R

R

THERMAL SHUTDOWN

TIMING CHARACTERISTICS (see Figure 4 and Figure 6)

t

d(TxD−BUSon)

t

d(TxD−BUSoff)

t

d(BUSon−RxD)

t

d(BUSoff−RxD)

= 4.75 V to 5.25 V; TJ = −40°C to +150°C; RLT = 60 W, C

CC2

Symbol UnitMaxTypMinConditionsParameter

V

o(dom)(diff)

V

o(rec)(diff)

Differential bus output voltage
(V

CANHx

− V

CANLx

)

Differential bus output voltage
(V

CANHx

− V

CANLx

)

Differential bus output voltage during

o(dom)(sym)

I

o(sc)(CANH)

I

o(sc)(CANL)

i(rec)(diff)_NM

i(rec)(diff)_LP

i(dom)(diff)_NM

i(dom)(diff)_LP

arbitration (V

Dominant output voltage driver symmetry
(V

CANHx + VCANLx)

Short circuit output current at pins CANHx −3 V < V

Short circuit output current at pins CANLx −3 V < V

Differential input voltage range recessive
state

Differential input voltage range dominant
state

CANHx

− V

CANLx

)

Differential receiver threshold voltage in
normal mode

Differential receiver threshold voltage in
normal mode, extended range

Differential receiver threshold voltage in
standby mode

i(cm)(CANH)

i(cm)(CANL)

R

i(cm)(m)

R

i(diff)

C

i(CANH)

C

i(CANL)

C

i(diff)

T

J(sd)

Common−mode input resistance at pin
CANHx

Common−mode input resistance at pin
CANLx

Matching between pin CANHx and pin
CANLx common mode input resistance

Differential input resistance −2 V ≤ V

Input capacitance at pins CANHx V

Input capacitance at pins CANLx V

Differential input capacitance V

Shutdown junction temperature per channel Junction temperature rising 160 180 200 °C

Delay TxDx to bus active − 75 − ns

Delay TxDx to bus inactive − 85 − ns

Delay bus active to RxDx − 24 − ns

Delay bus inactive to RxDx − 32 − ns

t

pd_dr

Propagation delay TxDx to RxDx
dominant to recessive transition

NCV7446

= 100 pF, C1 not used, C

LT

V

= 0 V; dominant;

TxDx

45 W < R

V

TxDx

load

R

LT =

RLT = 60W; C1 = 4.7 nF; C
not used; TxDx = square
wave up to 1 MHz

Normal mode;

−12 V ≤ V
V

CANLx

Standby mode;

−12 V ≤ V
V

CANLx

Normal mode;

−12 V ≤ V
V

CANLx

Standby mode;

−12 V ≤ V
V

CANLx

−12 V ≤ V

−12 V ≤ V

−30 V < V

−30 V < V

−12 V ≤ V

−12 V ≤ V

−2 V ≤ V

−2 V ≤ V

−2 V ≤ V

−2 V ≤ V

V

CANHx

−2 V ≤ V

TxDx

TxDx

TxDx

< 65 W

LT

= High; recessive; no

2.24kW (Note 13)

< +18 V −100 − 1.5 mA

CANHx

< +36 V −1.5 − 100 mA

CANLx

CANHx

≤ +12 V; no load

CANHx

≤ +12 V; no load

CANHx

≤ +12 V; no load

CANHx

≤ +12 V; no load

CANLx
CANHx

CANLx
CANHx

CANLx
CANHx

≤ +7 V;

CANLx

≤ +7 V

CANHx

≤ +7 V;

CANLx

≤ +7 V

CANHx

= V

CANLx

≤ +7 V;

CANLx

≤ +7 V

CANHx

= High; (Note 13) − 4.5 20 pF

= High; (Note 13) − 4.5 20 pF

= High; (Note 13) − 3.75 10 pF

= 15 pF, unless specified otherwise.

RxD

1.5 2.25 3.0 V

−50 0 +50 mV

1.5 − 5.0 V

LT

0.9 1.0 1.1 VCCx

−3.0 − 0.5 V

,

−3.0 0.4 V

,

0.9 − 8.0 V

,

1.05 8.0 V

,

≤ +12 V;

0.5 − 0.9 V

≤ +12 V

< +35 V;

0.4 − 1.0 V

< +35 V

≤ +12 V;

0.4 − 1.05 V

≤ +12 V

15 26 37

15 26 37

= +5 V −1 0 +1 %

25 50 75

50 100 210 ns

kW

kW

kW

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NCV7446

Table 5. ELECTRICAL CHARACTERISTICS

V

V

CC1,

= 4.75 V to 5.25 V; TJ = −40°C to +150°C; RLT = 60 W, C

CC2

Symbol UnitMaxTypMinConditionsParameter

TIMING CHARACTERISTICS (see Figure 4 and Figure 6)

t

pd_rd

t

d(stb−nm)

t

wake_filt

t

dwakerd

t

dwakedr

t

wake_to

t

dom(TxD)

t

Bit(RxD)

t

Bit(Vi(diff))

Dt

Rec

Propagation delay TxDx to RxDx
recessive to dominant transition

Delay standby mode to normal mode 5.0 11 20

Dominant time for wake−up via bus 0.5 − 5.0

Delay to flag wake event
(recessive to dominant transitions)

Delay to flag wake event
(dominant to recessive transitions)

Bus time for wake−up timeout Standby mode 1.0 − 10 ms

TxDx dominant time for timeout V

Bit time on RxDx pin

Bit time on bus (CANHx – CANLx pin)

Receiver timing symmetry
Dt

Rec =

t

Bit(RxD) −

t

Bit(Vi(diff))

;

12.In the range of 4.5 V to 4.75 V and from 5.25 V to 5.5 V the chip is fully functional; some parameters may be outside of the specification.

13.Values based on design and characterization, not tested in production.

= 100 pF, C1 not used, C

LT

= 15 pF, unless specified otherwise.

RxD

50 120 210 ns

Valid bus wake−up event 0.5 2.6 6.0

Valid bus wake−up event 0.5 2.6 6.0

= 0 V; Normal mode 1.0 − 10 ms

TxDx

t

= 500 ns 400 − 550 ns

Bit(TxD)

t

= 200 ns 120 − 220 ns

Bit(TxD)

t

= 500 ns 435

Bit(TxD)

t

= 200 ns 155

Bit(TxD)

t

= 500 ns −65 − +40 ns

Bit(TxD)

t

= 200 ns −45 − +15 ns

Bit(TxD)

−

−

530 ns

210 ns

ms

ms

ms

ms

1

TxDx

V

i(diff)=VCANHx−VCANLx

RxDx

MEASUREMENT SETUPS AND DEFINITIONS

0.7 × V

IO

0.3 × V

IO

5 × t

bit(TxD)

1

TxDx Edge length below 10 ns

t

d(TxD−BUSoff)

t

t

d(TxD−BUSon)

500 mV

0.7 × V

bit(TxD)

t

pd_dr

t

bit(Vi(diff))

IO

0.3 × V

t

pd_rd

t

d(BUSoff−RxD)

t

bit(RxD)

IO

900 mV

t

d(BUSon−RxD)

0.3 × V

IO

Figure 4. Transceiver Timing Diagram

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+5 V

100 nF

TxD1

TxD2

RxD1

3

1

5

4

NCV7446

V

CC1

NCV7446

V

CC2

5

13

CANH1

1nF

Transient

Generator

1nF

12

CANL1

+5 V

15 pF

15 pF

CANH2

10

1nF

RxD2

8

11

14

STB1 GND1

2

STB2

9

6

GND2

1nF

CANL2

Figure 5. Test Circuit for Automotive Transients

100 nF

TxD1

TxD2

RxD1

V

CC1

35

1

5

4

NCV 7446

V

CC2

CANH 1

13

RLT/2

4.7 nF

C

1

RLT/2

12

CANL1

Generator

2x 30 W

Transient

C

LT

100 pF

15 pF

15 pF

RxD 2

8

11

14

STB2

STB1 GND 1

10

9

6

2

GND2

Figure 6. Test Circuit for Timing Characteristics

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CANH2

4.7 nF

CANL2

RLT/2

C

1

RLT/2

2x 30 W

C

LT

100 pF

NCV7446

Table 6. ISO 11898−2:2016 PARAMETER CROSS−REFERENCE TABLE

ISO 11898−2:2016 Specification NCV7446 Datasheet

Parameter Notation Symbol

Dominant output characteristics

Single ended voltage on CAN_H

Single ended voltage on CAN_L V

Differential voltage on normal bus load V

Differential voltage on effective resistance during arbitration V

Differential voltage on extended bus load range (optional) V

V

CAN_H

CAN_L

Diff

Diff

Diff

Driver symmetry

Driver symmetry

V

SYM

Driver output current

Absolute current on CAN_H

Absolute current on CAN_L I

I

CAN_H

CAN_L

Receiver output characteristics, bus biasing active

Single ended output voltage on CAN_H

Single ended output voltage on CAN_L V

Differential output voltage V

V

CAN_H

CAN_L

Diff

Receiver output characteristics, bus biasing inactive

Single ended output voltage on CAN_H

Single ended output voltage on CAN_L V

Differential output voltage V

V

CAN_H

CAN_L

Diff

Optional transmit dominant timeout

Transmit dominant timeout, long

Transmit dominant timeout, short t

t

dom

dom

Static receiver input characteristics, bus biasing active

Recessive state differential input voltage range

Dominant state differential input voltage range V

V

Diff

Diff

Static receiver input characteristics, bus biasing inactive

Recessive state differential input voltage range

Dominant state differential input voltage range V

V

Diff

Diff

Receiver input resistance

Differential internal resistance R

Single ended internal resistance R

CAN_H

R

CAN_L

Diff

Receiver input resistance matching

Matching a of internal resistance

m

R

Implementation loop delay requirement

Loop delay

t

Loop

Optional implementation data signal timing requirements for use with bit rates above 1 Mbit/s and up to 2 Mbit/s

Transmitted recessive bit width @ 2 Mbit/s

Received recessive bit width @ 2 Mbit/s t

Receiver timing symmetry @ 2 Mbit/s

t

Bit(Bus)

Bit(RXD)

Dt

Rec

V

V

V

o(dom)(diff)_arb

V

I

I

V

V

V

V

V

V

i(dom)(diff)_NM

V

V

R
R

o(dom)(CANH)

o(dom)(CANL)

V

o(dom)(diff)

V

o(dom)(diff)

o(dom)(sym)

o(SC)(CANH)

o(SC)(CANL)

o(rec)(CANH)

o(rec)(CANL)

V

o(rec)(diff)

o(off)(CANH)

o(off)(CANL)

V

o(off)(dif)

t

dom(TxD)

NA

i(rec)(diff)_NM

i(rec)(diff)_LP

i(dom)(diff)_LP

R

i(diff)

i(cm)(CANH)

i(cm)(CANL)

R

i(cm)(m)

t

pd_rd

t

pd_dr

t

Bit(Vi(diff))

t

Bit(RxD)

D

tRec

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11

NCV7446

†

Table 6. ISO 11898−2:2016 PARAMETER CROSS−REFERENCE TABLE

ISO 11898−2:2016 Specification NCV7446 Datasheet

Parameter SymbolNotation

Optional implementation data signal timing requirements for use with bit rates above 2 Mbit/s and up to 5 Mbit/s

Transmitted recessive bit width @ 5 Mbit/s

Transmitted recessive bit width @ 5 Mbit/s t

Received recessive bit width @ 5 Mbit/s

Maximum ratings of V

Maximum rating V

Diff

General maximum rating V

CAN_H

CAN_H

, V

Optional: Extended maximum rating V

CAN_L

and V

and V

CAN_L

CAN_H

Diff

and V

CAN_L

Maximum leakage currents on CAN_H and CAN_L, unpowered

Leakage current on CAN_H, CAN_L

Bus biasing control timings

CAN activity filter time, long

CAN activity filter time, short t

Wake−up timeout, short t

Wake−up timeout, long t

Timeout for bus inactivity (Required for selective wake−up implementation only) t

Bus Bias reaction time (Required for selective wake−up implementation only) t

t

Bit(Bus)

Bit(RXD)

Dt

Rec

V

Diff

V

CAN_H

V

CAN_L

V

CAN_H

V

CAN_L

I

CAN_H

I

CAN_L

t

Filter

Filter

Wake

Wake

Silence

Bias

V

t

Bit(Vi(diff))

t

Bit(RxD)

Dt

Rec

CANH−CANL

V

CANH

V

CANL

NA

I

LI

t

wake_filt

NA

NA

t

wake_to

NA

NA

ORDERING INFORMATION

Device Description Package Shipping

NCV7446MW0R2G Dual CAN FD Transceiver, High Speed, Low Power DFNW14

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

5000 / Tape & Reel

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12

DFNW14 4.5x3, 0.65P

8

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

1

SCALE 2:1

D

PIN ONE

REFERENCE

TOP VIEW

DETAIL B

C
C

SIDE VIEW

NOTE 4

0.08

C0.10

C

DETAIL A

D2

1

14

K

e

BOTTOM VIEW

RECOMMENDED

SOLDERING FOOTPRINT*

4.35

4.23

14

3.60

1.75

1

0.65

PITCH

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

14X

0.33

DIMENSIONS: MILLIMETERS

A B

E

A

E2

b

0.10

0.05

8

7

SEATING

C

PLANE

14X

M

C AB

M

C

14X

0.75

PACKAGE

OUTLINE

L

NOTE 3

A3

7

8

14X

CASE 507AC

ISSUE D

LL

DETAIL A

A1

A4

DETAIL B

A4

PLATED
SURFACES

SECTION C−C

ALTERNATE

CONSTRUCTION

EXPOSED

COPPER

PLATING

L3

DATE 03 JUL 201

NOTES:

L3L3

1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMESNION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN

0.15 AND 0.30 MM FROM TERMINAL.

4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.

5. THIS DEVICE CONTAINS WETTABLE FLANK
DESIGN FEATURES TO AID IN FILLET FOR­MATION ON THE LEADS DURING MOUNTING.

MILLIMETERS

DIM MIN NOM

A 0.80 0.85

A1 −−− −−−
A3
A4

0.10 −−− −−−

b 0.25 0.30
D

4.40 4.50

D2 4.13 4.20

E

2.90 3.00

E2 1.53 1.60

e 0.65 BSC

K
L 0.35 0.40

L3

0.00 0.05 0.10

0.20 REF

0.30 REF

MAX

0.90

0.05

0.35

4.60

4.27

3.10

1.67

0.45

GENERIC

MARKING DIAGRAM*

XXXXX
XXXXX

AYWWG

G

XXXXX = Specific Device Code
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package

(*Note: Microdot may be in either location)

*This information is generic. Please refer to

device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”, may
or may not be present. Some products may
not follow the Generic Marking.

DOCUMENT NUMBER:

DESCRIPTION:

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ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.

© Semiconductor Components Industries, LLC, 2018

98AON14979G
DFNW14 4.5x3, 0.65P

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

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