ON Semiconductor NCV7446 User Manual

Dual CAN FD Transceiver, High Speed, Low Power

NCV7446

Description

NCV7446 is a dual CAN FD physical layer transceiver. It allows interfacing of two independent CAN physical buses and two independent CAN protocol controllers. The transceivers provide differential transmit capability to the bus and differential receive capability to the CAN controllers.

It is consisted of two fully independent NCV7344 transceivers. The NCV7446 guarantees additional timing parameters to ensure robust communication at data rates beyond 1 Mbps to cope with CAN flexible data rate requirements (CAN FD). These features make the NCV7446 an excellent choice for all types of HS−CAN networks, in nodes that require a low−power mode with wake−up capability via the CAN bus.

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DFNW14

CASE 507AC

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MARKING DIAGRAM

NV74

46−0

ALYW

Features

• Compliant with the ISO 11898−2:2016

• CAN FD Timing Specified up to 5 Mbps

• Very Low Current Standby Mode with Wake−up via the Bus

• Low Electromagnetic Emission (EME) and High Electromagnetic

Immunity

• No Disturbance of the Bus Lines with an Un−powered Node

• Transmit Data (TxD) Dominant Timeout Function

• Under All Supply Conditions the Chip Behaves Predictably

• Very High ESD Robustness of Bus Pins

• Thermal Protection

• Bus Pins Short Circuit Proof to Supply Voltage and Ground

• Bus Pins Protected Against Transients in an Automotive

Environment

Quality

• Wettable Flank Package for Enhanced Optical Inspection

• AEC−Q100 Qualified and PPAP Capable

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

Typical Applications

• Automotive

• Industrial Networks

NV7446−0 = Specific Device Code A = Assembly Site L = Wafer Lot Y = Year of Production, Last Number W = Work Week Number G = Pb−Free Package

PIN CONNECTIONS

TxD1

GND1

VCC1

RxD1

TxD2

GND2

VCC2

NCV7446

STB1

CANH1

CANL1

STB2

CANH2

CANL2

RxD2

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet.

December, 2019 − Rev. 2

1 Publication Order Number:

NCV7446/D

NCV7446

BLOCK DIAGRAM

CC1

NCV7446

TxD1

STB1

RxD1

GND1

Thermal

CC 1

Timer

Mode &

Wake −up

control

shutdown

Driver control

Wake −up

Filter

COMP

CANH1

CANL1

Channel 1

TxD2

GND2

CC2

Figure 1. NCV7446 Block Diagram

Channel2

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STB2

CANH2

CANL2

RxD2

NCV7446

TYPICAL APPLICATION DIAGRAM

VBAT

IN OUT

5V −reg

Micro−

controller

GND

STB1

TxD1

RxD1

STB2

TxD2

RxD2

CC1

NCV7446

GND1

GND2

CC2

CANH1

CAN

BUS

CANL1

CANH2

CAN

BUS

CANL2

Figure 2. NCV7446 Application Diagram

Table 1. PIN FUNCTION DESCRIPTION

Pin Number Pin Name Description

1 TxD1

2 GND1 Ground for channel 1

3 V

4 RxD1

5 TxD2

6 GND2 Ground for channel 2

7 V

8 RxD2

9 CANL2 Low−level CAN bus line channel 2 (low in dominant mode)

10 CANH2 High−level CAN bus line channel 2 (high in dominant mode)

11 STB2 Standby mode control input for channel 2; internal pull−up current

12 CANL1 Low−level CAN bus line channel 1 (low in dominant mode)

13 CANH1 High−level CAN bus line channel 1 (high in dominant mode)

14 STB1 Standby mode control input for channel 1; internal pull−up current

EP Exposed Pad Recommended to connect to GND or left floating in application

CC1

CC2

Transmit data input for channel 1; low input Ù dominant driver; internal pull−up current

Supply voltage for channel 1

Receive data output for channel 1; dominant transmitter Ù low output

Transmit data input for channel 2; low input Ù dominant driver; internal pull−up current

Supply voltage for channel 2

Receive data output for channel 2; dominant transmitter Ù low output

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NCV7446

FUNCTIONAL DESCRIPTION

Operating Modes

NCV7446 provides two modes of operation per transceiver as illustrated in Table 2. These modes are selectable through pins STB1 and STB2 independently for each transceiver.

Table 2. OPERATING MODES

Pins

STBx

Low Normal

High Standby

Normal Mode

Mode Pins RxDx

Low when bus dominant

Follows the bus when wake−up detected

High when bus recessive

High when no wake−up request detected

In the normal mode, the selected transceiver is able to communicate via the bus lines. The signals are transmitted and received to the CAN controller via the pins TxDx and RxDx. The slopes on the bus lines outputs are optimized to give low EME.

wake_filt

Standby Mode

In standby mode both the transmitter and receiver are disabled and a very low−power differential receiver monitors the bus lines for CAN bus activity. The bus lines are biased to ground and supply current is reduced to a minimum. When a wake−up request is detected by the low−power differential receiver, the signal is first filtered and then verified as a valid wake signal after a time period of t

wake_filt, the corresponding RxDx pin is driven low by the

transceiver (following the bus) to inform the controller of the wake−up request.

Wake−up

When a valid wake−up pattern (phase in order dominant − recessive − dominant) is detected during the standby mode the RxDx pins follows the bus. Minimum length of each phase is t

wake_filt

Pattern must be received within t

– see Figure 3.

to be recognized

wake_to

as valid wake−up otherwise internal logic is reset.

wake_filt

CANHx

CANLx

RxDx

wake_to

Figure 3. NCV7446 Wake−up behavior

dwakerdtdwakedr

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NCV7446

Overtemperature Detection

A thermal protection circuit protects the IC from damage

by switching off the affected transmitter if the junction temperature exceeds a value of approximately 170°C. Because the transmitter dissipates most of the power, the power dissipation and temperature of the IC is reduced. All other IC functions continue to operate. The transmitter off−state resets when the temperature decreases below the shutdown threshold and pins TxDx goes high. The thermal protection circuit is particularly needed when a bus line short circuits.

TxDx Dominant Timeout Function

A TxD dominant timeout timer circuit prevents the bus lines being driven to a permanent dominant state (blocking all network communication) if pins TxDx are forced permanently low by a hardware and/or software application failure. The timer is triggered by a negative edge on pins TxDx. If the duration of the low−level on pins TxDx exceeds the internal timer value t

dom(TxD)

, the transmitter is disabled, driving the bus into a recessive state. The timer is reset by a positive edge on pins TxDx.

This TxD dominant timeout time t

dom(TxD)

defines

the minimum possible bit rate to 17 kbps.

Fail Safe Features

A current−limiting circuit protects the transmitter output stage from damage caused by accidental short circuit to either positive or negative supply voltage, although power dissipation increases during this fault condition.

Undervoltage on V sending data on the bus when there is not enough V

CC1

or V

pins prevents the chip

CC2

supply

voltage.

After supply is recovered, corresponding TxD pin must be first released to high to allow sending dominant bits again. Recovery time from undervoltage detection is equal to td(stb−nm) time.

The pins CANHx and CANLx are protected from automotive electrical transients (according to ISO 7637; see Figure 5). Pins TxDx and STBx are pulled high internally should the input become disconnected. Pins TxDx, STBx and RxDx will be floating, preventing reverse supply should the adjacent VCCx supply be removed.

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