ON Semiconductor NCV47822 User Manual

NCV47822

Dual High Side Switch with
Adjustable Current Limit and
Diagnostic Features

The NCV47822 dual channel High Side Switch (HSS) with 250 mA
per channel is designed for use in harsh automotive environments. The
device has a h igh p eak i nput v oltage t olerance a nd r everse i nput v oltage,
reverse bias, overcurrent and overtemperature protections. The
integrated current sense feature (adjustable by resistor connected to
CSO pin for each channel) provides diagnosis and system protection
functionality. The CSO pin output current creates voltage drop across
CSO resistor which is proportional to output current of each channel.
Extended diagnostic features in OFF state are also available and
controlled by dedicated input and output pins.

Features

• Output Current per Channel: up to 250 mA

• Two Independent Enable Inputs (3.3 V Logic Compatible)

• Adjustable Current Limits: up to 350 mA

• Protection Features:

♦ Current Limitation
♦ Thermal Shutdown
♦ Reverse Input Voltage and Reverse Bias Voltage

• Diagnostic Features:

♦ Short To Battery (STB) and Open Load (OL) in OFF State
♦ Internal Components for OFF State Diagnostics
♦ Open Collector Flag Output
♦ Two Output Voltage Monitoring Outputs (Analog)

• AEC−Q100 Grade 1 Qualified and PPAP Capable

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

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MARKING
DIAGRAM

14

14

TSSOP−14

Exposed Pad

1

CASE 948AW

NCV4

7822

ALYWG

G

1

A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package

(Note: Microdot may be in either location)

ORDERING INFORMATION

See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.

Typical Applications

• Audio and Infotainment System

• Active Safety System

V

and V

out_FB2

in

DE

CS

EN2

are sensed V

NCV47822

(Dual HSS)

out1

C

in

1 μF

Diagnostic Enable Input

Diagnostic Channel Select Input

* V

out_FB1

Figure 1. Application Schematic

(See Application Section for More Details)

© Semiconductor Components Industries, LLC, 2016

May, 2016 − Rev. 0

V

out1

V

out_FB1

CSO1EN1

C

EF

V

out2

V

out_FB2

CSO2

GND

and V

C

output voltages, respectively, via internal resistor dividers

out2

1 μF

1 μF

CSO1

CSO2

Proportional Voltage to V

R

CSO1

Error Flag Output (Open Collector)

Proportional Voltage to V

R

CSO2

C

out1

*

out1

1 μF

C

out2

*

out2

1 μF

1 Publication Order Number:

NCV47822/D

NCV47822

I

10 mA

PU1

V

EN1

DE
CS

in

VOLTAGE

REFERENCE

R

PD_EN1

780 kΩ

ENABLE

SATURATION

PROTECTION

THERMAL

SHUTDOWN

PD_CS

EN1
EN2

R

780 kΩ

OC1_ON
OC2_ON

R

780 kΩ

STB1_OL1_OFF
STB2_OL2_OFF

PD_DE

IPU1_ON

V

REF

V

REF _OFF

EN1

PD1_ON

DIAGNOSTIC

CONTROL

LOGIC

PASS DEVICE 1

AND

CURRENT MIRROR

STB1_OL1_OFF

IPU1_ON
IPU2_ON

PD1_ON
PD2_ON

I

PU2

10 mA

OC1_ON

I

CSO1

= I

out1

/ RATIO*

+

−

+

0.95x

−

V

+

V

−

V

REF

2.55 V

REF

500 kΩ

100 kΩ

REF_OFF

V

out1

CSO1

R

PD11

V

R

PD12

out_FB1

EF

EN2

GND

V

in

R

PD_EN2

780 kΩ

ENABLE

SATURATION

PROTECTION

THERMAL

SHUTDOWN

IPU2_ON

EN2

PD2_ON

PASS DEVICE 2

AND

CURRENT MIRROR

OC2_ON

STB2_OL2_OFF

I

CSO2

= I

out2

+

−

+

−

+

−

/ RATIO*

V

REF

2.55 V

0.95x
V

REF

V

REF_OFF

R

PD21

500 kΩ

R

PD22

100 kΩ

V

out2

CSO2

V

out_FB2

*) for current value of RATIO see
into Electrical Characteristic Table

Figure 2. Simplified Block Diagram

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2

NCV47822

411

V

in

CSO1

EN1

GND

EPAD

EN2

CSO2

V

in

TSSOP−14 EPAD

(Top View)

Figure 3. Pin Connections

Table 1. PIN FUNCTION DESCRIPTION

Pin No.

TSSOP−14

EPAD

1 V

2 CSO1 Current Sense Output 1, Current Limit setting and Output Current value information. See Application

3 EN1 Enable Input 1; low level disables the Channel 1. (Used also for OFF state diagnostics control for

4 GND Power Supply Ground.
5 EN2 Enable Input 2; low level disables the Channel 2. (Used also for OFF state diagnostics control for

6 CSO2 Current Sense Output 2, Current Limit setting and Output Current value information. See Application

7 V
8 V

9 V
10 DE Diagnostic Enable Input.
11 EF Error Flag (Open Collector) Output. Active Low.
12 CS Channel Select Input for OFF state diagnostics. Set CS = Low for OFF state diagnostics of Chan-

13 V
14 V

EPAD EPAD Exposed Pad is connected to Ground. Connect to GND plane on PCB.

Pin Name Description

in

Power Supply Input for Channel 1 and supply of control circuits of whole chip. At least 4.4 V power
supply must be used for proper IC functionality.

Section for more details.

Channel 1)

Channel 2)

Section for more details.

in

out2

out_FB2

Power Supply Input for Channel 2. Connect to pin 1 or different power supply rail.
Output Voltage 2.
Output Voltage 2 Analog Monitoring. See Application Section for more details.

nel 1. Set CS = High for OFF state diagnostics of Channel 2. Corresponding EN pin has to be used
for diagnostics control (see Application Information section for more details).

out_FB1

out1

Output Voltage 1 Analog Monitoring. See Application Section for more details.
Output Voltage 1.

V

out1

V

out_FB1

CS
EF
DE
V

out_FB2

V

out2

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NCV47822

Table 2. MAXIMUM RATINGS

Rating Symbol Min Max Unit

Input Voltage DC V
Input Voltage (Note 1)

Load Dump − Suppressed
Enable Input Voltage V
Output Voltage Monitoring V
CSO Voltage V
DE, CS and EF Voltages VDE, VCS, V
Output Voltage V
Junction Temperature T
Storage Temperature T

in

U

s*

EN1,2

out_FB1,2

CSO1,2

out1,2

J

STG

EF

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.

1. Load Dump Test B (with centralized load dump suppression) according to ISO16750−2 standard. Guaranteed by design. Not tested in
production. Passed Class A according to ISO16750−1.

Table 3. ESD CAPABILITY (Note 2)

Rating

ESD Capability, Human Body Model ESD

2. This device series incorporates ESD protection and is tested by the following methods:

ESD Human Body Model tested per AEC−Q100−002 (JS−001−2010)

Field Induced Charge Device Model ESD characterization is not performed on plastic molded packages with body sizes < 50 mm2 due
to the inability of a small package body to acquire and retain enough charge to meet the minimum CDM discharge current waveform
characteristic defined in JEDEC JS−002−2014.

Symbol Min Max Unit

HBM

Table 4. MOISTURE SENSITIVITY LEVEL (Note 3)

Rating

Moisture Sensitivity Level MSL 1 −

3. For more information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D

Symbol Min Max Unit

THERMAL CHARACTERISTICS (Note 4)

Rating

Thermal Characteristics (single layer PCB)

Thermal Resistance, Junction−to−Air (Note 5)
Thermal Reference, Junction−to−Lead (Note 5)

Thermal Characteristics (4 layers PCB)

Thermal Resistance, Junction−to−Air (Note 5)
Thermal Reference, Junction−to−Lead (Note 5)

4. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.

5. Values based on copper area of 645 mm

2

(or 1 in2) of 1 oz copper thickness and FR4 PCB substrate. Single layer − according to JEDEC51.3,

4 layers − according to JEDEC51.7

Symbol Value Unit

R

θJA

R

ψJL

R

θJA

R

ψJL

Table 5. RECOMMENDED OPERATING RANGES

Rating Symbol Min Max Unit

Input Voltage (Note 6) V
Output Current Limit (Note 7) I
Junction Temperature T
Current Sense Output (CSO) Capacitor C

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.

6. Minimum V

7. Corresponding R

= 4.4 V or (V

in

CSO1,2

+ 0.5 V), whichever is higher.

out1,2

is in range from 76.5 kW down to 2185 W.

in

LIM1,2

J

CSO1,2

−42 45 V

− 60

−42 45 V

−0.3 10 V

−0.3 7 V

−0.3 7 V

−1 40 V

−40 150 °C

−55 150 °C

−2 2 kV

°C/W

52

9.0
°C/W

31
10

4.4 40 V
10 350 mA

−40 150 °C
1 4.7

V

mF

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NCV47822

Table 6. ELECTRICAL CHARACTERISTICS V

= 1 mF, Min and Max values are valid for temperature range −40°C v TJ v +150°C unless noted otherwise and are guaranteed by

C

out1,2

test, design or statistical correlation. Typical values are referenced to T

Parameter

= 13.5 V, V

in

= 3.3 V, VDE = 0 V, R

EN1,2

= 25°C (Note 8)

J

CSO1,2

= 0 W, C

= 1 mF, Cin = 1 mF,

CSO1,2

Test Conditions Symbol Min Typ Max Unit

OUTPUTS

Input to Output Differential Voltage

Vin = 8 V to 18 V
I

= 200 mA

out1,2

= 250 mA

I

out1,2

V

in−out1,2

−

−

210
230

350
400

mV

CURRENT LIMIT PROTECTION

Current Limit

Vin − 1 V I

out1,2

LIM1,2

350 − − mA

=

V

DISABLE AND QUIESCENT CURRENTS

Disable Current
Quiescent Current, Iq = Iin − (I
Quiescent Current, Iq = Iin – (I
Quiescent Current, Iq = Iin – (I

out1
out1
out1

+I
+I
+I

out2
out2
out2

)
) I
) I

= 0 V I

EN1,2

I

= I

out1
out1
out1

= 500 mA, Vin = 8 V to 18 V

out2

= I

= 200 mA, Vin = 8 V to 18 V I

out2

= I

= 250 mA, Vin = 8 V to 18 V I

out2

DIS

I

q
q
q

− 0.005 10

mA

− 0.85 1.5 mA

− 15 25 mA

− 20 40 mA

V

ENABLE

Enable Input Threshold Voltage

Logic Low (OFF)

Logic High (ON)
Enable Input Current V
Turn On Time

from Enable ON to V

out1,2

= Vin − 1 V

v

V
V

I

0.1 V

out1,2

w

Vin − 1 V

out1,2

= 3.3 V I

EN1,2

= 100 mA t

out1,2

V

th(EN1,2)

EN1,2

on

0.99

−

1.8

1.9

2 7 20

− 25 −

−

2.31

V

mA

ms

OUTPUT CURRENT SENSE

CSO Voltage Level at Current Limit

CSO Transient Voltage Level

Output Current to CSO Current Ratio

CSO Current at no Load Current

= Vin − 1 V

out1,2

= 3.3 kW

R

CSO1,2

C

= 4.7 mF, R

CSO1,2

pulse from 10 mA to 350 mA, tr = 1 ms
V

= 2 V, I

CSO1,2

V

= 8 V to 18 V, −40°C v TJ v +150°C)

in

V

CSO1,2

V

= 8 V to 18 V, −40°C v TJ v +150°C)

in

V

CSO1,2

= 2 V, I

= 0 V, I

out1,2

out1,2

out1,2

= 3.3 kW, I

CSO1,2

= 10 mA to 50 mA

= 50 mA to 350 mA

= 0 mA

out1,2

V

CSO_I

V

CSO1,2

I

out1,2

I

CSO1,2

I

CSO_off1,2

lim1,2

/

2.448

2.55 2.652

(−4%)

− − 3.3

−

265 −

(−15%)

−

285 −

(−5%)

− − 15

(+4%)

V

V

−

(+15%)

(+5%)

mA

V

DIAGNOSTICS

V

Overcurrent Voltage Level Threshold

Short To Battery (STB) Voltage
Threshold in OFF state

Open Load (OL) Current Threshold

= Vin − 1 V,

out1,2

= 3.3 kW

R

CSO1,2

Vin = 4.4 V to 18 V, I
V

= 3.3 V

DE

out1

= I

out2

= 0 mA,

Vin = 4.4 V to 18 V, VDE = 3.3 V I

in OFF state
Output Voltage to Output Feedback

Vin = 4.4 V to 18 V V

Voltage Ratio
Diagnostics Enable Threshold Voltage

Logic Low

Logic High
Channel Select Threshold Voltage

Logic Low

Logic High
Error Flag Low Voltage IEF = −1 mA V

V

OC1,2

V

STB1,2

OL1,2

out1,2/

V

out_FB1,2

V

th(DE)

V

th(CS)

EF_Low

92 95 98 % of

V

Ilim1,2

2 3 4 V

5.0 10 25 mA

5.7 6.0 6.3 −

0.99

−

0.99

−

1.8

1.9

1.8

1.9

−

2.31

−

2.31

− 0.04 0.4 V

CSO_

V

V

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.

8. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at T

cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.

[ TJ. Low duty

A

9. Values based on design and/or characterization.

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NCV47822

Table 6. ELECTRICAL CHARACTERISTICS V

= 1 mF, Min and Max values are valid for temperature range −40°C v TJ v +150°C unless noted otherwise and are guaranteed by

C

out1,2

test, design or statistical correlation. Typical values are referenced to T

= 13.5 V, V

in

= 3.3 V, VDE = 0 V, R

EN1,2

= 25°C (Note 8)

J

CSO1,2

= 0 W, C

= 1 mF, Cin = 1 mF,

CSO1,2

Parameter UnitMaxTypMinSymbolTest Conditions

THERMAL SHUTDOWN

Thermal Shutdown Temperature (Note 9)

out1

sured separately

= 90 mA, each channel mea-

out2

T

SD1,2

150 175 195 °C

I

= I

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.

8. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at T

cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.

[ TJ. Low duty

A

9. Values based on design and/or characterization.

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NCV47822

TYPICAL CHARACTERISTICS

400
350

300
250
200
150

, INPUT TO OUTPUT

100

in−out1,2

V

50

DIFFERENTIAL VOLTAGE (mV)

0

900
850

800
750
700

Vin = 13.5 V

I

out1,2

I

out1,2

I

= 350 mA

= 200 mA

out1,2

= 15 mA

60 100 160

TJ, JUNCTION TEMPERATURE (°C)

Figure 4. Input to Output Differential vs.

Temperature

V

out1,2

= (Vin − 1 V) V

TJ = 25°C

TJ = 150°C

TJ = −40°C

400

Vin = 13.5 V

350

TJ = 150°C

300
250

TJ = 25°C

200
150

, INPUT TO OUTPUT

TJ = −40°C

100

in−out1,2

V

50

DIFFERENTIAL VOLTAGE (mV)

1401208040200−20−40

0

I

, OUTPUT CURRENT (mA)

out1,2

300250200 350150100500

400

Figure 5. Input to Output Diff. vs. Output

Current

0

TJ = 25°C
R

= 3.3 kW

out1,2

−1

−2

−3
650
600

, OUTPUT CURRENT LIMIT (mA)

550

LIM1,2

I

500

V

, INPUT VOLTAGE (V)

IN

Figure 6. Output Current Limit vs. Input

Voltage

400
350

300
250
200
150
100

, OUTPUT CURRENT LIMIT (mA)

50

LIM1,2

I

0

10 20 35 45 60 65

R

CSO1,2

Figure 8. Output Current Limit vs. R

(Calculated Using E24 Series)

(kW)

−4

, INPUT CURRENT (mA)

in

I

−5

−6

40

35302520151050

45

V

, INPUT VOLTAGE (V)

IN

−10 0

−5−15−20−25−30−35−40−45

Figure 7. Output Voltage vs. Input Voltage

(Reverse Input Voltage)

3.0
TJ = −40°C to 150°C

2.5

, = 10 mA to 350 mA

I

LIM1,2

2.0

1.5

, CSO VOLTAGE (V)

1.0

CSO1,2

V

0.5

0

55504030251550

70 75 80

CSO

20 60 90 110

, OUTPUT CURRENT (% of I

I

out1,2

Figure 9. Output Current (% of I

LIM

1008070504030100

)

LIM1,2

) vs. CSO

Voltage

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NCV47822

TYPICAL CHARACTERISTICS

1.6
TJ = 25°C

1.5

1.5

= 13.5 V

V

in

1.3

1.2

1.1

1.0

0.9

, QUIESCENT CURRENT (mA)

q

0.8

I

0.7

I

, OUTPUT CURRENT (mA) I

out1,2

Figure 10. Quiescent Current vs. Output

Current (Low Load)

151050

310

TJ = 25°C

305
300

= 13.5 V

V

in

295
290
285
280
275

, OUTPUT CURRENT

270

CSO1,2

265

/I

260

TO CSO CURRENT RATIO (−)

out1,2

255

I

250

I

out1,2

Figure 12. I

40

TJ = 25°C

35

= 13.5 V

V

in

30
25
20
15
10

, QUIESCENT CURRENT (mA)

5

q

I

0

20

Figure 11. Quiescent Current vs. Output

, OUTPUT CURRENT (mA)

Current vs. Output Current

CSO

Ratio

, OUTPUT CURRENT (mA)

out1,2

Current (High Load)

100010010

350

300250200150100500

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NCV47822

DEFINITIONS

General

All measurements are performed using short pulse low
duty cycle techniques to maintain junction temperature as
close as possible to ambient temperature.

Input to Output Differential Voltage

The Input to Output Differential Voltage parameter is
defined for specific output current values and specified over
Temperature range.

Quiescent and Disable Currents

Quiescent Current (Iq) is the difference between the input
current (measured through the LDO input pin) and the
output load current. If Enable pin is set to LOW the regulator
reduces its internal bias and shuts off the output, this term is
called the disable current (I

DIS

).

Current Limit

Current Limit is value of output current by which output

voltage drops below 90% of its nominal value.

Thermal Protection

Internal thermal shutdown circuitry is provided to protect
the integrated circuit in the event that the maximum junction
temperature is exceeded. When activated at typically 175°C,
the regulator turns off. This feature is provided to prevent
failures from accidental overheating.

Maximum Package Power Dissipation

The power dissipation level is maximum allowed power
dissipation for particular package or power dissipation at
which the junction temperature reaches its maximum
operating value, whichever is lower.

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NCV47822

APPLICATIONS INFORMATION

Circuit Description

The NCV47822 is an integrated dual High Side Switch
(HSS) with output current capability up to 250 mA per each
output. It is enabled with an input to the enable pin. The
integrated current sense feature provides diagnosis and
system protection functionality. The current limit of the
device is adjustable by resistor connected to CSO pin.
Voltage on CSO pin is proportional to output current. The
HSS is protected by both current limit and thermal
shutdown. Thermal shutdown occurs above 150°C to
protect the IC during overloads and extreme ambient
temperatures.

Enable Inputs

An enable pin is used to turn a channel on or off. By
holding the pin down to a voltage less than 0.99 V, the output
of the channel will be turned off. When the voltage on the
enable pin is greater than 2.31 V, the output of the channel
will be enabled to power its output to the regulated output
voltage. The enable pins may be connected directly to the
input pin to give constant enable to the output channel.

Setting the Output Current Limit

The output current limit can be set up to 350 mA by
external resistor R
1 mF in parallel with R

(see Figure 1). Capacitor C

CSO1,2

is required for stability of current

CSO

CSO

of

limit control circuitry (see Figure 1).

V

CSO1,2

I

LIM1,2

R

CSO1,2

+ I

out1,2

+

+

ǒ

R

RATIO

1

RATIO

1

CSO1,2

R

RATIO

2.55

CSO1,2

2.55

I

LIM1,2

1

Ǔ

(eq. 1)

(eq. 2)

(eq. 3)

where

− current limit setting resistor

R

CSO1,2

V

 voltage at CSO pin proportional to I

CSO1,2

I

− current limit value

LIM1,2

I

− output current actual value

out1,2

out1,2

RATIO − typical value of Output Current to CSO

Current Ratio for particular output current
range

CSO pin provides information about output current actual
value. The CSO voltage is proportional to output current
according to Equation 1.

Once output current reaches its limit value (I

external resistor R

2.55 V. Calculations of I

than voltage at CSO pin is typically

CSO

or R

LIM1,2

CSO1,2

values can be

LIM1,2

) set by

done using equations Equation 2 and Equation 3,
respectively. Minimum and maximum value of Output
Current Limit can be calculated according Equation 4 and 5.

V

I

LIM1,2_min

I

LIM1,2_max

+ RATIO

+ RATIO

min

max

R

V

R

CSO1,2_min

CSO1,2_max

CSO1,2_max

CSO1,2_min

(eq. 4)

(eq. 5)

where

RATIO

− minimum value of Output Current to

min

CSO Current Ratio from electrical
characteristics table and particular output
current range

RATIO

− maximum value of Output Current to

max

CSO Current Ratio from electrical
characteristics table and particular output
current range

V

CSO1,2_min

 minimum value of CSO Voltage Level at

Current Limit from electrical characteristics
table

V

CSO1,2_max

 maximum value of CSO Voltage Level at

Current Limit from electrical characteristics
table

R

CSO1,2_min

− minimum value of R

CSO1,2

with respect

its accuracy

R

CSO1,2_max

− maximum value of R

CSO1,2

with respect

its accuracy

Designers should consider the tolerance of R

CSO1,2

during the design phase.

Diagnostic in OFF State

The NCV47822 contains also circuitry for OFF state
diagnostics for Short to Battery (STB) and Open Load (OL).
There are internal current sources and Pull Down resistors
which provide additional cost savings for overall application

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NCV47822

by excluding external components and their assembly cost
and saving PCB space and safe control IOs of a
Microcontroller Unit (MCU).

Simplified functional schematic and truth table is shown

in Figure 13 and related flowchart in Figure 14.

Current source enabled via EN and DE pins

I

PU

PASS DEVICE is OFF in Diagnostics

state(DE =H).

Mode in OFF state

out

> V

out

out_OFF

< V

out

out_OFF

> V

out

out_OFF

< V

out

out_OFF

+

V

−

REF_OFF

Diagnostic Status/Action

Short to Battery (STB)

Check for Open Load (OL)

Open Load (OL)

No Failure (V

close to 0 V)

out

V

R

PD1

R

PD2

Digital Diagnostics:
to MCU’s digital input
with pull−up resistor
to MCU’s DIO supply rail

out

EF

V

in

Comparator active only in Diagnostic

EN
DE

EN – Enable (Logic Input)
DE – Diagnostics Enable(Logic Input)
EF– Error Flag Output(Open Collector Output)

EN DE IPUEF V

L L OFF HZ Unknown None (Diagnostics OFF)

L H OFF L V

L H OFF HZ V

HHONLV

H H ON HZ V

Figure 13. Simplified Functional Diagram of OFF

State Diagnostics (STB and OL)

Start

Diag. OFF. Set

EN = L & DE = L

Diag. ON. Set

EN = L & DE = H

HZ

EF = ?

L

IPU ON. Set

EN = H & DE = H

HZ

EF = ?

L

No Failure Open Load Short to Battery

Figure 14. Flowchart for Diagnostics in OFF State

The diagnostics in OFF state shall be performed for each
channel separately. For diagnostics of Channel 1 the input
CS pin has to be put logic low, for diagnostics of Channel 2
the input CS pin has to be put logic high. Corresponding EN
pin has to be used for control (EN1 for Channel 1 and EN2
for Channel 2).

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11

NCV47822

Diagnostic in ON State

Diagnostic in ON State provides information about
Overcurrent or Short to Ground failures, during which the
EF output is in logic low state. The diagnostics in ON state
shall be performed for each channel separately. For
diagnostics of Channel 1 the input CS pin has to be put logic
low, for diagnostics of Channel 2 the input CS pin has to be
put logic high. For detailed information see Diagnostic
Features Truth Table in Figure 15.

Output Voltage Monitoring

The Output Voltage net is connected to internal resistor
divider. Output of the resistor divider is connected to
V

out_FB1,2

pin and provides information about Output

Voltage Level according to Equation 4.

V

V

out_FB1,2

+

out1,2

6

(eq. 6)

Figure 15. Diagnostic Features Truth Table

10.State of EN pin of appropriate channel

11.CS = L means CH1 diagnostics and CS = H means CH2 diagnostics in OFF state (DE = H) via EF output, appropriate EN pin is used for
turning internal switch ON and OFF (e.g. when DE = H and CS = L and EN1 = L then IPU1 is OFF, when DE = H and CS = L and EN1 =
H then IPU1 is ON)

12.Internal current source turned OFF (between V

13.Internal current source turned ON (between V

14.CS = L means CH1 diagnostics and CS = H means CH2 diagnostics in ON state (e.g. when CS = L and EF = L then CH1 has Overcurrent
or Short to Ground failure, when CS = H and EF = L then CH1 has Overcurrent or Short to Ground failure)

out

out

and V

and V

of appropriate channel)

in

of appropriate channel)

in

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12

NCV47822

Thermal Considerations

As power in the device increases, it might become
necessary to provide some thermal relief. The maximum
power dissipation supported by the device is dependent
upon board design and layout. Mounting pad configuration
on the PCB, the board material, and the ambient temperature
affect the rate of junction temperature rise for the part. When
the device has good thermal conductivity through the PCB,
the junction temperature will be relatively low with high
power applications. The maximum dissipation the device
can handle is given by:

P

D(MAX)

+

ƪ

T

J(MAX)

R

qJA

* T

ƫ

A

(eq. 7)

Since TJ is not recommended to exceed 150°C, then the

2

device soldered on 645 mm
dissipate up to 2.38 W when the ambient temperature (T
is 25°C. See Figure 16 for R

, 1 oz copper area, FR4 can

versus PCB area. The power

JA

q

A

dissipated by the device can be calculated from the
following equations:

(eq. 8)

PD[ V

in

ǒ

Iq@I

out1,2

Ǔ

) I

out1

ǒ

Vin−V

out1

Ǔ

) I

out2

ǒ

Vin−V

out2

or

(eq. 9)

V

in(MAX)

[

P

D(MAX)

)

ǒ

V

out1

I

out1

I
) I

out1

out2

Ǔ)ǒ

) I

I

out2

Ǔ

V

out2

q

130
120
110
100

90
80
70
60

2 oz, Single Layer

50
40

, THERMAL RESISTANCE (°C/W)

JA

30

q

R

20

COPPER HEAT SPREADER AREA (mm2)

1 oz, Single Layer

1 oz, 4 Layer
2 oz, 4 Layer

600 7005004003002001000

Figure 16. Thermal Resistance vs. PCB Copper Area

)

Hints

Vin and GND printed circuit board traces should be as
wide as possible. When the impedance of these traces is
high, there is a chance to pick up noise or cause the regulator

Ǔ

to malfunction. Place external components, especially the
output capacitor, as close as possible to the device and make
traces as short as possible.

The Output V oltage Monitoring Output is high impedance
output (see Figure 2) and during OFF state diagnostics it
may be prone to couple a noise via PCB track or wire.
Disturbing may appear as Error Flag Output oscillation
when Output Voltage Level is close to Short to Battery
threshold. To improve robustness connect capacitor
(typically 10 nF) between each V
close as possible to the V

out_FB1,2

out_FB1,2

pins.

pin and GND as

ORDERING INFORMATION

Device Marking Package Shipping

NCV47822PAAJR2G Line1: NCV4

Line2: 7822

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D

TSSOP−14 Exposed Pad

(Pb−Free)

2500 / Tape & Reel

†

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13

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

14

TSSOP−14 EP

CASE 948AW

1

SCALE 1:1

NOTE 6

B

14 8

c1

NOTE 5

E1

E

c

PIN 1

REFERENCE

NOTE 6

0.05 C

0.10 C

14X

A

e

1

TOP VIEW

D

NOTE 4

14X

NOTE 3

b

0.10

7

C

2X 14 TIPS

A2

B A

0.20 C

A

SS

C

BA

SEATING
PLANE

B

c

B

SIDE VIEW

D2

H

E2

A1

NOTE 7

DETAIL A

BOTTOM VIEW

RECOMMENDED

SOLDERING FOOTPRINT*

3.40

3.06

1

0.65

PITCH

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

14X

1.15

6.70

14X

0.42

ISSUE C

b

b1

SECTION B−B

NOTE 8

DETAIL A

END VIEW

L

L2

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL BE

0.07 mm MAX. AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER RADI­US OF THE FOOT. MINIMUM SPACE BETWEEN PRO­TRUSION AND ADJACENT LEAD IS 0.07.

4. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED

0.15 mm PER SIDE. DIMENSION D IS DETERMINED AT
DATUM H.

5. DIMENSION E1 DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSIONS. INTERLEAD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.25 mm PER
SIDE. DIMENSION E1 IS DETERMINED AT DATUM H.

6. DATUMS A AND B ARE DETERMINED AT DATUM H.

7. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM

C

M

GAUGE
PLANE

THE SEATING PLANE TO THE LOWEST POINT ON THE
PACKAGE BODY.

8. SECTION B−B TO BE DETERMINED AT 0.10 TO 0.25 mm
FROM THE LEAD TIP.

MILLIMETERS

DIM MIN MAX

A −−−− 1.20
A1 0.05 0.15
A2 0.80 1.05

b 0.19 0.30

b1 0.19 0.25

c 0.09 0.20

c1 0.09 0.16

D 4.90 5.10
D2 3.09 3.62

E 6.40 BSC
E1 4.30 4.50
E2 2.69 3.22

0.65 BSCe

L 0.45 0.75

L2 0.25 BSC

M 0 8

__

GENERIC

MARKING DIAGRAM*

14

XXXX
XXXX

ALYWG

G

1

XXXX = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package

(Note: Microdot may be in either location)

*This information is generic. Please refer to

device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.

DATE 09 OCT 2012

DOCUMENT NUMBER:

DESCRIPTION:

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.

© Semiconductor Components Industries, LLC, 2019

98AON66474E

TSSOP−14 EP, 5.0X4.4

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

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