ON Semiconductor NCV47821 User Manual

NCV47821

LDO Regulator - Dual,

Adjustable Current Limit,
Diagnostic Features

3.3 V to 20 V

The NCV47821 dual channel LDO regulator with 200 mA per
channel is designed for use in harsh automotive environments. The
device has a high peak input voltage tolerance and reverse input voltage,
reverse bias, overcurrent and overtemperature protections. The
integrated current sense feature (adjustable by resistor connected to
CSO pin for each channel) provides diagnosis and system protection
functionality. The CSO pin output current creates voltage drop across
CSO resistor which is proportional to output current of each channel.
Extended diagnostic features in OFF state are also available and
controlled by dedicated input and output pins.

Features

• Adjustable Outputs: 3.3 V to 20 V ±3% Output Voltage

• Output Current per Channel: up to 200 mA

• Two Independent Enable Inputs (3.3 V Logic Compatible)

• Adjustable Current Limits: up to 300 mA

• Protection Features:

♦ Current Limitation
♦ Thermal Shutdown
♦ Reverse Input Voltage and Reverse Bias Voltage

• Diagnostic Features:

♦ Short To Battery (STB) and Open Load (OL) in OFF State
♦ Internal Components for OFF State Diagnostics
♦ Open Collector Flag Output

• AEC−Q100 Grade 1 Qualified and PPAP Capable

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

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MARKING
DIAGRAM

14

14

TSSOP−14

Exposed Pad

1

CASE 948AW

NCV4

7821

ALYWG

G

1

A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package

(Note: Microdot may be in either location)

ORDERING INFORMATION

See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.

Typical Applications

• Audio and Infotainment System

• Active Safety System

GND

V

ADJ1

CSO1EN1

V

ADJ2

CSO2

out1

EF

out2

V

DE

CS

EN2

in

NCV47821

(Dual LDO)

C

in

1 μF

Diagnostic Enable Input

Diagnostic Channel Select Input

Cb1* and Cb2* are optional for stability with ceramic output capacitors

Figure 1. Application Schematic

(See Application Section for More Details)

© Semiconductor Components Industries, LLC, 2017

September, 2019 − Rev. 2

C

1 μF

C

1 μF

CSO1

CSO2

R11Cb1*

To A / D

R

CSO1

R

12

Error Flag Output (Open Collector)

R21Cb2*

To A / D

R

R

CSO2

22

C

out1

10 μF

C

out2

10 μF

1 Publication Order Number:

NCV47821/D

NCV47821

I

10 mA

PU1

EN1

DE
CS

V

in

VOLTAGE

REFERENCE

R

PD_EN1

780 kΩ

ENABLE

SATURATION

PROTECTION

THERMAL

SHUTDOWN

PD_CS

EN1
EN2

R

780 kΩ

OC1_ON
OC2_ON

PD_DE

R

780 kΩ

STB1_OL1_OFF
STB2_OL2_OFF

IPU1_ON

V

REF 1

V

REF 2

V

REF _OFF

EN1

DIAGNOSTIC

CONTROL

LOGIC

CURRENT MIRROR

PD1_ON

IPU1_ON
IPU2_ON

PD1_ON
PD2_ON

PASS DEVICE 1

AND

STB1_OL1_OFF

I

PU2

10 mA

OC1_ON

I

CSO1

= I

EA1

V

/ 100

out1

V

REF 2

+

2.55 V

−

out1

CSO1

+

0.95x

−

V

REF 2

R

PD11

500 kΩ

+

R

PD12

100 kΩ

V

−

REF_OFF

V

REF 1

+

1.265 V

−

ADJ1

EF

EN2

GND

V

in

R

PD_EN2

780 kΩ

SATURATION

PROTECTION

THERMAL

SHUTDOWN

IPU2_ON

EN2ENABLE

CURRENT MIRROR

PD2_ON

PASS DEVICE 2

AND

STB2_OL2_OFF

OC2_ON

I

CSO2

= I

EA2

V

/ 100

out2

V

REF 2

+

2.55 V

−

out2

CSO2

+

0.95x

−

V

REF 2

R

PD21

500 kΩ

+

R

PD22

100 kΩ

V

−

REF_OFF

V

REF 1

+

1.265 V

−

ADJ2

Figure 2. Simplified Block Diagram

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2

NCV47821

411

V

in

CSO1

EN1

GND

EN2

CSO2

V

in

EPAD

TSSOP−14 EPAD

(Top View)

Figure 3. Pin Connections

Table 1. PIN FUNCTION DESCRIPTION

Pin No.

TSSOP−14

EPAD

1 V

2 CSO1 Current Sense Output 1, Current Limit setting and Output Current value information. See Application

3 EN1 Enable Input 1; low level disables the Channel 1. (Used also for OFF state diagnostics control for

4 GND Power Supply Ground.

5 EN2 Enable Input 2; low level disables the Channel 2. (Used also for OFF state diagnostics control for

6 CSO2 Current Sense Output 2, Current Limit setting and Output Current value information. See Application

7 V

8 V

9 ADJ2 Adjustable Voltage Setting Input 2. See Application Section for more details.

10 DE Diagnostic Enable Input.

11 EF Error Flag (Open Collector) Output. Active Low.

12 CS Channel Select Input for OFF state diagnostics. Set CS = Low for OFF state diagnostics of Chan-

13 ADJ1 Adjustable Voltage Setting Input 1. See Application Section for more details.

14 V

EPAD EPAD Exposed Pad is connected to Ground. Connect to GND plane on PCB.

Pin Name Description

in

in

out2

out1

Power Supply Input for Channel 1 and supply of control circuits of whole chip. At least 4.4 V power
supply must be used for proper IC functionality.

Section for more details.

Channel 1)

Channel 2)

Section for more details.

Power Supply Input for Channel 2. Connect to pin 1 or different power supply rail.

Regulated Output Voltage 2.

nel 1. Set CS = High for OFF state diagnostics of Channel 2. Corresponding EN pin has to be used
for diagnostics control (see Application Information section for more details).

Regulated Output Voltage 1.

V

out1

ADJ1

CS

EF

DE

ADJ2

V

out2

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NCV47821

Table 2. MAXIMUM RATINGS

Rating Symbol Min Max Unit

Input Voltage DC V

Input Voltage (Note 1)

Load Dump − Suppressed

Enable Input Voltage V

ADJ Input Voltage V

CSO Voltage V

DE, CS and EF Voltages VDE, VCS V

Output Voltage V

Junction Temperature T

Storage Temperature T

in

U

s*

EN1,2

ADJ1,2

CSO1,2

out1,2

J

STG

EF

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.

1. Load Dump Test B (with centralized load dump suppression) according to ISO16750−2 standard. Guaranteed by design. Not tested in

production. Passed Class C according to ISO16750−1.

Table 3. ESD CAPABILITY (Note 2)

Rating

ESD Capability, Human Body Model ESD

2. This device series incorporates ESD protection and is tested by the following methods:

ESD Human Body Model tested per AEC−Q100−002 (JS−001−2010)

Field Induced Charge Device Model ESD characterization is not performed on plastic molded packages with body sizes < 50 mm2 due
to the inability of a small package body to acquire and retain enough charge to meet the minimum CDM discharge current waveform
characteristic defined in JEDEC JS−002−2014.

Symbol Min Max Unit

HBM

Table 4. LEAD SOLDERING TEMPERATURE AND MSL (Note 3)

Rating

Moisture Sensitivity Level MSL 1 −

3. For more information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D

Symbol Min Max Unit

THERMAL CHARACTERISTICS (Note 4)

Rating

Thermal Characteristics (single layer PCB)

Thermal Resistance, Junction−to−Air (Note 5)
Thermal Reference, Junction−to−Lead (Note 5)

Thermal Characteristics (4 layers PCB)

Thermal Resistance, Junction−to−Air (Note 5)
Thermal Reference, Junction−to−Lead (Note 5)

4. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.

5. Values based on copper area of 645 mm

2

(or 1 in2) of 1 oz copper thickness and FR4 PCB substrate. Single layer − according to JEDEC51.3,

4 layers − according to JEDEC51.7

Symbol Value Unit

R

θJA

R

ψJL

R

θJA

R

ψJL

Table 5. RECOMMENDED OPERATING RANGES

Rating Symbol Min Max Unit

Input Voltage (Note 6) V

Nominal Output Voltages V

Output Current Limit (Note 7) I

Junction Temperature T

Current Sense Output (CSO) Capacitor C

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.

6. Minimum V

7. Corresponding R

= 4.4 V or (V

in

CSO1,2

+ 0.5 V), whichever is higher.

out1,2

is in range from 25.5 kW down to 850 W.

in

out_nom1,2

LIM1,2

J

CSO1,2

−42 45 V

− 60

−42 45 V

−0.3 10 V

−0.3 7 V

−0.3 7 V

−1 40 V

−40 150 °C

−55 150 °C

−2 2 kV

°C/W

52

9.0

°C/W

31
10

4.4 40 V

3.3 20 V

10 300 mA

−40 150 °C

1 4.7

V

mF

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NCV47821

Table 6. ELECTRICAL CHARACTERISTICS V

= 10 mF, Min and Max values are valid for temperature range −40°C v TJ v +150°C unless noted otherwise and are guaranteed

C

out1,2

by test, design or statistical correlation. Typical values are referenced to T

Parameter

= 13.5 V, V

in

= 3.3 V, VDE = 0 V, R

EN1,2

= 25°C (Note 8)

J

CSO1,2

= 0 W, C

= 1 mF, Cin = 1 mF,

CSO1,2

Test Conditions Symbol Min Typ Max Unit

REGULATOR OUTPUTS

Output Voltage (Accuracy %) (Note 9)

Vin = V
I

out1,2

Line Regulation (Note 9) Vin = V

I

out1,2

Load Regulation Vin = (V

I

out1,2

Dropout Voltage (Note 10) V

out_nom1,2

V

DO1,2

to 40 V

in_min

= 5 mA to 200 mA

to (V

in_min

= 5 mA

out_nom1,2

= 5 mA to 200 mA

= Vin − V

= 5 V, I

out1,2

out_nom1,2

+ 8.5 V)

out1,2

+ 20 V)

= 200 mA

V

Reg

Reg

V

out1,2

line1,2

load1,2

DO1,2

−3 − +3

%

%

− 0.1 1.0

%

− 0.4 1.4

− 250 500 mV

DISABLE AND QUIESCENT CURRENTS

Disable Current

Quiescent Current, Iq = Iin − (I

Quiescent Current, Iq = Iin – (I

out1

out1

+I

+I

out2

out2

EN1,2

−40°C v T

) I

out1

) I

out1

= 0 V, V

v +125°C

J

= I

= 500 mA, Vin = (V

out2

= I

= 200 mA, Vin = (V

out2

out_nom1,2

= 5 V,

out_nom

out_nom

+ 8.5 V) I

+ 8.5 V) I

I

DIS

− 0.1 10

q

q

− 0.6 1.0 mA

− 15.5 25 mA

mA

V

CURRENT LIMIT PROTECTION

Current Limit

out1,2

Vin = (V

0.9 x V

out_nom1,2

out_nom1,2

+ 8.5 V)

I

LIM1,2

300 − − mA

=

V

PSRR & NOISE

Power Supply Ripple Rejection (Note 11)

f = 100 Hz, 0.5 V

p−p1,2

Output Noise Voltage (Note 11) f = 10 Hz to 100 kHz, C

= 10 nF V

b1,2

PSRR

n1,2

1,2

− 75 − dB

− 137 −

mV

rms

ENABLE

Enable Input Threshold Voltage

Logic Low (OFF)
Logic High (ON)

Enable Input Current V

Turn On Time

from Enable ON to 90 % of V

out

v

V
V

I
R

0.1 V

out1,2

w

0.9 x V

out1,2

= 3.3 V, V

EN1,2

= 100 mA, C

out1,2

= 82 kW, Rn2 = 27 kW

n1

out_nom1,2(Vout_nom1,2

out_nom1,2

= 10 nF,

b1,2

V

= 5 V)

= 5 V I

th(EN1,2)

EN1,2

t

on

0.99

−

1.8

1.9

2 8 20

− 1.7 −

−

2.31

V

mA

ms

OUTPUT CURRENT SENSE

CSO Voltage Level at Current Limit

CSO Transient Voltage Level

Output Current to CSO Current Ratio
(Note 11, 12)

Output Current to CSO Current Ratio
(Note 12)

CSO Current at no Load Current

= 0.9 x V

out1,2

(V

out_nom1,2

C

CSO1,2

pulse from 10 mA to 300 mA, tr = 1 ms

I

out1,2

V

CSO1,2

(V

out_nom1,2

V

CSO1,2

(V

out_nom1,2

V

CSO1,2

(V

out_nom1,2

out_nom1,2

= 5 V) R

= 4.7 mF, R

= 2 V, I

out1,2

= 5 V)

= 2 V, I

out1,2

= 5 V)

= 0 V, I

out1,2

= 5 V)

,

= 1 kW

CSO1,2

= 1 kW

CSO1,2

= 1 mA to 10 mA

= 10 mA to 300 mA

= 0 mA,

V

CSO_I

V

CSO1,2

I

out1,2

I

CSO1,2

I

out1,2

I

CSO1,2

I

CSO_off1,2

lim1,2

/

/

2.448

2.55 2.652

(−4%)

− − 3.3

−

98 −

(−5%)

−

100 −

(−5%)

− − 10

(+4%)

V

V

−

(+5%)

−

(+5%)

mA

V

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.

8. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at T
cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.

9. Minimum input voltage V

and Rn2 accuracy.

R

n1

10.Measured when the output voltage V

11.Values based on design and/or characterization.

is 4.4 V or (V

in_min

out_nom1,2

has dropped by 2% of V

out1,2

+ 1 V) whichever is higher. V

out_nom1,2

from the nominal valued obtained at Vin = V

out_nom1,2

measured at ADJ1,2 pin due to excluding

[ TJ. Low duty

A

+ 8.5 V.

out1,2

12.Not guaranteed in dropout.

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NCV47821

Table 6. ELECTRICAL CHARACTERISTICS V

= 10 mF, Min and Max values are valid for temperature range −40°C v TJ v +150°C unless noted otherwise and are guaranteed

C

out1,2

by test, design or statistical correlation. Typical values are referenced to T

= 13.5 V, V

in

= 3.3 V, VDE = 0 V, R

EN1,2

= 25°C (Note 8)

J

CSO1,2

= 0 W, C

= 1 mF, Cin = 1 mF,

CSO1,2

Parameter UnitMaxTypMinSymbolTest Conditions

DIAGNOSTICS

Overcurrent Voltage Level Threshold

Short To Battery (STB) Voltage
Threshold in OFF state

Open Load (OL) Current Threshold

V

out_nom1,2

Vin = 4.4 V to 18 V, I
V

DE

= 3.3 V

= 5 V, R

CSO1,2

= I

out1

= 1 kW

= 0 mA,

out2

Vin = 4.4 V to 18 V, VDE = 3.3 V I

in OFF state

Diagnostics Enable Threshold Voltage

Logic Low
Logic High

Channel Select Threshold Voltage

Logic Low
Logic High

Error Flag Low Voltage IEF = −1 mA V

V

OC1,2

V

STB1,2

OL1,2

V

th(DE)

V

th(CS)

EF_Low

92 95 98 % of

V

Ilim1,2

2 3 4 V

5.0 10 25 mA

0.99

−

0.99

−

1.8

1.9

1.8

1.9

−

2.31

−

2.31

− 0.04 0.4 V

CSO_

V

V

THERMAL SHUTDOWN

Thermal Shutdown Temperature
(Note 11)

out1

each channel measured separately

= 5 mA, V

out2

out_nom1,2

= 5 V,

T

SD1,2

150 175 195 °C

I

= I

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.

8. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at T
cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.

9. Minimum input voltage V

and Rn2 accuracy.

R

n1

10.Measured when the output voltage V

11.Values based on design and/or characterization.

is 4.4 V or (V

in_min

out_nom1,2

has dropped by 2% of V

out1,2

+ 1 V) whichever is higher. V

out_nom1,2

from the nominal valued obtained at Vin = V

out_nom1,2

measured at ADJ1,2 pin due to excluding

[ TJ. Low duty

A

+ 8.5 V.

out1,2

12.Not guaranteed in dropout.

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NCV47821

TYPICAL CHARACTERISTICS

1.30

800

Vin = 13.5 V

1.29

1.28

1.27

I

out1,2

= 5 mA

700

600

500

400

1.26

1.25

, REFERENCE VOLTAGE (V)

1.24

REF1

V

1.23
60 100 160

1401208040200−20−40

300

200

, QUIESCENT CURRENT (mA)

q

100

I

0

TJ, JUNCTION TEMPERATURE (°C) VIN, INPUT VOLTAGE (V)

Figure 4. Reference Voltage vs. Temperature Figure 5. Quiescent Current vs. Input Voltage

1.4

1.2

1.0

0.8

0.6

0.4

, REFERENCE VOLTAGE (V)

0.2

REF1

V

0

TJ = 25°C

= 5 mA

I

out1,2

543210

VIN, INPUT VOLTAGE (V) VIN, INPUT VOLTAGE (V)

0

TJ = 25°C
R

−1

out1,2

V

out_nom1,2

= 3.3 kW

= 3.3 V

−2

−3

−4

, INPUT CURRENT (mA)

in

I

−5

−6

Figure 6. Reference Voltage vs. Input Voltage Figure 7. Input Current vs. Input Voltage

(Reverse Input Voltage)

TJ = 25°C
I

= 500 mA

out1,2

V

out_nom1,2

−10 0

= 5 V

35302520151050

−5−15−20−25−30−35−40−45

40

450

400

350

300

250

200

150

, DROPOUT VOLTAGE (mV)

100

DO1,2

50

V

0

V

out_nom1,2

= 5 V

TJ = 150°C

TJ = 25°C

TJ = −40°C

300250200 350150100500

I

, OUTPUT CURRENT (mA) VIN, INPUT VOLTAGE (V)

out1,2

1.15

1.10

V

out_nom1,2

V

out1,2

= 3.3 V

= 90% of V

out_nom1,2

1.05

1.00

0.95

0.90

0.85

0.80

, OUTPUT CURRENT LIMIT (A)

0.75

LIM1,2

I

0.70
15 25

V

Figure 8. Dropout Voltage vs. Output Current Figure 9. Output Current Limit vs. Input

Voltage

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TJ = 25°C

TJ = −40°C

TJ = 150°C

40353020 451050

NCV47821

TYPICAL CHARACTERISTICS

350

300

250

200

150

100

, OUTPUT CURRENT LIMIT (mA)

50

LIM1,2

I

0

4 8 14 18 24 26

R

CSO1,2

Figure 10. Output Current Limit vs. R

2.0
TJ = 25°C

1.5

1.0

V

in

= V

out_nom1,2

+ 8.5 V

(kW)

V

out1,2

= 3.3 V to 20 V

2220161210620

CSO

3.0

2.5

2.0

1.5

, CSO VOLTAGE (V)

1.0

CSO1,2

V

0.5

0

30

25

20

15

V

= 3.3 V to 20 V

out1,2

= −40°C to 150°C

T

J

, = 10 mA to 300 mA

I

LIM1,2

20 60 90 110

I

, OUTPUT CURRENT (% of I

out1,2

Figure 11. Output Current (% of I

LIM

Voltage

TJ = 25°C
V

in

= V

out_nom1,2

+ 8.5 V

1008070504030100

)

LIM1,2

) vs. CSO

0.5

, QUIESCENT CURRENT (mA)

q

I

0

I

, OUTPUT CURRENT (mA) I

out1,2

Figure 12. Quiescent Current vs. Output

Current (Low Load)

112
110

TJ = 25°C

108

V

in

= V

out_nom1,2

+ 8.5 V

106

104

102
100

98

, OUTPUT CURRENT

96

CSO1,2

94

/I

92

TO CSO CURRENT RATIO (−)

out1,2

90

I

88

I

, OUTPUT CURRENT (mA) I

out1,2

Figure 14. Output Current to CSO Current

Ratio vs. Output Current

10

5

, QUIESCENT CURRENT (mA)

q

I

0

20.0

17.515.012.510.07.55.02.50

, OUTPUT CURRENT (mA)

out1,2

28024020016012080400

Figure 13. Quiescent Current vs. Output

Current (High Load)

100

95

90

85

80

75

, OUTPUT CURRENT

70

65

CSO1,2

/I

TO CSO CURRENT RATIO (−)

out1,2

I

60

55

TJ = 25°C

= 4.5 V

V

in

V

out_nom1,2

= 5 V

50

1000100101

, OUTPUT CURRENT (mA)

out1,2

1000100101

Figure 15. Output Current to CSO Current

Ratio vs. Output Current (in dropout)

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NCV47821

TYPICAL CHARACTERISTICS

ESR (W)

100

Unstable Region

(Area above curves)

10

V

V

V

(Area under curves)

0.1

1

TJ = 25°C

= V

V

in

out_nom1,2

C

= 10 mF − 100 mF

out1,2

C

= none

b1,2

+ 8.5 V

0.01

I

, OUTPUT CURRENT (mA) FREQUENCY (Hz)

out1,2

Figure 16. Output Capacitor Stability Region

vs. Output Current

100

90

I

out1,2

80

70

I

(dB)

1,2

out1,2

60

out_nom1,2

out_nom1,2

out_nom1,2

= 20 V

= 5 V

= 3.3 V

Stable Region

= 5 mA

= 200 mA

3000

)

1/2

2500

2000

1500

1000

, NOISE DENSITY (nV/Hz

500

n1,2

V

0

200150100500

f = 10 Hz − 100 kHz
V

= 182 mV

n1,2

Figure 17. Noise vs. Frequency

TJ = 25°C

= 12 V

V

in

C

= 10 nF

b1,2

I

= 5 mA

out1,2

100,00010,000100010010

50

PSRR

40

30

20

TA = 25°C

= 13.5 V DC + 0.5 VPP AC

V

in

V

out_nom1,2

= 5 V

FREQUENCY (Hz)

Figure 18. PSRR vs. Frequency

100,00010,000100010010

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NCV47821

DEFINITIONS

General

All measurements are performed using short pulse low
duty cycle techniques to maintain junction temperature as
close as possible to ambient temperature.

Output voltage

The output voltage parameter is defined for specific
temperature, input voltage and output current values or
specified over Line, Load and Temperature ranges.

Line Regulation

The change in output voltage for a change in input voltage
measured for specific output current over operating ambient
temperature range.

Load Regulation

The change in output voltage for a change in output
current measured for specific input voltage over operating
ambient temperature range.

Dropout Voltage

The input to output differential at which the regulator
output no longer maintains regulation against further
reductions in input voltage. It is measured when the output
drops 2% of V

below its nominal value. The junction

out_nom

temperature, load current, and minimum input supply
requirements affect the dropout level.

Quiescent and Disable Currents

Quiescent Current (Iq) is the difference between the input
current (measured through the LDO input pin) and the
output load current. If Enable pin is set to LOW the regulator
reduces its internal bias and shuts off the output, this term is
called the disable current (I

DIS

).

Current Limit

Current Limit is value of output current by which output

voltage drops below 90% of its nominal value.

PSRR

Power Supply Rejection Ratio is defined as ratio of output
voltage and input voltage ripple. It is measured in decibels
(dB).

Line Transient Response

Typical output voltage overshoot and undershoot
response when the input voltage is excited with a given
slope.

Load Transient Response

Typical output voltage overshoot and undershoot
response when the output current is excited with a given
slope between low-load and high-load conditions.

Thermal Protection

Internal thermal shutdown circuitry is provided to protect
the integrated circuit in the event that the maximum junction
temperature is exceeded. When activated at typically 175°C,
the regulator turns off. This feature is provided to prevent
failures from accidental overheating.

Maximum Package Power Dissipation

The power dissipation level is maximum allowed power
dissipation for particular package or power dissipation at
which the junction temperature reaches its maximum
operating value, whichever is lower.

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10

NCV47821

APPLICATIONS INFORMATION

Circuit Description

The NCV47821 is an integrated dual low dropout
regulator that provides a regulated voltage at 200 mA to each
output. It is enabled with an input to the enable pin. The
regulator voltage is provided by a PNP pass transistor
controlled by an error amplifier with a bandgap reference,
which gives it the lowest possible dropout voltage. The
output current capability of the LDO is 200 mA per output
and the base drive quiescent current is controlled to prevent
oversaturation when the input voltage is low or when the
output is overloaded. The integrated current sense feature
provides diagnosis and system protection functionality. The
current limit of the device is adjustable by resistor connected
to CSO pin. Voltage on CSO pin is proportional to output
current. The regulator is protected by both current limit and
thermal shutdown. Thermal shutdown occurs above 150°C
to protect the IC during overloads and extreme ambient
temperatures.

Regulator

The error amplifier compares the reference voltage to a
sample of the output voltage (V

) and drives the base of

out1,2

a PNP series pass transistor via a buffer. The reference is a
bandgap design to give it a temperature stable output.
Saturation control of the PNP is a function of the load current
and input voltage. Oversaturation of the output power
device is prevented, and quiescent current in the ground pin
is minimized.

Regulator Stability Considerations

The input capacitor (Cin) is necessary to stabilize the input
impedance to avoid voltage line influences. The output
capacitor (C

) helps determine three main

out1,2

characteristics of a linear regulator: startup delay, load
transient response and loop stability. The capacitor value
and type should be based on cost, availability, size and
temperature constraints. The aluminum electrolytic
capacitor is the least expensive solution, but, if the circuit
operates at low temperatures (−25°C to −40°C), both the
value and ESR of the capacitor will vary considerably. The
capacitor manufacturer’s data sheet usually provides this
information. The value for the output capacitor C

out1,2

shown in Figure 1 should work for most applications; see
also Figure 16 for output stability at various load and Output
Capacitor ESR conditions. Stable region of ESR in
Figure 16 shows ESR values at which the LDO output
voltage does not have any permanent oscillations at any
dynamic changes of output load current. Marginal ESR is
the value at which the output voltage waving is fully damped
during four periods after the load change and no oscillation
is further observable.

ESR characteristics were measured with ceramic
capacitors and additional series resistors to emulate ESR.
Low duty cycle pulse load current technique has been used

to maintain junction temperature close to ambient
temperature.

Calculating Bypass Capacitor

If improved stability (reducing output voltage ringing
during transients) is demanded, connect the bypass
capacitor C

between Adjustable Input pin and V

b1,2

according to Applications circuit at Figure 1. Parallel
combination of bypass capacitor C
resistor R

contributes in the device transfer function as an

n1

with the feedback

b1,2

additional zero and affects the device loop stability,
therefore its value must be optimized. Attention to the
Output Capacitor value and its ESR must be paid. See also
Stability in High Speed Linear LDO Regulators Application
Note, AND8037/D for more information. Optimal value of
bypass capacitor is given by following expression

Cbn+

2 p f

1

z

R

(F)

n1

where

the upper feedback resistor

R

1

n

f

the frequency of the zero added into the device

z

transfer function by R

and Cb1 external

1

n

components.

Set the R
Chose the f

resistor according to output voltage requirement.

n1

with regard on the output capacitance C

z

refer to the table below.

C

(mF)

out1,2

fZ range (kHz) max 19 max 19 N/A* N/A*

NOTE: * For C

out1,2

needed for stability improvement. C
useful for reduction start up overshoot and noise
reduction. See electrical characteristic table.

10 22 47 100

= 47 mF and higher, C

capacitors are not

b1,2

capacitors are

b1,2

Ceramic capacitors and its part numbers listed bellow
have been used as low ESR output capacitors C
the table above to define the frequency ranges of additional
zero required for stability:

GRM31CR71C106KAC7 (10 mF, 16 V, X7R, 1206)

,

GRM32ER71C226KE18 (22 mF, 16 V, X7R, 1210)

GRM32ER61C476ME15 (47 mF, 16 V, X5R, 1210)

GRM32ER60J107ME20 (100 mF, 6.3 V, X5R, 1210)

Enable Inputs

An enable pin is used to turn a channel on or off. By
holding the pin down to a voltage less than 0.99 V, the output
of the channel will be turned off. When the voltage on the
enable pin is greater than 2.31 V, the output of the channel
will be enabled to power its output to the regulated output
voltage. The enable pins may be connected directly to the
input pin to give constant enable to the output channel.

out1,2

out1,2

pin

(eq. 1)

out1,2

from

,

www.onsemi.com

11

NCV47821

Setting the Output Voltage

The output voltage range can be set between 3.3 V and
20 V. This is accomplished with an external resistor divider
feeding back the voltage to the IC back to the error amplifier
by the voltage adjust pin ADJ. The internal reference voltage
is set to a temperature stable reference (V

) of 1.265 V.

REF1

The output voltage is calculated from the following formula.
Ignoring the bias current into the ADJ pin:

R

V

out_nom_n

+ V

REF1

ǒ

1 )

n1

Ǔ

R

n2

(eq. 2)

Use Rn2 < 50 kW to avoid significant voltage output errors
due to ADJ bias current.

Designers should consider the tolerance of R

and R

n1

n2

during the design phase.

Setting the Output Current Limit

The output current limit can be set up to 300 mA by
external resistor R
1 mF in parallel with R

(see Figure 1). Capacitor C

CSO1,2

is required for stability of current

CSO

CSO

of

limit control circuitry (see Figure 1).

V

CSO1,2

I

LIM1,2

R

CSO1,2

+ I

out1,2

+

+

100

1

ǒ

R

100

1

CSO1,2

R

2.55

CSO1,2

2.55

I

LIM1,2

1

100

Ǔ

(eq. 3)

(eq. 4)

(eq. 5)

where

R

− current limit setting resistor

CSO1,2

 voltage at CSO pin proportional to I

V

CSO1,2

I

− current limit value

LIM1,2

− output current actual value

I

out1,2

out1,2

CSO pin provides information about output current actual
value. The CSO voltage is proportional to output current
according to Equation 3.

Once output current reaches its limit value (I
external resistor R

2.55 V. Calculations of I

than voltage at CSO pin is typically

CSO

or R

LIM1,2

CSO1,2

values can be

LIM1,2

) set by

done using Equation 4 and Equation 5, respectively.
Minimum and maximum value of Output Current Limit can
be calculated according Equation 6 and 7.

V

max

R

V

CSO1,2_min

CSO1,2_max

CSO1,2_max

R

CSO1,2_min

(eq. 6)

(eq. 7)

I

LIM1,2_min

I

LIM1,2_max

+ RATIO

+ RATIO

min

where

RATIO

− minimum value of Output Current to

min

CSO Current Ratio from electrical
characteristics table and particular output
current range

RATIO

− maximum value of Output Current to

max

CSO Current Ratio from electrical
characteristics table and particular output
current range

V

CSO1,2_min

 minimum value of CSO Voltage Level at

Current Limit from electrical characteristics
table

V

CSO1,2_max

 maximum value of CSO Voltage Level at

Current Limit from electrical characteristics
table

R

CSO1,2_min

− minimum value of R

CSO1,2

with respect

its accuracy

R

CSO1,2_max

− maximum value of R

CSO1,2

with respect

its accuracy

Designers should consider the tolerance of R

CSO1,2

during the design phase.

Diagnostic in OFF State

The NCV47821 contains also circuitry for OFF state
diagnostics for Short to Battery (STB) and Open Load (OL).
There are internal current sources, Pull−Up and Pull Down
resistors which provide additional cost savings for overall
application by excluding external components and their
assembly cost and saving PCB space and safe control IOs of
a Microcontroller Unit (MCU).

Simplified functional schematic and truth table is shown
in Figure 19 and related flowchart in Figure 20.

Current source enabled via EN and DE pins

I

PU

PASS DEVICE is OFF in Diagnostics

state (DE = H).

Mode in OFF state

out

> V

out

out_OFF

< V

out

out_OFF

> V

out

out_OFF

< V

out

out_OFF

+

V

−

REF_OFF

Diagnostic Status/Action

Short to Battery (STB)

Check for Open Load (OL)

Open Load (OL)

No Failure (V

close to 0 V)

out

V

R

PD1

R

PD2

Digital Diagnostics:
to MCU’s digital input
with pull−up resistor
to MCU’s DIO supply rail

out

EF

V

in

Comparator active only in Diagnostic

EN

DE

EN – Enable(Logic Input)
DE – Diagnostics Enable(Logic Input)
EF – Error Flag Output(Open Collector Output)

EN DE IPUEF V

L L OFF HZ Unknown None (Diagnostics OFF)

L H OFF L V

L H OFF HZ V

HHONLV

H H ON HZ V

Figure 19. Simplified Functional Diagram of OFF

State Diagnostics (STB and OL)

www.onsemi.com

12

NCV47821

Start

Diag. OFF. Set

EN = L & DE = L

Diag. ON. Set

EN = L & DE = H

HZ

IPU ON. Set

EN = H & DE = H

HZ

No Failure Open Load Short to Battery

EF = ?

EF = ?

L

L

Figure 20. Flowchart for Diagnostics in OFF State

The diagnostics in OFF state shall be performed for each
channel separately. For diagnostics of Channel 1 the input
CS pin has to be put logic low, for diagnostics of Channel 2
the input CS pin has to be put logic high. Corresponding EN
pin has to be used for control (EN1 for Channel 1 and EN2
for Channel 2). For detailed information see Diagnostic
Features Truth Table in Figure 21.

Diagnostic in ON State

Diagnostic in ON State provides information about
Overcurrent or Short to Ground failures, during which the
EF output is in logic low state. The diagnostics in ON state
shall be performed for each channel separately. For
diagnostics of Channel 1 the input CS pin has to be put logic
low, for diagnostics of Channel 2 the input CS pin has to be
put logic high. For detailed information see Diagnostic
Features Truth Table in Figure 21.

Figure 21. Diagnostic Features Truth Table

13.State of EN pin of appropriate channel

14.CS = L means CH1 diagnostics and CS = H means CH2 diagnostics in OFF state (DE = H) via EF output, appropriate EN pin is used for
turning internal switch ON and OFF (e.g. when DE = H and CS = L and EN1 = L then IPU1 is OFF, when DE = H and CS = L and EN1 =
H then IPU1 is ON)

15.Internal current source turned OFF (between V

16.Internal current source turned ON (between V

17. CS = L means CH1 diagnostics and CS = H means CH2 diagnostics in ON state (e.g. when CS = L and EF = L then CH1 has Overcurrent
or Short to Ground failure, when CS = H and EF = L then CH1 has Overcurrent or Short to Ground failure)

out

out

and V

and V

of appropriate channel)

in

of appropriate channel)

in

www.onsemi.com

13

NCV47821

Thermal Considerations

As power in the device increases, it might become
necessary to provide some thermal relief. The maximum
power dissipation supported by the device is dependent
upon board design and layout. Mounting pad configuration
on the PCB, the board material, and the ambient temperature
affect the rate of junction temperature rise for the part. When
the device has good thermal conductivity through the PCB,
the junction temperature will be relatively low with high
power applications. The maximum dissipation the device
can handle is given by:

ƪ

T

P

D(MAX)

+

J(MAX)

R

Since TJ is not recommended to exceed 150°C, then the
device soldered on 645 mm

2

, 1 oz copper area, FR4 can

dissipate up to 2.38 W when the ambient temperature (T
is 25°C. See Figure 22 for R

versus PCB area. The power

JA

q

dissipated by the device can be calculated from the
following equations:

PD[ V

in

ǒ

Iq@I

out1,2

Ǔ

) I

out1

ǒ

Vin−V

or

V

in(MAX)

P

[

D(MAX)

)ǒV

out1

I

out1

I

) I

qJA

out1

out1

out2

* T

Ǔ)ǒ

Ǔ

) I

) I

ƫ

A

out2

V

q

out2

ǒ

Vin−V

I

(eq. 8)

(eq. 9)

out2

(eq.

10)

Ǔ

out2

A

130

120

110

100

90

80

70

60

2 oz, Single Layer

50

40

, THERMAL RESISTANCE (°C/W)

JA

30

q

R

20

COPPER HEAT SPREADER AREA (mm2)

)

Figure 22. Thermal Resistance vs. PCB Copper Area

1 oz, Single Layer

1 oz, 4 Layer

2 oz, 4 Layer

600 7005004003002001000

Hints

Vin and GND printed circuit board traces should be as
wide as possible. When the impedance of these traces is
high, there is a chance to pick up noise or cause the regulator

Ǔ

to malfunction. Place external components, especially the
output capacitor, as close as possible to the device and make
traces as short as possible.

ORDERING INFORMATION

Device Output Voltage Marking Package Shipping

NCV47821PAAJR2G Adjustable Line1: NCV4

Line2: 7821

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D

TSSOP−14 Exposed Pad

(Pb−Free)

2500 / Tape & Reel

†

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14

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

14

TSSOP−14 EP

CASE 948AW

1

SCALE 1:1

NOTE 6

B

14 8

c1

NOTE 5

E1

E

c

PIN 1

REFERENCE

NOTE 6

0.05 C

0.10 C

14X

A

e

1

TOP VIEW

D

NOTE 4

14X

NOTE 3

b

0.10

7

C

2X 14 TIPS

A2

B A

0.20 C

A

SS

C

BA

SEATING
PLANE

B

c

B

SIDE VIEW

D2

H

E2

A1

NOTE 7

DETAIL A

BOTTOM VIEW

RECOMMENDED

SOLDERING FOOTPRINT*

3.40

3.06

1

0.65

PITCH

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

14X

1.15

6.70

14X

0.42

ISSUE C

b

b1

SECTION B−B

NOTE 8

DETAIL A

END VIEW

L

L2

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL BE

0.07 mm MAX. AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER RADI­US OF THE FOOT. MINIMUM SPACE BETWEEN PRO­TRUSION AND ADJACENT LEAD IS 0.07.

4. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED

0.15 mm PER SIDE. DIMENSION D IS DETERMINED AT
DATUM H.

5. DIMENSION E1 DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSIONS. INTERLEAD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.25 mm PER
SIDE. DIMENSION E1 IS DETERMINED AT DATUM H.

6. DATUMS A AND B ARE DETERMINED AT DATUM H.

7. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM

C

M

GAUGE
PLANE

THE SEATING PLANE TO THE LOWEST POINT ON THE
PACKAGE BODY.

8. SECTION B−B TO BE DETERMINED AT 0.10 TO 0.25 mm
FROM THE LEAD TIP.

MILLIMETERS

DIM MIN MAX

A −−−− 1.20
A1 0.05 0.15
A2 0.80 1.05

b 0.19 0.30
b1 0.19 0.25

c 0.09 0.20

c1 0.09 0.16

D 4.90 5.10
D2 3.09 3.62

E 6.40 BSC
E1 4.30 4.50
E2 2.69 3.22

0.65 BSCe

L 0.45 0.75
L2 0.25 BSC

M 0 8

__

GENERIC

MARKING DIAGRAM*

14

XXXX
XXXX

ALYWG

G

1

XXXX = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package

(Note: Microdot may be in either location)

*This information is generic. Please refer to

device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.

DATE 09 OCT 2012

DOCUMENT NUMBER:

DESCRIPTION:

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.

© Semiconductor Components Industries, LLC, 2019

98AON66474E

TSSOP−14 EP, 5.0X4.4

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

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