ON Semiconductor NCV47700 User Manual

NCV47700

Low Dropout Regulator -

Adjustable, Adjustable
Current Limit

5 V to 20 V

The NCV47700 is a 350 mA output current integrated low dropout
regulator designed for use in harsh automotive environments. It
includes wide operating temperature and input voltage ranges. The
device is offered with adjustable voltage versions available in 6%
output voltage accuracy. It has a high peak input voltage tolerance and
reverse input voltage protection. It also provides overcurrent
protection, overtemperature protection and enable for control of the
state of the output voltage. The integrated current sense feature
provides diagnosis and system protection functionality. The current
limit of the device is adjustable by resistor connected to CSO pin.
Voltage on CSO pin is proportional to output current.

Features

• Adjustable Voltage Version (from 5 V to 20 V) ±6% Output Voltage

for ±3% Output Voltage Accuracy see NCV47701 Specification

• Enable Input (5 V Logic Compatible Thresholds)

for 3.3 V Logic Compatible Thresholds see NCV47710 or
NCV47711 Specification

• Adjustable Current Limit (from 10 mA to 350 mA) with 10%

accuracy

• Protection Features:

♦ Current Limitation
♦ Thermal Shutdown
♦ Reverse Input Voltage

• This is a Pb−Free Device

Typical Applications

• Audio and Infotainment System

• Instrument Cluster

• Navigation

• Satellite Radio

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MARKING

DIAGRAMS

8

SOIC−8

8

1

8

1

Exposed Pad

PD SUFFIX

CASE 751AC

SOIC−8

D SUFFIX

CASE 751

A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package

47700
ALYW

G

1

8

47700
ALYW

G

1

PIN CONNECTIONS

18

ADJ

CSO

SOIC−8 EP, SOIC−8

V

out

NCGND
NCEN

V

in

ORDERING INFORMATION

See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.

V

EN

in

NCV47700

GND

C

in

1 m F

*Required if usage of low ESR output capacitor C

Regulator Stability Considerations section.

V

out

ADJ

CSO

C

1 m F

CSO

Figure 1. Application Schematic

© Semiconductor Components Industries, LLC, 2012

October, 2019 − Rev. 3

Cb*

R

CSO

is demand, see

out

R

1

C

R

out

2

22 mF

1 Publication Order Number:

NCV47700/D

NCV47700

V

EN

GND

in

V

VOLTAGE

REFERENCE

V

REF1
REF2

PASS DEVICE

AND

I

CSO

= I

out

/ 100

V

out

CURRENT MIRROR

ENABLE

SATURATION

PROTECTION

THERMAL

SHUTDOWN

SP

TSD

SP

+

-

+

-

V

REF1

1.275 V

V

REF2

2.55 V

CSO

ADJ

TSD

Figure 2. Simplified Block Diagram

PIN FUNCTION DESCRIPTION

Pin No.

SOIC−8 EP

1 1 ADJ Adjustable Voltage Setting Input. See Application Section for more details.

2 2 GND Power Supply Ground.

3 3 EN Enable Input; low level disables the IC.

4 4 CSO Current Sense Output, Current Limit setting and Output Current value information.

5 5 V

6 6 NC Not Connected

7 7 NC Not Connected

8 8 V

EPAD − EPAD Connect to ground potential or leave unconnected.

Pin No.
SOIC−8

Pin Name Description

See Application Section for more details.

in

out

Positive Power Supply Input.

Regulated Output Voltage.

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2

NCV47700

ABSOLUTE MAXIMUM RATINGS (Note 1)

Rating

Input Voltage V

Enable Input Voltage V

Adjustable Input Voltage V

CSO Voltage V

Output Voltage V

Junction Temperature T

Storage Temperature T

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.

1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.

ESD CAPABILITY (Note 2)

Rating

ESD Capability, Human Body Model ESD

ESD Capability, Machine Model ESD

2. This device series incorporates ESD protection and is tested by the following methods:

ESD Human Body Model tested per AEC−Q100−002 (JS−001−2010)

ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Field Induced Charge Device Model ESD characterization is not performed on plastic molded packages with body sizes < 50mm
the inability of a small package body to acquire and retain enough charge to meet the minimum CDM discharge current waveform
characteristic defined in JEDEC JS−002−2014.

LEAD SOLDERING TEMPERATURE AND MSL (Note 3)

Rating

Moisture Sensitivity Level SOIC−8 EP

SOIC−8

3. For more information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D

THERMAL CHARACTERISTICS

Rating Symbol Value Unit

Thermal Characteristics, SOIC−8 EP (single layer PCB)

Thermal Resistance, Junction−to−Air (Note 4)
Thermal Reference, Junction−to−Lead (Note 4)

Thermal Characteristics, SOIC−8 EP (4 layers PCB)

Thermal Resistance, Junction−to−Air (Note 4)
Thermal Reference, Junction−to−Lead (Note 4)

Thermal Characteristics, SOIC−8 (single layer PCB)

Thermal Resistance, Junction−to−Air (Note 4)
Thermal Reference, Junction−to−Lead (Note 4)

Thermal Characteristics, SOIC−8 (4 layers PCB)

Thermal Resistance, Junction−to−Air (Note 4)
Thermal Reference, Junction−to−Lead (Note 4)

4. Values based on copper area of 645 mm2 (or 1 in2) of 1 oz copper thickness and FR4 PCB substrate. Single layer − according to JEDEC51.3,
4 layers − according to JEDEC51.7.

RECOMMENDED OPERATING RANGES

Rating Symbol Min Max Unit

Input Voltage (Note 5) V

Output Current Limit (Note 6) I

Junction Temperature T

Nominal Output Voltage V

Current Sense Output (CSO) Capacitor C

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.

5. Minimum V

6. Corresponding R

= 5.5 V or (V

in

CSO

+ 0.5 V), whichever is higher.

out_nom

is in range from 25 kW down to 728 W.

Symbol Min Max Unit

in

EN

ADJ

CSO

out

J

STG

−42 45 V

−42 45 V

−0.3 10 V

−0.3 7 V

−1 40 V

−40 150 °C

−55 150 °C

Symbol Min Max Unit

HBM

MM

−2 2 kV

−200 200 V

2

due to

Symbol Min Max Unit

MSL 2

−

1

°C/W

R

θJA

R

ψJL

70
19

°C/W

R

θJA

R

ψJL

29
12

°C/W

R

θJA

R

ψJL

121

42

°C/W

R

θJA

R

ψJL

in

LIM

J

out_nom

CSO

77
52

5.5 40 V

10 350 mA

−40 150 °C

5.0 20 V

1.0 4.7

mF

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3

NCV47700

ELECTRICAL CHARACTERISTICS V

and Max values are valid for temperature range −40°C ≤ T
statistical correlation. Typical values are referenced to T

Parameter

= 13.5 V, VEN = 5 V, R

in

≤ 150°C unless otherwise noted and are guaranteed by test design or

J

= 25°C.

J

Test Conditions Symbol Min Typ Max Unit

CSO

= 0 W, C

= 1 mF, Cin = 1 mF, C

CSO

REGULATOR OUTPUT

Output Voltage (Accuracy %)

Vin = (V

Line Regulation Vin = (V

Load Regulation I

Dropout Voltage (Note 7) I

= 5 mA to 350 mA Reg

out

= 150 mA, VDO = Vin − V

out

out_nom

out_nom

+ 1 V) to 40 V, I

+ 1 V) to (V

out_nom

out

= 5 mA to 350 mA V

out

+ 20V), I

= 5mA Reg

out

DISABLE AND QUIESCENT CURRENTS

Disable Current

Quiescent Current, Iq = Iin − I

Quiescent Current, Iq = Iin − I

VEN = 0 V
V

outIout

outIout

= 0 V, TJ = 25°C

EN

= 1 mA, Vin = (V

= 350 mA, Vin = (V

+ 8.5 V) I

out_nom

+ 8.5 V) I

out_nom

CURRENT LIMIT PROTECTION

Current Limit

= 0.9 x V

out

out_nom

, Vin = (V

+ 8.5 V) I

out_nom

V

PSRR & NOISE

Power Supply Ripple Rejection

Output Noise Voltage

f = 100 Hz, 0.5 V

p−p

, I

f = 10 Hz to 100 kHz, C

= 5 mA, Cin = none

out

= 10 nF, I

b

out

= 5 mA

ENABLE

Enable Input Threshold Voltage

≤

V

Logic Low (OFF)
Logic High (ON)

V

out
out

0.1 V

≥

0.9 x V

out_nom

Enable Input Current VEN = 5 V I

Turn On Time from Enable ON to
90% of V

out_nom

I

= 100 mA, C

out

= 27 kW

R

2

= 10 nF, R1 = 82 kW,

b

OUTPUT CURRENT SENSE

CSO Voltage Level at Current
Limit

CSO Transient Voltage Level

CSO Current to Output Current
Ratio (Note 8)

CSO Current at No Load Current

= 0.9 x V

out

= 1 kW

R

CSO

C

= 4.7 mF, R

CSO

to 350 mA, t

V

= 2 V, I

CSO

(V

V

out_nom

= 0 V, I

CSO

= 5V)

r

, (V

out_nom

= 1 ms

out

out

out_nom

= 1 kW, I

CSO

= 10 mA to 350 mA,

= 0 mA, (V

out_nom

= 5 V)

pulse from 10 mA

out

= 5 V)

V

REVERSE CURRENT

Reverse Current (Note 9)

Vin = 12 V, V

= 14 V I

out

THERMAL SHUTDOWN

I

Thermal Shutdown Temperature

7. Measured when the output voltage V

8. Not guaranteed in dropout.

= 5 mA T

out

has dropped −2% from the nominal value obtained at Vin = V

out

9. Values based on design and/or characterization.

= 22 mF, ESR = 1.5 W, Min

out

−6 − 6 %

− 0.1 2.0 %

− 0.14 2.8 %

− 250 500 mV

−

−

85

−

10

−

− 150 230

− 23 50 mA

400 − − mA

V

I

out

line

load

DO

DIS

q

q

LIM

PSRR − 70 − dB

V

V

th(EN)

EN

t

V

CSO_Ilim

V

CSO

I

CSO/Iout

I

CSO_off

out_rev

n

on

SD

− 100 −

0.8

−

2.4

2.7

−

3.5

2.0 8.0 20

− 1.6 − ms

2.346

(−8 %)

2.55 2.754
(+8 %)

− − 3.0 V

−

(−10%)

(1/100) −

(+10%)

− − 10

−40 −25 − mA

150 − 195 °C

+ 8.5 V.

out_nom

mV

mA

nA

mA

rms

V

mA

V

−

mA

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4

NCV47700

TYPICAL CHARACTERISTICS

1.32
Vin = 13.5 V

1.31

I

out

= 5 mA

1.30

1.29

1.28

1.27

1.26

, REFERENCE VOLTAGE (V)

1.25

REF1

V

1.24

−40 −20 0 20 40 60 80 100 160120 140
TJ, JUNCTION TEMPERATURE (°C)

0.40

0.35

0.30

0.25

0.20

0.15

0.10

, QUIESCENT CURRENT (mA)

q

0.05

I

0

0 5 10 15 20 25 4030 35

, INPUT VOLTAGE (V)

V

in

Figure 3. Reference Voltage vs. Temperature Figure 4. Quiescent Current vs. Input Voltage

6

TJ = 25°C

= 5 mA

I

out

5

V

out_nom

= 5 V

4

3

2

, OUTPUT VOLTAGE (V)

out

1

V

0

13579

0246810

, INPUT VOLTAGE (V)

V

in

Figure 5. Output Voltage vs. Input Voltage

2

TJ = 25°C

1

R

= 4.7 kW

out

0

V

out_nom

= 5 V

−1

−2

−3

−4

−5

, INPUT CURRENT (mA)

−6

in

I

−7

−8

−45 −40 −35 −30 −25 −20 −5−15 −10 1005

, INPUT VOLTAGE (V)

V

in

Figure 6. Input Current vs. Input Voltage

(Reverse Input Voltage)

TJ = 25°C

= 5 mA

I

out

V

out_nom

= 5 V

800

Vin = 13.5 V

700

V

out_nom

= 5 V

600

500

400

TJ = 150°C

TJ = 25°C

300

200

, DROPOUT VOLTAGE (mV)

DO

100

V

0

0 50 100 150 200 250 300 350

I

, OUTPUT CURRENT (mA)

out

TJ = −40°C

Figure 7. Dropout vs. Output Current Figure 8. Output Current Limit vs. Input Voltage

1400

1300

1200

1100

1000

900

800

, OUTPUT CURRENT LIMIT (mA)

700

LIM

I

600

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5

V

= 4.5 V

out

V

out_nom

= 5 V

TJ = −40°C

TJ = 25°C

TJ = 150°C

0 5 10 15 20 25 30 35

, INPUT VOLTAGE (V)

V

in

40 45

NCV47700

0

0

TYPICAL CHARACTERISTICS

400

V

= 5 V to 20 V

350

out

= 25°C

T

J

300

250

200

150

100

, OUTPUT CURRENT LIMIT (mA)

50

LIM

I

0

2 6 10 14 18 22 26

0481216202428

Figure 9. Output Current Limit vs. R

R

CSO

, (kW)

CSO

105

TJ = 25°C

104

103

= 13.5 V

V

in

102

101

100

99

, OUTPUT CURRENT TO

98

CSO CURRENT RATIO

CSO

97

/I

out

96

I

95

1 10 100

I

, OUTPUT CURRENT (mA)

out

Figure 11. Output Current to CSO Current Ratio

vs. Output Current

1000

3.0
V

= 5 V to 20 V

out

= 25°C

T

J

2.5
I

= 10 mA to 350 mA

LIM

2.0

, (V)

1.5

CSO

V

1.0

0.5

0

0 25 50 75 100 125

, OUTPUT CURRENT (% of I

I

out

Figure 10. Output Current (% of I

LIM

) vs. CSO

LIM

Voltage

105

100

95

90

85

80

75

70

, OUTPUT CURRENT TO

65

CSO CURRENT RATIO

CSO

60

/I

out

I

55

50

1 10 100

, OUTPUT CURRENT (mA)

I

out

TJ = 25°C

= 4.5 V

V

in

V

out_nom

Figure 12. Output Current to CSO Current Ratio

vs. Output Current in Dropout

)

= 5 V

100

25

TJ = 25°C

= 13.5 V

V

in

20

15

10

5

, QUIESCENT CURRENT (mA)

q

I

0

0 50 100 150 200 250

I

, OUTPUT CURRENT (mA)

out

Figure 13. Quiescent Current vs. Output Current

(High Load)

, QUIESCENT CURRENT (mA)

q

I

300 350

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6

5.0

4.5

4.0

TJ = 25°C

= 13.5 V

V

in

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

010203040506070 10

I

, OUTPUT CURRENT (mA)

out

80 90

Figure 14. Quiescent Current vs. Output Current

(Low Load)

NCV47700

TYPICAL CHARACTERISTICS

3000

2500

2000

TJ = 25°C

= 13.5 V

V

in

V

out_nom

I

= 5 mA

out

= 5 V

Noise 10 Hz − 100 kHz
V

= 100.6 mV

n

90
85

80
75

70

65

1500

1000

60
55

PSRR (dB)

50

I

out

= 5 mA

I

= 150 mA

out

45

500

OUTPUT NOISE DENSITY (nV/√Hz)

0

10 1000 100000

100 10000

FREQUENCY (Hz)

TJ = 25°C

40

= 13.5 V

V

in

35

V

30

10 100 1000 10000 1000000100000

out_nom

= 5 V

FREQUENCY (Hz)

Figure 15. Output Noise Density vs. Frequency Figure 16. PSRR vs. Frequency

100

Unstable Region

10

1

V

out

TJ = 25°C

= V

V

in

C

= 10−100 mF, Cb = none

out

= 5 V

out_nom

V

out

+ 8.5 V

= 20 V

0.1

, ESR STABILITY REGION (W)

out

C

0.01
0 50 100 150 200 250 300 350

Figure 17. C

Unstable Region

I

, OUTPUT CURRENT (mA)

out

ESR Stability Region vs. Output

out

Current

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7

NCV47700

DEFINITIONS

General

All measurements are performed using short pulse low duty
cycle techniques to maintain junction temperature as close
as possible to ambient temperature.

Output Voltage

The output voltage parameter is defined for specific
temperature, input voltage and output current values or
specified over Line, Load and Temperature ranges.

Line Regulation

The change in output voltage for a change in input voltage
measured for specific output current over operating ambient
temperature range.

Load Regulation

The change in output voltage for a change in output current
measured for specific input voltage over operating ambient
temperature range.

Dropout Voltage

The input to output differential at which the regulator output
no longer maintains regulation against further reductions in
input voltage. It is measured when the output voltage V

out

has dropped −2% from the nominal value obtained at Vin =
V

+ 8.5 V. The junction temperature, load current,

out_nom

and minimum input supply requirements affect the dropout
level.

Quiescent and Disable Currents

Quiescent Current (Iq) is the difference between the input
current (measured through the LDO input pin) and the
output load current. If Enable pin is set to LOW the regulator

reduces its internal bias and shuts off the output, this term is
called the disable current (I

Current Limit

DIS

).

Current Limit is value of output current by which output
voltage drops below 90% of its nominal value.

PSRR

Power Supply Rejection Ratio is defined as ratio of output
voltage and input voltage ripple. It is measured in decibels
(dB).

Line Transient Response

Typical output voltage overshoot and undershoot response
when the input voltage is excited with a given slope.

Load Transient Response

Typical output voltage overshoot and undershoot response
when the output current is excited with a given slope
between low−load and high−load conditions.

Thermal Protection

Internal thermal shutdown circuitry is provided to protect
the integrated circuit in the event that the maximum junction
temperature is exceeded. When activated at typically 175°C,
the regulator turns off. This feature is provided to prevent
failures from accidental overheating.

Maximum Package Power Dissipation

The power dissipation level is maximum allowed power
dissipation for particular package or power dissipation at
which the junction temperature reaches its maximum
operating value, whichever is lower.

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8

NCV47700

APPLICATIONS INFORMATION

Circuit Description

The NCV47700 is an integrated low dropout regulator
that provides a regulated voltage at 350 mA to the output. It
is enabled with an input to the enable pin. The regulator
voltage is provided by a PNP pass transistor controlled by an
error amplifier with a bandgap reference, which gives it the
lowest possible dropout voltage. The output current
capability is 350 mA, and the base drive quiescent current is
controlled to prevent oversaturation when the input voltage
is low or when the output is overloaded. The integrated
current sense feature provides diagnosis and system
protection functionality. The current limit of the device is
adjustable by resistor connected to CSO pin. Voltage on
CSO pin is proportional to output current. The regulator is
protected by both current limit and thermal shutdown.
Thermal shutdown occurs above 150°C to protect the IC
during overloads and extreme ambient temperatures.

Regulator

The error amplifier compares the reference voltage to a
sample of the output voltage (V

) and drives the base of a

out

PNP series pass transistor via a buffer. The reference is a
bandgap design to give it a temperature−stable output.
Saturation control of the PNP is a function of the load current
and input voltage. Oversaturation of the output power
device is prevented, and quiescent current in the ground pin
is minimized.

Calculating Bypass Capacitor

If usage of low ESR ceramic capacitors is demanded,
connect the bypass capacitor C
pin and V

pin according to Applications circuit at

out

Figure 1. Parallel combination of bypass capacitor C
the feedback resistor R

contributes in the device transfer

1

between Adjustable Input

b

with

b

function as an additional zero and affects the device loop
stability, therefore its value must be optimized. Attention to
the Output Capacitor value and its ESR must be paid. See
also Stability in High Speed Linear LDO Regulators
Application Note, AND8037/D for more information.
Optimal value of bypass capacitor is given by following
expression:

Cb+

2 p fz R

1

1

(eq. 1)

where

R

− the upper feedback resistor

1

f

− the frequency of the zero added into the device

z

transfer function by R

Set the R
Chose the f

resistor according to output voltage requirement.

1

with regard on the output capacitance C

z

and Cb external components.

1

, refer

out

to the table below.

C

(mF)

out

fZ range (kHz) 3.3−48.2 1.5−33 1.5−33 2.2−22

10 22 47 100

Regulator Stability Considerations

The input capacitor (Cin) is necessary to stabilize the input
impedance to avoid voltage line influences. The output
capacitor (C

) helps determine three main characteristics

out

of a linear regulator: startup delay, load transient response
and loop stability. The capacitor value and type should be
based on cost, availability, size and temperature constraints.
The aluminum electrolytic capacitor is the least expensive
solution, but, if the circuit operates at low temperatures
(−25°C to −40°C), both the value and ESR of the capacitor
will vary considerably. The capacitor manufacturer’s data
sheet usually provides this information. The value for the
output capacitor C

, shown in Figure 1 should work for

out

most applications; see also Figure 17 for output stability at
various load and Output Capacitor ESR conditions. Stable
region of ESR in Figure 17 shows ESR values at which the
LDO output voltage does not have any permanent
oscillations at any dynamic changes of output load current.
Marginal ESR is the value at which the output voltage
waving is fully damped during four periods after the load
change and no oscillation is further observable.

ESR characteristics were measured with ceramic
capacitors and additional series resistors to emulate ESR.
Low duty cycle pulse load current technique has been used
to maintain junction temperature close to ambient
temperature.

Ceramic capacitors and its part numbers listed bellow

have been used as low ESR output capacitors C

from the

out

table above to define the frequency ranges of additional zero
required for stability:

GRM31CR71C106KAC7 (10 mF, 16 V, X7R, 1206)
GRM32ER71C226KE18 (22 mF, 16 V, X7R, 1210)
GRM32ER61C476ME15 (47 mF, 16 V, X5R, 1210)
GRM32ER60J107ME20 (100 mF, 6.3 V, X5R, 1210)

Enable Input

The enable pin is used to turn the regulator on or off. By
holding the pin down to a voltage less than 0.8 V, the output
of the regulator will be turned off. When the voltage on the
enable pin is greater than 3.5 V, the output of the regulator
will be enabled to power its output to the regulated output
voltage. The enable pin may be connected directly to the
input pin to give constant enable to the output regulator.

Setting the Output Voltage

The output voltage range can be set between 5 V and 20 V.
This is accomplished with an external resistor divider
feeding back the voltage to the IC back to the error amplifier
by the voltage adjust pin ADJ. The internal reference voltage
is set to a temperature stable reference (V

) of 1.275 V.

REF1

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9

NCV47700

The output voltage is calculated from the following formula.
Ignoring the bias current into the ADJ pin:

R

1 )

1

Ǔ

R

2

(eq. 2)

V

+ V

out

REF1

ǒ

Use R2 < 50 kW to avoid significant voltage output errors
due to ADJ bias current.

Designers should consider the tolerance of R

and R2 during

1

the design phase.

Setting the Output Current Limit

The output current limit can be set between 10 mA and

350 mA by external resistor R

of 1 mF in parallel with R

C

CSO

(see Figure 1). Capacitor

CSO

is required for stability

CSO

of current limit control circuitry (see Figure 1).

2.55

R

2.55

CSO

I

LIM

1

100

Ǔ

(eq. 3)

(eq. 4)

(eq. 5)

V

CSO

I

R

LIM

CSO

+ I

+

out

+

ǒ

100

1

100

R

1

CSO

Where
R
V
I

LIM

I

out

CSO

CSO

− current limit setting resistor

− voltage at CSO pin proportional to I

− current limit value

− output current actual value

out

CSO pin provides information about output current actual
value. The CSO voltage is proportional to output current
according to Equation 3.

Once output current reaches its limit value (I
external resistor R

2.55 V. Calculations of I

than voltage at CSO pin is typically

CSO

LIM

or R

values can be done

CSO

LIM

) set by

using equations Equation 4 and Equation 5, respectively.

Thermal Considerations

As power in the NCV47700 increases, it might become
necessary to provide some thermal relief. The maximum
power dissipation supported by the device is dependent
upon board design and layout. Mounting pad configuration
on the PCB, the board material, and the ambient temperature
affect the rate of junction temperature rise for the part. When
the NCV47700 has good thermal conductivity through the
PCB, the junction temperature will be relatively low with

high power applications. The maximum dissipation the
NCV47700 can handle is given by:

P

D(MAX)

+

ƪ

T

J(MAX)

R

qJA

* T

ƫ

A

(eq. 6)

Since TJ is not recommended to exceed 150°C, then the

NCV47700 soldered on 645 mm

2

, 1 oz copper area, FR4
can dissipate up to 1.8 W (SOIC−8 EP) or 1 W (SOIC−8) and
up to 4.3 W (SOIC−8 EP) or 1.6 W (SOIC−8) for 4 layers
PCB (all layers are 1 oz) when the ambient temperature (T
is 25°C. See Figure 18 for R

versus PCB area. The power

thJA

A

dissipated by the NCV47700 can be calculated from the
following equations:

PD+ V

in

ǒ

Iq@I

out

Ǔ

) I

out

ǒ

Vin* V

out

Ǔ

(eq. 7)

or

I

out

Ǔ

(eq. 8)

Hints

V

in(MAX)

[

P

D(MAX)

)ǒV

I

out

) I

out

q

Vin and GND printed circuit board traces should be as
wide as possible. When the impedance of these traces is
high, there is a chance to pick up noise or cause the regulator
to malfunction. Place external components, especially the
output capacitor, as close as possible to the NCV47700 and
make traces as short as possible.

220

200

180

160

140

120

100

1 oz

80

60

SO−8 4 layers PCB

, THERMAL RESISTANCE (°C/W)

SO−8 EP 4 layers PCB

40

JA

q

R

20

0 100 200 300 400 500 600 700

COPPER HEAT SPREADER AREA (mm

Figure 18. Thermal Resistance vs. PCB Copper Area

2 oz

1 oz

2 oz

1 oz
2 oz

SO−8 single layer PCB

SO−8 EP single layer PCB

1 oz 2 oz

2

)

)

ORDERING INFORMATION

Device Output Voltage Marking Package Shipping

NCV47700PDAJR2G Adjustable 47700 SOIC−8 EP

(Pb−Free)

NCV47700DAJR2G Adjustable 47700 SOIC−8

(Pb−Free)

†For information on tape and reel specifications,including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

www.onsemi.com

10

2500 / Tape & Reel

2500 / Tape & Reel

†

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

8

1

SCALE 1:1

−Y−

−Z−

−X−

A

58

B

1

4

G

H

D

0.25 (0.010) Z

M

SOLDERING FOOTPRINT*

7.0

0.275

S

Y

0.25 (0.010)

C

SXS

SEATING
PLANE

0.10 (0.004)

1.52

0.060

4.0

0.155

CASE 751−07

M

M

Y

N

SOIC−8 NB

ISSUE AK

K

X 45

_

M

J

MARKING DIAGRAM*

8

XXXXX
ALYWX

1

XXXXX = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package

8

XXXXX

ALYWX

G

1

IC

IC

(Pb−Free)

DATE 16 FEB 2011

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.

MILLIMETERS

DIMAMIN MAX MIN MAX

4.80 5.00 0.189 0.197

B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050

M 0 8 0 8

____

N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244

INCHES

GENERIC

8

XXXXXX

AYWW

1

Discrete

XXXXXX = Specific Device Code
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package

8

XXXXXX

AYWW

1

Discrete

(Pb−Free)

G

0.6

0.024

1.270

0.050

SCALE 6:1

ǒ

inches

mm

Ǔ

*This information is generic. Please refer to

device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

STYLES ON PAGE 2

DOCUMENT NUMBER:

DESCRIPTION:

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.

© Semiconductor Components Industries, LLC, 2019

98ASB42564B

SOIC−8 NB

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 2

www.onsemi.com

STYLE 1:

PIN 1. EMITTER

2. COLLECTOR

3. COLLECTOR

4. EMITTER

5. EMITTER

6. BASE

7. BASE

8. EMITTER

STYLE 5:

PIN 1. DRAIN

2. DRAIN

3. DRAIN

4. DRAIN

5. GATE

6. GATE

7. SOURCE

8. SOURCE

STYLE 9:

PIN 1. EMITTER, COMMON

2. COLLECTOR, DIE #1

3. COLLECTOR, DIE #2

4. EMITTER, COMMON

5. EMITTER, COMMON

6. BASE, DIE #2

7. BASE, DIE #1

8. EMITTER, COMMON

STYLE 13:

PIN 1. N.C.

2. SOURCE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 17:

PIN 1. VCC

2. V2OUT

3. V1OUT

4. TXE

5. RXE

6. VEE

7. GND

8. ACC

STYLE 21:

PIN 1. CATHODE 1

2. CATHODE 2

3. CATHODE 3

4. CATHODE 4

5. CATHODE 5

6. COMMON ANODE

7. COMMON ANODE

8. CATHODE 6

STYLE 25:

PIN 1. VIN

2. N/C

3. REXT

4. GND

5. IOUT

6. IOUT

7. IOUT

8. IOUT

STYLE 29:

PIN 1. BASE, DIE #1

2. EMITTER, #1

3. BASE, #2

4. EMITTER, #2

5. COLLECTOR, #2

6. COLLECTOR, #2

7. COLLECTOR, #1

8. COLLECTOR, #1

STYLE 2:

PIN 1. COLLECTOR, DIE, #1

2. COLLECTOR, #1

3. COLLECTOR, #2

4. COLLECTOR, #2

5. BASE, #2

6. EMITTER, #2

7. BASE, #1

8. EMITTER, #1

STYLE 6:

PIN 1. SOURCE

2. DRAIN

3. DRAIN

4. SOURCE

5. SOURCE

6. GATE

7. GATE

8. SOURCE

STYLE 10:

PIN 1. GROUND

2. BIAS 1

3. OUTPUT

4. GROUND

5. GROUND

6. BIAS 2

7. INPUT

8. GROUND

STYLE 14:

PIN 1. N−SOURCE

2. N−GATE

3. P−SOURCE

4. P−GATE

5. P−DRAIN

6. P−DRAIN

7. N−DRAIN

8. N−DRAIN

STYLE 18:

PIN 1. ANODE

2. ANODE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. CATHODE

8. CATHODE

STYLE 22:

PIN 1. I/O LINE 1

2. COMMON CATHODE/VCC

3. COMMON CATHODE/VCC

4. I/O LINE 3

5. COMMON ANODE/GND

6. I/O LINE 4

7. I/O LINE 5

8. COMMON ANODE/GND

STYLE 26:

PIN 1. GND

2. dv/dt

3. ENABLE

4. ILIMIT

5. SOURCE

6. SOURCE

7. SOURCE

8. VCC

STYLE 30:

PIN 1. DRAIN 1

2. DRAIN 1

3. GATE 2

4. SOURCE 2

5. SOURCE 1/DRAIN 2

6. SOURCE 1/DRAIN 2

7. SOURCE 1/DRAIN 2

8. GATE 1

SOIC−8 NB

CASE 751−07

ISSUE AK

STYLE 3:

STYLE 7:

STYLE 11:

STYLE 15:

PIN 1. DRAIN, DIE #1

2. DRAIN, #1

3. DRAIN, #2

4. DRAIN, #2

5. GATE, #2

6. SOURCE, #2

7. GATE, #1

8. SOURCE, #1

PIN 1. INPUT

2. EXTERNAL BYPASS

3. THIRD STAGE SOURCE

4. GROUND

5. DRAIN

6. GATE 3

7. SECOND STAGE Vd

8. FIRST STAGE Vd

PIN 1. SOURCE 1

2. GATE 1

3. SOURCE 2

4. GATE 2

5. DRAIN 2

6. DRAIN 2

7. DRAIN 1

8. DRAIN 1

PIN 1. ANODE 1

2. ANODE 1

3. ANODE 1

4. ANODE 1

5. CATHODE, COMMON

6. CATHODE, COMMON

7. CATHODE, COMMON

8. CATHODE, COMMON

STYLE 19:

PIN 1. SOURCE 1

2. GATE 1

3. SOURCE 2

4. GATE 2

5. DRAIN 2

6. MIRROR 2

7. DRAIN 1

8. MIRROR 1

STYLE 23:

PIN 1. LINE 1 IN

2. COMMON ANODE/GND

3. COMMON ANODE/GND

4. LINE 2 IN

5. LINE 2 OUT

6. COMMON ANODE/GND

7. COMMON ANODE/GND

8. LINE 1 OUT

STYLE 27:

PIN 1. ILIMIT

2. OVLO

3. UVLO

4. INPUT+

5. SOURCE

6. SOURCE

7. SOURCE

8. DRAIN

DATE 16 FEB 2011

STYLE 4:

PIN 1. ANODE

2. ANODE

3. ANODE

4. ANODE

5. ANODE

6. ANODE

7. ANODE

8. COMMON CATHODE

STYLE 8:

PIN 1. COLLECTOR, DIE #1

2. BASE, #1

3. BASE, #2

4. COLLECTOR, #2

5. COLLECTOR, #2

6. EMITTER, #2

7. EMITTER, #1

8. COLLECTOR, #1

STYLE 12:

PIN 1. SOURCE

2. SOURCE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 16:

PIN 1. EMITTER, DIE #1

2. BASE, DIE #1

3. EMITTER, DIE #2

4. BASE, DIE #2

5. COLLECTOR, DIE #2

6. COLLECTOR, DIE #2

7. COLLECTOR, DIE #1

8. COLLECTOR, DIE #1

STYLE 20:

PIN 1. SOURCE (N)

2. GATE (N)

3. SOURCE (P)

4. GATE (P)

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 24:

PIN 1. BASE

2. EMITTER

3. COLLECTOR/ANODE

4. COLLECTOR/ANODE

5. CATHODE

6. CATHODE

7. COLLECTOR/ANODE

8. COLLECTOR/ANODE

STYLE 28:

PIN 1. SW_TO_GND

2. DASIC_OFF

3. DASIC_SW_DET

4. GND

5. V_MON

6. VBULK

7. VBULK

8. VIN

DOCUMENT NUMBER:

DESCRIPTION:

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.

© Semiconductor Components Industries, LLC, 2019

98ASB42564B

SOIC−8 NB

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 2 OF 2

www.onsemi.com

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

8

1

SCALE 1:1

SOIC−8 EP

CASE 751AC

ISSUE D

DATE 02 APR 2019

GENERIC

MARKING DIAGRAM*

8

XXXXX

AYWWG

G

1

DOCUMENT NUMBER:

DESCRIPTION:

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.

© Semiconductor Components Industries, LLC, 2018

XXXXXX = Specific Device Code
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package

98AON14029D

SOIC−8 EP

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

*This information is generic. Please refer to

device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”, may
or may not be present and may be in either
location. Some products may not follow the
Generic Marking.

PAGE 1 OF 1

www.onsemi.com

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
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application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
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claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.

. ON Semiconductor reserves the right to make changes without further notice to any products herein.

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1