ON Semiconductor NCV47551 User Manual

NCV47551

LDO Regulator - Adjustable,

Low Noise, Adjustable Current

3.3 V to 20 V

The NCV47551 is a low noise low output current integrated low dropout regulator designed for use in harsh automotive environments. It includes wide operating temperature and input voltage ranges. The device is offered with adjustable voltage versions available in 3% output voltage accuracy. It has a high peak input voltage tolerance and reverse input voltage protection. It also provides overcurrent protection, overtemperature protection and enable for control of the state of the output voltage. The integrated current sense feature provides diagnosis and system protection functionality. The current limit of the device is adjustable by resistor connected to CSO pin. Voltage on CSO pin is proportional to output current.

Features

• Adjustable Voltage Version (from 3.3 V to 20 V) ± 3% Output

Voltage

• Enable Input (3.3 V Logic Compatible Thresholds)

• Adjustable Current Limit (from 100 mA to 20 mA) with 10%

Accuracy

• Protection Features:

♦ Current Limitation ♦ Thermal Shutdown ♦ Reverse Input Voltage

• This is a Pb−Free Device

http://onsemi.com

MARKING DIAGRAM

8

1

47551 = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package

SOIC−8

SUFFIX D

CASE 751

47551 ALYW

G

1

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet.

Typical Applications

• Microphone Power Supply

• Audio and Infotainment System

• Navigation

• Satellite Radio

V

C

in

1 mF

C

*

noise

C

*, C

* − Optional for noise reduction.

b

noise

September, 2019 − Rev. 0

in

EN

NR

NCV47551

GND

Figure 1. Application Schematic

(See Application Section for more details)

V

ADJ

CSO

out

C

CSO

1 mF

Cb*

R

1

C

out

R

2

10 mF

R

CSO

1 Publication Order Number:

NCV47551/D

NCV47551

V

EN

NR

GND

in

V

NR

VOLTAGE

REFERENCE

ENABLE

SATURATION

PROTECTION

THERMAL

SHUTDOWN

NOISE

REDUCTION

V

SP

TSD

NR

REF1

REF2

PASS DEVICE

AND

CURRENT MIRROR

SP

TSD

= I

I

CSO

out

(Ratio 1:1)

V

REF2

+

2.55 V

−

V

REF1

+

1.265 V

−

V

out

CSO

ADJ

Figure 2. Simplified Block Diagram

18

ADJ

GND

EN

CSO

V

NC

NR

V

out

in

SOIC−8

Figure 3. Pin Connections

(Top View)

PIN FUNCTION DESCRIPTION

Pin No.

SOIC−8

Pin Name Description

1 ADJ Adjustable Voltage Setting Input. See Application Section for more details.

2 GND Power Supply Ground.

3 EN Enable Input; low level disables the IC.

4 CSO Current Sense Output, Current Limit setting and Output Current value information. See Application Section

for more details.

5 V

in

Positive Power Supply Input.

6 NR Noise Reduction Input. Connect either external capacitor for decreasing noise or must be left unconnected.

7 NC Not Connected.

8 V

out

Regulated Output Voltage.

http://onsemi.com

2

NCV47551

ABSOLUTE MAXIMUM RATINGS

Rating Symbol Min Max Unit

Input Voltage DC V

Enable Input Voltage V

Adjustable Input Voltage V

CSO Voltage V

Noise Reduction Input Voltage V

Output Voltage V

Junction Temperature T

Storage Temperature T

in

EN

ADJ

CSO

NR

out

J

STG

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

ESD CAPABILITY (Note 1)

Rating

ESD Capability, Human Body Model ESD

ESD Capability, Machine Model ESD

1. This device series incorporates ESD protection and is tested by the following methods:

ESD Human Body Model tested per AEC−Q100−002 (JS−001−2010) ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)

Symbol Min Max Unit

HBM

MM

−42 45 V

−0.3 10 V

−0.3 7 V

−1 40 V

−40 150 °C

−55 150 °C

−2 2 kV

−200 200 V

LEAD SOLDERING TEMPERATURE AND MSL (Note 2)

Rating

Moisture Sensitivity Level MSL 1 −

Lead Temperature Soldering

Reflow (SMD Styles Only), Pb−Free Versions

2. For more information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D

Symbol Min Max Unit

°C

T

SLD

− 265 peak

THERMAL CHARACTERISTICS (Note 3)

Rating Symbol Value Unit

Thermal Characteristics

Thermal Resistance, Junction−to−Air (Note 4) Thermal Reference, Junction−to−Lead (Note 4)

3. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.

4. Values based on copper area of 645 mm

2

(or 1 in2) of 1 oz copper thickness and FR4 PCB substrate.

R

θJA

R

ψJL

133

76

°C/W

RECOMMENDED OPERATING RANGES

Rating Symbol Min Max Unit

Input Voltage (Note 5) V

Nominal Output Voltage V

Output Current Limit (Note 6) I

Junction Temperature T

in

out_nom

LIM

J

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability.

5. Minimum V

6. Corresponding R

= 4.4 V or (V

in

is in range from 25.5 kW down to 127.5 W.

CSO

+ 1 V), whichever is higher.

out_nom

4.4 40 V

3.3 20 V

0.1 20 mA

−40 150 °C

http://onsemi.com

3

NCV47551

ELECTRICAL CHARACTERISTICS V

and Max values are valid for temperature range −40°C ≤ T statistical correlation. Typical values are referenced to T resistor divider R

and R2. (Note 7)

1

Parameter

= 13.5 V, VEN = 3.3 V, R

in

≤ +150°C unless noted otherwise and are guaranteed by test, design or

J

= 25°C. Output Current I

J

CSO

= 0 W, C

= 1 mF, Cin = 1 mF, C

CSO

is the current out of pin including current through the

out

= 10 mF, ESR = 1.5 W, Min

out

Test Conditions Symbol Min Typ Max Unit

REGULATOR OUTPUT

Output Voltage (Accuracy %) (Note 8)

Line Regulation (Note 8) Vin = V

Load Regulation I

Dropout Voltage (Note 9) I

Vin = V I

= 0.1 mA to 20 mA

out

I

= 0.1 mA

out

= 0.1 mA to 20 mA

out

V

= (V

in

= 10 mA, V

out

V

DO

in_min

out_nom

= Vin − V

to 40 V

to (V

out

out_nom

+ 8.5 V)

out_nom

+ 20 V)

= 5 V

V

Reg

V

out

DO

line

load

−3 − +3 %

− 0.1 1.0 %

− 0.2 1.4 %

− 210 500 mV

DISABLE AND QUIESCENT CURRENTS

Disable Current

Quiescent Current, Iq = Iin − I

VEN = 0 V I

outIout

= 0.1 mA, Vin = (V

= 1 mA, Vin = (V

out_nom

+ 8.5 V) I

out_nom

+ 8.5 V) I

DIS

− 0.075 10

q

− 265 380

− 1.45 3 mA

mA

CURRENT LIMIT PROTECTION

Current Limit

=

V

out

0.9 x V

out_nom

, Vin = (V

+ 8.5 V) I

out_nom

LIM

20 − 50 mA

PSRR AND NOISE

Power Supply Ripple Rejection (Note 10)

Output Noise Voltage (Note 10)

I

= 1 mA, R1 = 82 kW, R2 = 27 kW

out

C

= none, Cb = 10 nF, C

in

f = 100 Hz, 0.5 V f = 1 kHz, 0.5 V

I

= 1 mA, R1 = 82 kW, R2 = 27 kW, Cb = 10 nF

out

f = 10 Hz to 100 kHz, C

p−p

f = 10 Hz to 100 kHz, C f = 20 Hz to 20 kHz, C

noise noise

noise

= none = 10 nF

= 10 nF

PSRR

V

n

dB

−

85 90

60 23 20

−

mV

−

rms

−

ENABLE

Enable Input Threshold Voltage

Logic Low (OFF) Logic High (ON)

V

out

V

out

≤ 0.1 V ≥ 0.9 x V

out_nom

Enable Input Current VEN = 3.3 V I

Turn On Time

from ENABLE ON to 90% of V

out_nom

I

= 1 mA

out

= 82 kW, R2 = 27 kW

R

1

= 10 nF, C

C

b

noise

= 10 nF

V

th(EN)

EN

t

on

0.99

−

1.8

1.9

−

2.31

2 8 20

− 2.8 − ms

V

mA

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.

7. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at T cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.

8. V

9. Measured when the output voltage V

= 4.4 V or (V

in_min

10.Values based on design and/or characterization.

+ 1 V), whichever is higher.

out_nom

out

has dropped – 2% from the nominal value obtained at Vin = V

out_nom

+ 8.5 V.

≈ TJ. Low duty

A

11.Not guaranteed in dropout.

current at no load includes also mirrored current of resistor divider (I

12.I

CSO

div

= V

out

/ (R1 + R2)).

http://onsemi.com

4

NCV47551

ELECTRICAL CHARACTERISTICS V

and Max values are valid for temperature range −40°C ≤ T statistical correlation. Typical values are referenced to T resistor divider R

and R2. (Note 7)

1

= 13.5 V, VEN = 3.3 V, R

in

≤ +150°C unless noted otherwise and are guaranteed by test, design or

J

= 25°C. Output Current I

J

CSO

= 0 W, C

= 1 mF, Cin = 1 mF, C

CSO

is the current out of pin including current through the

out

= 10 mF, ESR = 1.5 W, Min

out

Parameter UnitMaxTypMinSymbolTest Conditions

OUTPUT CURRENT SENSE

CSO Voltage Level at Current Limit

CSO Transient Voltage Level

Output Current to CSO Current Ratio (Note 11)

CSO Current at no Load Current (Note 12)

V

= 0.9 x V

out

= 220 W

R

CSO

C

= 4.7 mF, R

CSO

pulse from 0.1 mA to 20 mA, tr = 1 ms

I

out

V

= 2 V

CSO

I

= 0.1 mA to 20 mA, (V

out

V

= 0 V

CSO

= 82 kW, R2 = 27 kW, Cb = 10 nF

R

1

out_nom

CSO

, (V

out_nom

= 220 W

out_nom

= 5 V)

V

CSO_Ilim

V

CSO

I

out/ICSO

I

CSO_off

2.346

(−8 %)

2.55 2.754 (+8 %)

− − 3.3 V

−

(−10%)

(1/1) −

(+10%)

− 47 60

V

−

mA

THERMAL SHUTDOWN

Thermal Shutdown Temperature (Note 10)

I

= 1 mA T

out

SD

150 − 195 °C

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.

7. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at T cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.

8. V

9. Measured when the output voltage V

= 4.4 V or (V

in_min

10.Values based on design and/or characterization.

+ 1 V), whichever is higher.

out_nom

out

has dropped – 2% from the nominal value obtained at Vin = V

out_nom

+ 8.5 V.

≈ TJ. Low duty

A

11.Not guaranteed in dropout.

current at no load includes also mirrored current of resistor divider (I

12.I

CSO

div

= V

out

/ (R1 + R2)).

http://onsemi.com

5

NCV47551

TYPICAL CHARACTERISTICS

1.31 Vin = 13.5 V

1.3 I

= 100 mA

out

1.29

1.28

1.27

1.26

1.25

, REFERENCE VOLTAGE (V)

1.24

1.23

REF1

V

1.22

−40 −20 0 20 40 60 80 100 160120 140

TJ, JUNCTION TEMPERATURE (°C)

Figure 4. Reference Voltage vs. Temperature Figure 5. Quiescent Current vs. Input Voltage

1.4

TJ = 25°C

1.2

I

= 100 mA

out

1

0.8

0.6

0.4

, REFERENCE VOLTAGE (V)

0.2

REF1

V

0

0.5 1.5 2.5 4.5 5.5

0123 56

, INPUT VOLTAGE (V)

V

in

3.5 4

Figure 6. Reference Voltage vs. Input Voltage Figure 7. Input Current vs. Input Voltage

450

400

350

300

250

200

150

100

, QUIESCENT CURRENT (mA)

q

50

I

0

TJ = 25°C I

= 100 mA

out

V

out_nom

0 5 10 15 20 25 4030 35

V

, INPUT VOLTAGE (V)

in

0

TJ = 25°C

−0.1 R

= 4.7 kW

−0.2

out

V

out_nom

= 5 V

−0.3

−0.4

−0.5

−0.6

−0.7

, INPUT CURRENT (mA)

−0.8

in

I

−0.9

−1.0

−45 −40 −35 −30 −25 −20 −5−15 −10 0

, INPUT VOLTAGE (V)

V

in

(Reverse Input Voltage)

= 5 V

500

Vin = 13.5 V

450

400

350

V

out_nom

= 5 V

TJ = 150°C

300

250

TJ = 25°C

200

150

, DROPOUT VOLTAGE (mV)

100

DO

V

50

0

02468 161820

I

, OUTPUT CURRENT (mA)

out

TJ = −40°C

10 12 14

Figure 8. Dropout vs. Output Current Figure 9. Output Current Limit vs. Input

42

40

38

36

34

32

30

28

26

, OUTPUT CURRENT LIMIT (mA)

24

LIM

I

22

http://onsemi.com

6

V

= 4.5 V

out

out_nom

= 0 W

CSO

= 5 V

TJ = −40°C

V R

TJ = 25°C

TJ = 150°C

0 5 10 15 20 25 30 35

, INPUT VOLTAGE (V)

V

in

Voltage

40 45

NCV47551

TYPICAL CHARACTERISTICS

25

V

= 3.3 V to 20 V

out

= 25°C

T

20

J

15

10

5

, OUTPUT CURRENT LIMIT (mA)

LIM

I

0

0.1 10 100

1

R

, (kW)

CSO

Figure 10. Output Current Limit vs. R

10

TJ = 25°C

9

= V

V

in

8

out_nom

+ 8.5 V

7

6

5

4

3

2

, QUIESCENT CURRENT (mA)

q

I

1

0

012

, OUTPUT CURRENT (mA)

I

out

Figure 12. Quiescent Current vs. Output Current

(Low Load)

43

CSO

3.0 V

= 3.3 V to 20 V

out

= 25°C

T

J

2.5 I

= 0.1 mA to 20 mA

LIM

2.0

1.5

1.0

, CSO VOLTAGE (V)

CSO

V

0.5

0

0 10 20 30 100 110

I

out

Figure 11. Output Current (% of I

40

TJ = 25°C

35

= V

V

in

out_nom

30

25

20

15

10

, QUIESCENT CURRENT (mA)

5

q

I

5

0

0510

Figure 13. Quiescent Current vs. Output Current

, OUTPUT CURRENT (% of I

Voltage

LIM

+ 8.5 V

15 20

, OUTPUT CURRENT (mA)

I

out

(High Load)

90807040 50 60 )

LIM

) vs. CSO

25

1.12 TJ = 25°C

1.1 V

in

1.08

1.06

1.04

1.02

1

0.98

0.96

, OUTPUT CURRENT TO

0.94

CSO

CSO CURRENT RATIO (−)

0.92

/I

out

0.9

I

0.88

0.1 10 1001

= V

+ 8.5 V

out_nom

I

, OUTPUT CURRENT (mA)

out

Figure 14. Output Current to CSO Current

Ratio vs. Output Current

http://onsemi.com

1

0.95

0.9

0.85

0.8

0.75

, OUTPUT CURRENT TO

CSO

/I

out

I

0.7

CSO CURRENT RATIO (−)

0.65

0.6

TJ = 25°C

= 4.5 V

V

in

V

out_nom

= 5 V

0.1 10 1001 , OUTPUT CURRENT (mA)

I

out

Figure 15. Output Current to CSO Current

Ratio vs. Output Current (In Dropout)

7

NCV47551

TYPICAL CHARACTERISTICS

1000

Unstable Region

Area above curves

100

TJ = 25°C

= V

V

in

out_nom

C

= 1 mF − 100 mF

out

C

= none

b

+ 8.5 V

10

V

1

ESR (W)

0.1

out_nom

= 20 V

V

= 5 V

out_nom

Stable Region

V

out_nom

= 3.3 V

Area below curves

0.01 04 20

2 8 10 100 1000 10000 1000000100000

61012141618

, OUTPUT CURRENT (mA)

I

out

Figure 16. Output Capacitor Stability Region

vs. Output Current

120

110

C

= 100 nF

100

noise

90

80

70

PSRR (dB)

60

TJ = 25°C

50

V

in

40

V

out_nom

C

30

b

C

= none

noise

= 13.5 V (DC) + 0.5 VPP (AC)

= 5 V, I

= 1 mA

out

= 10 nF

10 100 1000 10000 100000

FREQUENCY (Hz)

Figure 18. PSRR vs. Frequency

)

3000

1/2

V

= 16.7 mV

C

noise

n

Vn = 26.1 mV

= 10 nF

2500

2000

1500

C

1000

noise

500

, OUTPUT NOISE DENSITY (nV/Hz

n

0

V

FREQUENCY (Hz)

Figure 17. Noise vs. Frequency

C

= 10 nF

noise

Noise 10 Hz − 100 kHz

@ C

rms

noise

@ C

rms

noise

TJ = 25°C

= 12 V

V

in

C

= 100 nF

= 10 nF

b

V

out_nom

I

= 20 mA

out

= 100 nF

= 10 nF

= 5 V

http://onsemi.com

8

NCV47551

DEFINITIONS

General

All measurements are performed using short pulse low duty cycle techniques to maintain junction temperature as close as possible to ambient temperature.

Output voltage

The output voltage parameter is defined for specific temperature, input voltage and output current values or specified over Line, Load and Temperature ranges.

Line Regulation

The change in output voltage for a change in input voltage measured for specific output current over operating ambient temperature range.

Load Regulation

The change in output voltage for a change in output current measured for specific input voltage over operating ambient temperature range.

Dropout Voltage

The input to output differential at which the regulator output no longer maintains regulation against further reductions in input voltage. It is measured when the output voltage V obtained at V

has dropped −2% from the nominal value

out

in

= V

+ 8.5 V. The junction temperature,

out_nom

load current, and minimum input supply requirements affect the dropout level.

reduces its internal bias and shuts off the output, this term is called the disable current (I

Current Limit

DIS

).

Current Limit is value of output current by which output

voltage drops below 90% of its nominal value.

PSRR

Power Supply Rejection Ratio is defined as ratio of output voltage and input voltage ripple. It is measured in decibels (dB).

Line Transient Response

Typical output voltage overshoot and undershoot response when the input voltage is excited with a given slope.

Load Transient Response

Typical output voltage overshoot and undershoot response when the output current is excited with a given slope between low-load and high-load conditions.

Thermal Protection

Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. When activated at typically 175°C, the regulator turns off. This feature is provided to prevent failures from accidental overheating.

Quiescent and Disable Currents

Quiescent Current (Iq) is the difference between the input current (measured through the LDO input pin) and the output load current. If Enable pin is set to LOW the regulator

Maximum Package Power Dissipation

The power dissipation level is maximum allowed power dissipation for particular package or power dissipation at which the junction temperature reaches its maximum operating value, whichever is lower.

http://onsemi.com

9

NCV47551

APPLICATIONS INFORMATION

Circuit Description

The NCV47551 is an integrated low dropout regulator that provides a regulated voltage at 20 mA to the output. It is enabled with an input to the enable pin. The regulator voltage is provided by a PNP pass transistor controlled by an error amplifier with a bandgap reference, which gives it the lowest possible dropout voltage. The output current capability is 20 mA, and the base drive quiescent current is controlled to prevent oversaturation when the input voltage is low or when the output is overloaded. The integrated

current sense feature provides diagnosis and system protection functionality. The current limit of the device is adjustable by resistor connected to CSO pin. Voltage on CSO pin is proportional to output current. The regulator is

protected by both current limit and thermal shutdown. Thermal shutdown occurs above 150°C to protect the IC during overloads and extreme ambient temperatures.

Regulator

The error amplifier compares the reference voltage to a sample of the output voltage (V

) and drives the base of a

out

PNP series pass transistor via a buffer. The reference is a bandgap design to give it a temperature−stable output. Saturation control of the PNP is a function of the load current and input voltage. Oversaturation of the output power device is prevented, and quiescent current in the ground pin is minimized.

Regulator Stability Considerations

The input capacitor (Cin) is necessary to stabilize the input impedance to avoid voltage line influences. The output capacitor (C

) helps determine three main characteristics

out

of a linear regulator: startup delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (−25°C to −40°C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturer’s data sheet usually provides this information. The value for the output capacitor C

, shown in Figure 1 should work for

out

most applications; see also Figure 14 for output stability at various load and Output Capacitor ESR conditions. Stable region of ESR in Figure 14 shows ESR values at which the LDO output voltage does not have any permanent oscillations at any dynamic changes of output load current. Marginal ESR is the value at which the output voltage waving is fully damped during four periods after the load change and no oscillation is further observable.

ESR characteristics were measured with ceramic capacitors and additional series resistors to emulate ESR. Low duty cycle pulse load current technique has been used to maintain junction temperature close to ambient temperature.

Enable Input

The enable pin is used to turn the regulator on or off. By holding the pin down to a voltage less than 0.99 V, the output of the regulator will be turned off. When the voltage on the enable pin is greater than 2.31 V, the output of the regulator will be enabled to power its output to the regulated output voltage. The enable pin may be connected directly to the input pin to give constant enable to the output regulator.

Setting the Output Voltage

The output voltage range can be set between 3.3 V and 20 V. This is accomplished with an external resistor divider feeding back the voltage to the IC back to the error amplifier by the voltage adjust pin ADJ. The internal reference voltage is set to a temperature stable reference (V

) of 1.265 V.

REF1

The output voltage is calculated from the following formula. Ignoring the bias current into the ADJ pin:

R

V

out_nom

+ V

REF1

ǒ

1 )

1

R

2

Ǔ (eq. 1)

Use R2 < 50 kW to avoid significant voltage output errors due to ADJ bias current.

Designers should consider the tolerance of R

and R

1

during the design phase.

Setting the Output Current Limit

The output current limit can be set between 0.1 mA and 20 mA by external resistor R

from range 1 mF to 4.7 mF in parallel with R

C

CSO

(see Figure 1). Capacitor

CSO

is required for stability of current limit control circuitry (see Figure 1).

V

+ I

CSO

R

I

LIM

CSO

+

out

+

R

2.55

R

2.55

CSO

I

LIM

CSO

(eq. 2)

(eq. 3)

(eq. 4)

Where R V I I

CSO

LIM

out

− current limit setting resistor

 voltage at CSO pin proportional to I

− current limit value

− output current actual value

out

CSO pin provides information about output current actual value. The CSO voltage is proportional to output current according to Equation 2.

Once output current reaches its limit value (I external resistor R

2.55 V. Calculations of I

than voltage at CSO pin is typically

CSO

LIM

or R

values can be done

CSO

LIM

) set by

using equations Equations 3 and 4, respectively.

Designers should consider the tolerance of R

CSO

during

the design phase.

2

http://onsemi.com

10

NCV47551

Thermal Considerations

As power in the NCV47551 increases, it might become necessary to provide some thermal relief. The maximum power dissipation supported by the device is dependent upon board design and layout. Mounting pad configuration on the PCB, the board material, and the ambient temperature affect the rate of junction temperature rise for the part. When the NCV47551 has good thermal conductivity through the PCB, the junction temperature will be relatively low with high power applications. The maximum dissipation the NCV47551 can handle is given by:

240

220

200

180

160

P

D(MAX)

1 oz, Single Layer

+

ƪ

T

J(MAX)

R

qJA

* T

ƫ

A

(eq. 5)

Since TJ is not recommended to exceed 150°C, then the

NCV47551 in SO-8 soldered on 645 mm

2

, 1 oz copper area, FR4 can dissipate up to 0.94 W when the ambient temperature (T

) is 25°C. See Figure 19 for R

A

thJA

versus PCB area. The power dissipated by the NCV47551 can be calculated from the following equations:

PD[ V

in

ǒ

Iq@I

out

Ǔ

) I

out

ǒ

Vin* V

out

Ǔ

(eq. 6)

or

I

out

Ǔ

(eq. 7)

Hints

V

in(MAX)

[

P

D(MAX)

)ǒV

I

out

) I

out

q

Vin and GND printed circuit board traces should be as wide as possible. When the impedance of these traces is high, there is a chance to pick up noise or cause the regulator to malfunction. Place external components, especially the output capacitor, as close as possible to the NCV47551 and make traces as short as possible.

140

, THERMAL RESISTANCE (°C/W)

120

JA

q

R

100

0 700

2 oz, Single Layer

100 200 300 400 500 600

COPPER HEAT SPREADER AREA (mm

2

)

Figure 19. Thermal Resistance vs. PCB Copper Area

ORDERING INFORMATION

Device Output Voltage Marking Package Shipping

NCV47551DAJR2G Adjustable 47551 SOIC−8

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

2500 / Tape & Reel

†

http://onsemi.com

11

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

8

1

SCALE 1:1

B

−Y−

−Z−

−X−

A

58

1

4

G

H

D

0.25 (0.010) Z

M

SOLDERING FOOTPRINT*

7.0

0.275

SOIC−8 NB

CASE 751−07

ISSUE AK

DATE 16 FEB 2011

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

S

0.25 (0.010)

M

Y

K

Y

C

SXS

SEATING PLANE

0.10 (0.004)

N

X 45

_

M

J

PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07.

MILLIMETERS

DIMAMIN MAX MIN MAX

4.80 5.00 0.189 0.197

B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.053 0.069 D 0.33 0.51 0.013 0.020 G 1.27 BSC 0.050 BSC H 0.10 0.25 0.004 0.010

J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050 M 0 8 0 8

____

N 0.25 0.50 0.010 0.020

S 5.80 6.20 0.228 0.244

INCHES

GENERIC

MARKING DIAGRAM*

8

XXXXXX

AYWW

1

Discrete

(Pb−Free)

G

1.52

0.060

4.0

0.155

8

XXXXX ALYWX

1

8

XXXXX ALYWX

G

1

IC

(Pb−Free)

XXXXX = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package

8

XXXXXX

AYWW

1

Discrete

XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package

0.6

0.024

1.270

0.050

SCALE 6:1

ǒ

inches

mm

Ǔ

*This information is generic. Please refer to

device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking.

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

STYLES ON PAGE 2

DOCUMENT NUMBER:

DESCRIPTION:

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others.

98ASB42564B

SOIC−8 NB

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 2

www.onsemi.com

STYLE 1:

PIN 1. EMITTER

2. COLLECTOR

3. COLLECTOR

4. EMITTER

5. EMITTER

6. BASE

7. BASE

8. EMITTER

STYLE 5:

PIN 1. DRAIN

2. DRAIN

3. DRAIN

4. DRAIN

5. GATE

6. GATE

7. SOURCE

8. SOURCE

STYLE 9:

PIN 1. EMITTER, COMMON

2. COLLECTOR, DIE #1

3. COLLECTOR, DIE #2

4. EMITTER, COMMON

5. EMITTER, COMMON

6. BASE, DIE #2

7. BASE, DIE #1

8. EMITTER, COMMON

STYLE 13:

PIN 1. N.C.

2. SOURCE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 17:

PIN 1. VCC

2. V2OUT

3. V1OUT

4. TXE

5. RXE

6. VEE

7. GND

8. ACC

STYLE 21:

PIN 1. CATHODE 1

2. CATHODE 2

3. CATHODE 3

4. CATHODE 4

5. CATHODE 5

6. COMMON ANODE

7. COMMON ANODE

8. CATHODE 6

STYLE 25:

PIN 1. VIN

2. N/C

3. REXT

4. GND

5. IOUT

6. IOUT

7. IOUT

8. IOUT

STYLE 29:

PIN 1. BASE, DIE #1

2. EMITTER, #1

3. BASE, #2

4. EMITTER, #2

5. COLLECTOR, #2

6. COLLECTOR, #2

7. COLLECTOR, #1

8. COLLECTOR, #1

STYLE 2:

PIN 1. COLLECTOR, DIE, #1

2. COLLECTOR, #1

3. COLLECTOR, #2

4. COLLECTOR, #2

5. BASE, #2

6. EMITTER, #2

7. BASE, #1

8. EMITTER, #1

STYLE 6:

PIN 1. SOURCE

2. DRAIN

3. DRAIN

4. SOURCE

5. SOURCE

6. GATE

7. GATE

8. SOURCE

STYLE 10:

PIN 1. GROUND

2. BIAS 1

3. OUTPUT

4. GROUND

5. GROUND

6. BIAS 2

7. INPUT

8. GROUND

STYLE 14:

PIN 1. N−SOURCE

2. N−GATE

3. P−SOURCE

4. P−GATE

5. P−DRAIN

6. P−DRAIN

7. N−DRAIN

8. N−DRAIN

STYLE 18:

PIN 1. ANODE

2. ANODE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. CATHODE

8. CATHODE

STYLE 22:

PIN 1. I/O LINE 1

2. COMMON CATHODE/VCC

3. COMMON CATHODE/VCC

4. I/O LINE 3

5. COMMON ANODE/GND

6. I/O LINE 4

7. I/O LINE 5

8. COMMON ANODE/GND

STYLE 26:

PIN 1. GND

2. dv/dt

3. ENABLE

4. ILIMIT

5. SOURCE

6. SOURCE

7. SOURCE

8. VCC

STYLE 30:

PIN 1. DRAIN 1

2. DRAIN 1

3. GATE 2

4. SOURCE 2

5. SOURCE 1/DRAIN 2

6. SOURCE 1/DRAIN 2

7. SOURCE 1/DRAIN 2

8. GATE 1

SOIC−8 NB

CASE 751−07

ISSUE AK

STYLE 3:

STYLE 7:

STYLE 11:

STYLE 15:

STYLE 19:

STYLE 23:

PIN 1. DRAIN, DIE #1

2. DRAIN, #1

3. DRAIN, #2

4. DRAIN, #2

5. GATE, #2

6. SOURCE, #2

7. GATE, #1

8. SOURCE, #1

PIN 1. INPUT

2. EXTERNAL BYPASS

3. THIRD STAGE SOURCE

4. GROUND

5. DRAIN

6. GATE 3

7. SECOND STAGE Vd

8. FIRST STAGE Vd

PIN 1. SOURCE 1

2. GATE 1

3. SOURCE 2

4. GATE 2

5. DRAIN 2

6. DRAIN 2

7. DRAIN 1

8. DRAIN 1

PIN 1. ANODE 1

2. ANODE 1

3. ANODE 1

4. ANODE 1

5. CATHODE, COMMON

6. CATHODE, COMMON

7. CATHODE, COMMON

8. CATHODE, COMMON

PIN 1. SOURCE 1

2. GATE 1

3. SOURCE 2

4. GATE 2

5. DRAIN 2

6. MIRROR 2

7. DRAIN 1

8. MIRROR 1

PIN 1. LINE 1 IN

2. COMMON ANODE/GND

3. COMMON ANODE/GND

4. LINE 2 IN

5. LINE 2 OUT

6. COMMON ANODE/GND

7. COMMON ANODE/GND

8. LINE 1 OUT

STYLE 27:

PIN 1. ILIMIT

2. OVLO

3. UVLO

4. INPUT+

5. SOURCE

6. SOURCE

7. SOURCE

8. DRAIN

DATE 16 FEB 2011

STYLE 4:

PIN 1. ANODE

2. ANODE

3. ANODE

4. ANODE

5. ANODE

6. ANODE

7. ANODE

8. COMMON CATHODE

STYLE 8:

PIN 1. COLLECTOR, DIE #1

2. BASE, #1

3. BASE, #2

4. COLLECTOR, #2

5. COLLECTOR, #2

6. EMITTER, #2

7. EMITTER, #1

8. COLLECTOR, #1

STYLE 12:

PIN 1. SOURCE

2. SOURCE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 16:

PIN 1. EMITTER, DIE #1

2. BASE, DIE #1

3. EMITTER, DIE #2

4. BASE, DIE #2

5. COLLECTOR, DIE #2

6. COLLECTOR, DIE #2

7. COLLECTOR, DIE #1

8. COLLECTOR, DIE #1

STYLE 20:

PIN 1. SOURCE (N)

2. GATE (N)

3. SOURCE (P)

4. GATE (P)

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 24:

PIN 1. BASE

2. EMITTER

3. COLLECTOR/ANODE

4. COLLECTOR/ANODE

5. CATHODE

6. CATHODE

7. COLLECTOR/ANODE

8. COLLECTOR/ANODE

STYLE 28:

PIN 1. SW_TO_GND

2. DASIC_OFF

3. DASIC_SW_DET

4. GND

5. V_MON

6. VBULK

7. VBULK

8. VIN

DOCUMENT NUMBER:

DESCRIPTION:

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others.

98ASB42564B

SOIC−8 NB

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 2 OF 2

www.onsemi.com

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

. ON Semiconductor reserves the right to make changes without further notice to any products herein.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT: Email Requests to: orderlit@onsemi.com

ON Semiconductor Website: www.onsemi.com

TECHNICAL SUPPORT North American Technical Support:

Voice Mail: 1 800−282−9855 Toll Free USA/Canada Phone: 011 421 33 790 2910

Europe, Middle East and Africa Technical Support:

Phone: 00421 33 790 2910 For additional information, please contact your local Sales Representative

◊

www.onsemi.com

1

ON Semiconductor NCV47551 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual