ON Semiconductor NCV4299 Technical data

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NCV4299

150 mA Low−Dropout
Voltage Regulator

The NCV4299 i s a f amily o f preci sion m icropower v oltage r egulators

with an output current capability of 150 mA. It is available in 5.0 V or

3.3 V output voltage, and is housed in an 8−lead SO N and in a 14−lead
SON (fused) package.

The output voltage is accurate within "2% with a maximum
dropout voltage of 0.5 V at 100 mA. Low Quiescent current is a
feature drawing only 90 mA with a 1 mA load. This part is ideal for any
and all battery operated microprocessor equipment.

The device features microprocessor interfaces including an
adjustable reset output and adjustable system monitor to provide
shutdown early warning. An inhibit function is available on the
14−lead part. With inhibit active, the regulator turns off and the device
consumes less than 1.0 mA of quiescent current.

The part can withstand load dump transients making it suitable for
use in automotive environments.

Features

• 5.0 V, 3.3 V "2%, 150 mA

• Extremely Low Current Consumption

♦ 90 mA (Typ) in the ON Mode
♦ t1.0 mA in the Off Mode

• Early Warning

• Reset Output Low Down to V

• Adjustable Reset Threshold

• Wide Temperature Range

• Fault Protection

♦ 60 V Peak Transient Voltage
♦ −40 V Reverse Voltage
♦ Short Circuit
♦ Thermal Overload

• Internally Fused Leads in the SO−14 Package

• Inhibit Function with mA Current Consumption in the Off Mode

• NCV Prefix for Automotive and Other Applications Requiring Site

and Change Control

• Pb−Free Packages are Available

= 1.0 V

Q

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8

1

14

1

xx = 33 (3.3 V Version)

A = Assembly Location
L, WL = Wafer Lot
Y = Year
W, WW = Work Week
G = Pb−Free Package
G = Pb−Free Package
(Note: Microdot may be in either location)

SO−8
D SUFFIX
CASE 751

14

SO−14

D SUFFIX

CASE 751A

= 50 (5.0 V Version)

PIN CONNECTIONS

18

1

14

1

MARKING

DIAGRAMS

8

4299

ALYW

G

1

NCV4299G

AWLYWW

V4299xxG

AWLYWW

QI
SOSI

RORADJ
GNDD

© Semiconductor Components Industries, LLC, 2006

April, 2006 − Rev. 16

114

ORDERING INFORMATION

See detailed ordering and shipping information in the package
dimensions section on page 21 of this data sheet.

1 Publication Order Number:

SIRADJ
ID
GNDGND
GNDGND

GNDGND
QINH
SORO

NCV4299/D

NCV4299

RADJ

I

Current Limit and

Bandgap

Reference

SI

−
+

1.36 V
+

−

Saturation Sense

+
+

−

8 mA

1.85 V

D GND

−
+

R

SO

Q

R

RO

SO

RO

Figure 1. SO−8 Simplified Block Diagram

PIN FUNCTION DESCRIPTION − SO−8 PACKAGE

Pin Symbol Description

1 I Input. Battery Supply Input Voltage. Bypass directly to GND with ceramic capacitor.
2 SI Sense Input. Can provide an early warning signal of an impending reset condition when used with SO.

3 RADJ Reset Adjust. Use resistor divider to Q to adjust reset threshold lower. Connect to GND if not used.
4 D Reset Delay. Connect external capacitor to ground to set delay time.
5 GND Ground.
6 RO

7 SO

8 Q

Connect to Q if not used.

Reset Output. NPN collector output with internal 20 kW pullup to Q. Notifies user of out of regulation condi-
tion. Leave open if not used.

Sense Output. NPN collector output with internal 20 kW pullup to Q. Can be used to provide early warning
of an impending reset condition. Leave open if not used.

5.0 V, 3.3 V, "2%, 150 mA out put. Use 22 mF, ESR t 5.0 W to ground.

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2

NCV4299

INH

RADJ

I

Current Limit and

Bandgap

Reference

SI

−
+

1.36 V
+

−

Saturation Sense

+
+

−

8 mA

1.85 V

D GND

−
+

R

SO

Q

R

RO

SO

RO

Figure 2. SO−14 Simplified Block Diagram

PIN FUNCTION DESCRIPTION − SO−14 PACKAGE

Pin Symbol Description

1 RADJ Reset Adjust. Use resistor divider to Q to adjust reset threshold lower. Connect to GND if not used.
2 D Reset Delay. Connect external capacitor to ground to set delay time.
3 GND Ground.
4 GND Ground.
5 GND Ground.
6 INH Inhibit. Connect to I if not needed. A high turns the regulator on.
7 RO

8 SO

9 Q
10 GND Ground.
11 GND Ground.
12 GND Ground.
13 I Input. Battery Supply Input Voltage.
14 SI Sense Input. Can provide an early warning signal of an impending reset condition when used with SO.

Reset Output. NPN collector output with internal 20 kW pullup to Q. Notifies user of out of regulation condi-
tion.

Sense Output. NPN collector output with internal 20 kW pullup to Q. Can be used to provide early warning
of an impending reset condition.

5.0 V, 3.3 V, "2%, 150 mA out put. Use 22 mF, ESR t 5.0 W to ground.

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NCV4299

MAXIMUM RATINGS

Rating Symbol Min Max Unit

Input Voltage to Regulator (DC) V

I

Input Peak Transient Voltage to Regulator wrt GND − − 60 V
Inhibit (INH) (Note 1) V
Sense Input (SI) V
Sense Input (SI) I
Reset Threshold (RADJ) V
Reset Threshold (RADJ) I
Reset Delay (D) V
Reset Output (RO) V
Sense Output (SO) V
Output (Q) V
Output (Q) I

ESD Capability, Human Body Model (Note 5) ESD
ESD Capability, Machine Model (Note 5) ESD

ESD Capability, Charged Device Model (Note 5) ESD
Junction Temperature T
Storage Temperature T

INH

SI

SI

RE

RE

D

RO

SO

Q

Q

HB

MM

CDM

J

stg

−40 45 V

−40 45 V

−0.3 45 V

−1.0 1.0 mA

−0.3 7.0 V

−10 10 mA

−0.3 7.0 V

−0.3 7.0 V

−0.3 7.0 V

−0.3 16 V

−5.0 − mA

2.0 − kV

200 − V

1.0 − kV

− 150 °C

−50 150 °C

OPERATING RANGE

Input Voltage

5.0 V Version

3.3 V Version

Junction Temperature T

V

I

J

4.5

4.4

45
45

−40 150 °C

V

LEAD TEMPERATURE SOLDERING REFLOW (Note 3)

Lead Temperature Soldering (Note 5)
Reflow (SMD styles only), leaded
60−150 sec above 183, 30 sec max at peak

Reflow (SMD styles only), lead free
60s−150 sec above 217, 40 sec max at peak

Moisture Sensitivity Level MSL Level 1

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.

1. 14 pin package only.

2. Preliminary numbers.

3. Per IPC / JEDEC J−STD−020C.

4. Measured to Pin 4. All ground pins connected to ground.

5. This device series incorporates ESD protection and is tested by the following methods:
ESD HBM tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD MM tested per AEC−Q100−003 (EIA/JESD22−A115)
ESD CDM tested per EIA/JES D22/C101, Field Induced Charge Model.

T

SLD

°C

− 240 Pk

T

SLD

− 265 Pk

°C

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THERMAL CHARACTERISTICS

Characteristic

SO−8

SO−14

6. 2 oz Copper, 50 mm sq Copper area, 1.5 mm thick FR4

7. 2 oz Copper, 150 mm sq Copper area, 1.5 mm thick FR4

8. 2 oz Copper, 500 mm sq Copper area, 1.5 mm thick FR4

Junction−to−Tab (y
Junction−to−Ambient (R

Junction−to−Tab (y
Junction−to−Ambient (R

JLx

JLx

, q

, q

θ

θ

JLx

JA

JLx

JA

)

, qJA)

)

, qJA)

NCV4299

Test Conditions (Typical Value)

Note 6 Note 7 Note 8

54

172

19

112

52

144

21
89

48

118

20
67

Unit

°C/W

°C/W

ELECTRICAL CHARACTERISTICS (−40°C < T

Characteristic Symbol Test Conditions Min Typ Max Unit

Output Q

Output Voltage (5.0 V Version) V
Output Voltage (3.3 V Version) V
Current Limit I
Quiescent Current (Iq = II – IQ) I
Quiescent Current (Iq = II – IQ) I
Quiescent Current (Iq = II – IQ) I
Quiescent Current (Iq = II – IQ) I
Quiescent Current (Iq = II – IQ) I
Dropout Voltage (Note 9) V
Load Regulation
Line Regulation
Power Supply Ripple Rejection P

Inhibit (INH) (14 Pin Package Only)

Inhibit Off Voltage V
Inhibit On Voltage

5.0 V Version

3.3 V Version

DV
DV

SRR

INHOFFVQ

V

INHON

< 150°C; VI = 13.5 V unless otherwise noted.)

J

1.0 mA < IQ < 150 mA, 6.0 V < VI < 16 V 4.9 5.0 5.1 V

Q

1.0 mA < IQ < 150 mA, 5.5 V < VI < 16 V 3.23 3.3 3.37 V

Q

Q

INH ON, IQ < 1.0 mA, TJ = 25°C − 86 100

q

INH ON, IQ < 1.0 mA − 90 105

q

INH ON, IQ = 10 mA − 170 500

q

INH ON, IQ = 50 mA − 0.7 2.0 mA

q

INH = 0 V, TJ = 25°C − − 1.0

q

IQ = 100 mA − 0.22 0.50 V

dr

IQ = 1.0 mA to 100 mA − 5.0 30 mV

Q

VI = 6.0 V to 28 V, IQ = 1.0 mA − 10 25 mV

Q

− 250 400 500 mA

ƒr = 100 Hz, Vr = 1.0 Vpp, IQ = 100 mA − 66 − dB

< 1.0 V − − 0.8 V

VQ > 4.85 V
VQ > 3.2 V

3.5

3.5

−

−

mA
mA
mA

mA

V

−

−

Input Current I

INHON

I

INHOFF

INH ON
INH = 0 V

−

−

Reset (RO)

Switching Threshold

5.0 V Version

3.3 V Version
Output Resistance R
Reset Output Low Voltage

5.0 V Version

3.3 V Version
Allowable External Reset Pullup Resistor V
Delay Upper Threshold V
Delay Lower Threshold V

V

rt

RO

V

RO

ROext

UD

LD

−

4.50

2.96

− 10 20 40

Q < 4.5 V, Internal RRO, IRO = −1.0 mA

−−0.17

Q < 2.96 V, Internal RRO, IRO = −1.0 mA
External Resistor to Q 5.6 − −

− 1.5 1.85 2.2 V

− 0.4 0.5 0.6 V

9. Measured when the output voltage VQ has dropped 100 mV from the nominal value obtained at VI = 13.5 V.

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5

3.0

0.5102.0

4.60

4.80

3.06

3.16

0.40

0.17

0.40

mA

V

kW

V

kW

NCV4299

ELECTRICAL CHARACTERISTICS (continued) (−40°C < T

< 150°C; VI = 13.5 V unless otherwise noted.)

J

Characteristic Symbol Test Conditions Min Typ Max Unit

Reset (RO)

Delay Output Low Voltage

5.0 V Version

3.3 V Version
Delay Charge Current

5.0 V Version

3.3 V Version
Power On Reset Delay Time t
Reset Reaction Time t
Reset Adjust Switching Threshold

5.0 V Version

3.3 V Version

V

I

D

rr

V

RADJ,TH

D

Q < 4.5 V, Internal R
Q < 2.96 V, Internal R

Q < 4.5 V, Internal RRO, VD = 1.0 V
Q < 2.96 V, Internal RRO, VD = 1.0 V

C

d

= 100 nF 17 28 35 ms

D

C

= 100 nF 0.5 2.2 4.0

D

Q > 3.5 V
Q > 2.3 V

RO

RO

Input Voltage Sense (SI and SO)

Sense Input Threshold High V
Sense Input Threshold Low V

SI,HIGH

SI,LOW

− 1.34 1.45 1.54 V

− 1.26 1.36 1.44 V

Sense Input Hysteresis − (Sense Threshold High) −

(Sense Threshold Low)
Sense Input Current I
Sense Output Resistance R
Sense Output Low Voltage V
Allowable External Sense Out

R

Pullup Resistor

SI

SO

SO

SOext

VSI < 1.20 V, VI > 4.2 V, ISO = 0 mA

− −1.0 0.1 1.0

− 10 20 40

− 5.6 − −

−

−−0.017

4.0−7.1

0.1

0.1

12

−

−

1.26−1.36−1.44

−

50 90 130 mV

− 0.1 0.4 V

V

mA

ms

V

mA
kW

kW

SI High to SO High Reaction Time t
SI Low to SO Low Reaction Time t

V

I

I

V

INH

(14−Pin Part Only)

INH

100 nF

I

V

RADJ

V

SI

RADJ

I

pdSOLH

pdSOHL

I

I

I

INH

I

D

D

C

D

I

D

Q

RO

NCV4299

RADJ

SI

SI

SO

GND

I

q

Figure 3. Measurement Circuit

− − 4.4 8.0

− − 3.8 5.0

I

Q

V

Q

V

RO

V

SO

ms
ms

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NCV4299

5

5.1

0

TYPICAL PERFORMANCE CHARACTERISTICS − 5.0 V OPTION

6

VI = 13.5 V

= 1 kW

R

L

5

4

5.0

VQ VOLTS

4.9

−40 80

−20 60 1004020 120
TEMPERATURE C

Figure 4. Output Voltage VQ vs. Temperature TJ

8.0
VI = 13.5 V

VD = 1 V
RL = 5 kW

7.0

CHARGE CURRENT, mA

6.0

−40 80

−20 60 1004020 120
TEMPERATURE C

3

2

1

OUTPUT VOLTAGE, VQ VOLTS

1600 140

0

010

5

INPUT VOLTAGE, VI VOLTS

RL = 50 W

1

Figure 5. Output Voltage VQ vs. Input Voltage

500

400

300

200

DROP VOLTAGE, Vdr, mV

100

0

1600 140

0 100

OUTPUT CURRENT IQ, mA

125°C

−40°C

50

25°C

150

Figure 6. Charge Current ld, c vs. Temperature TJ Figure 7. Drop Voltage Vdr vs. Output Current IQ

3.2

2.8

2.4
V

V

LD, VI

UD

= 13.5V

40 120

TEMPERATURE, C

2.0

1.6

1.2

0.8

SWITCHING VOLTAGE, V

0.4

0.0

−40 80

Figure 8. Switching Voltage VUD and VLD vs.

Temperature TJ

1600

1.5

1.4

1.3

1.2

VRADJTH, V

1.1

1.0

0.9

−40 80

0

40 120 16

TEMPERATURE TJ, C

Figure 9. Reset Adjust Switching Threshold

VRADJTH vs. Temperature TJ

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NCV4299

0

0

0

1.6

1.5

1.4

1.3

VSI, V

1.2

1.1

1.0

−40 80

VSIU

VSIL

40 120

TEMPERATURE, C

Figure 10. Sense Threshold VSI vs. Temperature TJ

2.0

1.5

350
300

250

200

150

100

OUTPUT CURRENT IQ, mA

50

1600

0

030

Figure 11. Output Current Limit IQ vs. Input

8.0

6.0

TJ = 25°C

TJ = 125°C

10

INPUT VOLTAGE, VI, V

20 4

Voltage, VI

VQ = 0 V

1.0

0.5

CURRENT CONSUMPTION Iq, mA

0.0
030

20 4010

OUTPUT CURRENT IQ, mA

Figure 12. Current Consumption Iq vs. Output

Current IQ

40

VI = 13.5V
RL = 5 kW

30

20

50 60

4.0

2.0

CURRENT CONSUMPTION Iq, mA

0.0
0 120

40

OUTPUT CURRENT IQ, mA

80 16

Figure 13. Current Consumption Iq vs. Output

Current IQ

16.0

14.0

12.0

10.0

8.0

6.0

4.0

RL 200W RL 100W RL 50W RL 33W

RRO, RSO RESISTANCE, Ohms

10

−40

0 120

TEMPERATURE C

80 16040

2.0

CURRENT CONSUMPTION Iq, mA

0.0
030

10

INPUT VOLTAGE VI, V

20 4

Figure 14. RRO, RSO Resistance vs. Temperature Figure 15. Current Consumption Iq vs. Input

Voltage VI

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NCV4299

90

85

80

75

70

65

CURRENT CONSUMPTION Iq, mA

60

8162014

618

12 22

INPUT VOLTAGE VI, V

IQ 100 mA

2410 26

Figure 16. Current Consumption Iq vs. Input

Voltage VI

45
40

35
30
25
20

Unstable

Region

6

5

4

3

2

1

CURRENT CONSUMPTION Iq, mA

0

8162014

618

IQ 50mA

IQ 10mA

12 22 2410 26

INPUT VOLTAGE VI, V

IQ 100mA

Figure 17. Current Consumption Iq vs. Input

Voltage VI

VI = 13.5V
TA = 25°C

1 mF to 100 mF

0.1 mF

15
10

5

OUTPUT CAPACITOR ESR, Ohms

0

Stable

Region

Unstable Region

0.1 mF Only

80

60 1004020 120

OUTPUT CURRENT, mA

Figure 18. Stability vs. Output Capacitor ESR

1600 140

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NCV4299

TYPICAL PERFORMANCE CHARACTERISTICS − 3.3 V OPTION

1000

VI = 13.5 V

100

IQ = 1 mA

10

1

, CURRENT CONSUMPTION (mA)

Q

I

0.1

TJ, JUNCTION TEMPERATURE (°C) IQ, OUTPUT CURRENT (mA)

Figure 19. Current Consumption vs. Junction

Temperature

5

4

3

2

1

, CURRENT CONSUMPTION (mA)

Q

I

0

VI, INPUT VOLTAGE (V) TJ, JUNCTION TEMPERATURE (°C)

Figure 21. Current Consumption vs. Input

Voltage

100806040200−20−40

140120

TJ = 25°C

RL = 33 W

RL = 50 W

RL = 100 W

200

12

10

8

6

4

2

, CURRENT CONSUMPTION (mA)

Q

I

0

Figure 20. Current Consumption vs. Output

3.5

3.4

3.3

3.2

3.1

, OUTPUT VOLTAGE (V)

Q

V

3.0

50403020100

2.9

Figure 22. Output Voltage vs. Junction

TJ = 150°C

Current

Temperature

TJ = 25°C

TJ = −40°C

140120100806040200

VI = 13.5V
RL = 1 kW

180160

16012080400−40

0

−50
TJ = 125°C

−100

−150
TJ = 25°C

−200

−250

, REVERSE OUTPUT CURRENT (mA)

Q

−300

I

VQ, OUTPUT VOLTAGE (V) VI, INPUT VOLTAGE (V)

TJ = −40°C

Figure 23. Reverse Output Current vs. Output

Voltage

VI = 0 V

50403020100

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10

350
300

250

200

150
100

50

, MAXIMUM OUTPUT CURRENT (mA)

Q

0

I

TJ = 25°C

TJ = 125°C

VQ = 0 V

25

Figure 24. Maximum Output Current vs. Input

Voltage

500

NCV4299

6

5

4

3

2

, OUTPUT VOLTAGE (V)

Q

V

1

0

1000

100

10

TJ = 25°C

RL = 50 W

3210

VI, INPUT VOLTAGE (V) IQ, OUTPUT CURRENT (mA)

Figure 25. Output Voltage at Input Voltage

Extremes

Max ESR for Vin = 6 V

Max ESR for Vin = 25 V

1000

100

10

1

0.1

0.01

CQ = 22 mF
TJ = 150°C

OUTPUT CAPACITOR ESR (W)

54

Max ESR for Vin = 6 V

Max ESR for Vin = 25 V

Stable Region

1301007040100

Figure 26. 3.3 V Output Stability with Output

Capacitor ESR

0.02

0.01

−0.01

0

INH = OFF

TJ = −40°C

TJ = 25°C

TJ = 125°C

1

Stable Region

0.1

0.01

CQ = 22 mF
TJ = −40°C

IQ, OUTPUT CURRENT (mA)

OUTPUT CAPACITOR ESR (W)

Figure 27. 3.3 V Output Stability with Output

Capacitor ESR

6

TJ = −40°C

TJ = 125°C

, INHIBIT INPUT CURRENT (mA)

INH

I

5

4

3

2

1

0

V

, INHIBIT INPUT VOLTAGE (V) TJ, JUNCTION TEMPERATURE (°C)

INH

Figure 29. Inhibit Input Current at Inhibit Input

Voltage Extremes

1301007040100

TJ = 25°C

403020100

−0.02

−0.03

, INHIBIT INPUT CURRENT (mA)

−0.04

INH

I

−0.05

VI, INPUT VOLTAGE (V)

Figure 28. Inhibit Input Current at Input

Voltage Extremes

3.25

3.20

3.15

3.10

3.05

3.00

, RESET TRIGGER THRESHOLD (V)

RT

2.95

V

−20−40 604020 12010080

Figure 30. Reset Trigger Threshold vs.

Junction Temperature

TJ = 150°C

403020100

VI = 13.5 V

Reset

1400

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NCV4299

35

VI = 13.5 V
C

= 100 nF

D

30

25

20

, RESET DELAY TIME (ms)

15

RD

T

10

200−20−40

1008060 120 8060 120 140

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

Figure 31. Reset Delay Time vs. Junction

Temperature

8
7
6
5
4
3

CURRENT (mA)

2

, DELAY CAPACITOR CHARGE

1

CH

I

0

1006020−20

, JUNCTION TEMPERATURE (°C)

T

J

Figure 33. Delay Capacitor Charge Current vs.

Junction Temperature

14040

VI = 13.5 V
VD = 1 V

14012080400−40

1.50

1.45

1.40

1.35

, SENSE THRESHOLD (V)

SI

V

1.30

Figure 32. Sense Threshold vs. Junction

1.15

1.14

1.13

1.12

1.11

1.10

1.09

1.08

, DROP VOLTAGE (V)

DR

1.07

V

1.06

VDR = V

Imin

− V

1.05

IQ, OUTPUT CURRENT (mA)

Figure 34. Drop Voltage vs. Output Current

Temperature

Q

VSI

VSI

VI = 13.5 V

High

Low

10040200−20−40

TJ = 125°C

TJ = −40°C

TJ = 25°C

16012080400

3.0

2.5

2.0

V

UD

1.5

1.0

, SWITCHING VOLTAGE (V)

LD

0.5

, V

UD

V

0

V

LD

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

Figure 35. Switching Voltage VUD and VLD vs.

Junction Temperature

VI = 13.5 V

12080400−40

1.5

1.4

1.3

(V)

1.2

RADJ,th

V

1.1

1.0

0.9

160

−40 8040 120

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12

1600

Figure 36. Reset Adjust Switching Threshold

vs. Junction Temperature

NCV4299

1.5

1.0

0.5
IQ = 10 mA

, CURRENT CONSUMPTION (mA)

Q

I

0

VI, INPUT VOLTAGE (V) TJ, JUNCTION TEMPERATURE (°C)

Figure 37. Current Consumption vs. Input

Voltage

3020100

TJ = 25°C

IQ = 1 mA

40

RESISTANCE (kW)
, R

R

40

35

30

25

SO

20

RO

15

10

Figure 38. RRO, RSO Resistance vs. Junction

Temperature

16012080400−40

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NCV4299

APPLICATION DESCRIPTION

NCV4299

The NCV4299 is a family of precision micropower
voltage regulators with an output current capability of
150 mA at 5.0 V and 3.3 V.

The output voltage is accurate within "2% with a
maximum dropout voltage of 0.5 V at 100 mA. Low
quiescent current is a feature drawing only 90 mA with a
100 mA load. This part is ideal for any and all battery
operated microprocessor equipment.

Microprocessor control logic includes an active reset
output RO (with delay), and a SI/SO monitor which can be
used to provide an early warning signal to the
microprocessor of a potential impending reset signal. The
use of the SI/SO monitor allows the microprocessor to finish
any signal processing before the reset shuts the
microprocessor down. Internal output resistors on the RO
and SO pins pulling up to the output pin Q reduce external
component count. An inhibit function is available on the
14−lead part. With inhibit active, the regulator turns off and
the device consumes less that 1.0 mA of quiescent current.

The active reset circuit operates correctly at an output
voltage as low as 1.0 V. The reset function is activated
during the powerup sequence or during normal operation if
the output voltage drops outside the regulation limits.

The reset threshold voltage can be decreased by the
connection of an external resistor divider to the RADJ lead.
The regulator is protected against reverse battery, short
circuit, and thermal overload conditions. The device can
withstand load dump transients making it suitable for use in
automotive environments.

NCV4299 Circuit Description

The low dropout regulator in the NCV4299 uses a PNP
pass transistor to give the lowest possible dropout voltage
capability. The current is internally monitored to prevent
oversaturation of the device and to limit current during over
current conditions. Additional circuitry is provided to
protect the device during overtemperature operation.

The regulator provides an output regulated to 2%.

Other features of the regulator include an undervoltage
reset function and a sense circuit. The reset function has an
adjustable time delay and an adjustable threshold level. The
sense circuit trip level is adjustable and can be used as an
early warning signal to the controller. An inhibit function
that turns off the regulator and reduces the current
consumption to less than 1.0 mA is a feature available in the
14 pin package.

Output Regulator

The output is controlled by a precision trimmed reference.
The PNP output has saturation control for regulation while
the input voltage is low, preventing oversaturation. Current
limit and voltage monitors complement the regulator design
to give safe operating signals to the processor and control
circuits.

Stability Considerations

The input capacitor CI is necessary for compensating
input line reactance. Possible oscillations caused by input
inductance and input capacitance can be damped by using a
resistor of approximately 1.0 W in series with CI.

The output or compensation capacitor helps determine
three main characteristics of a linear regulator: startup delay ,
load transient response and loop stability.

The capacitor value and type should be based on cost,
availability, size and temperature constraints. A tantalum or
aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR can cause
instability. The aluminum electrolytic capacitor is the least
expensive solution, but, if the circuit operates at low
temperatures (−25°C to −40°C), both the value and ESR of
the capacitor will vary considerably. The capacitor
manufacturer’s data sheet usually provides this information.

The value for the output capacitor CQ shown in Figures 39
and 40 should work for most applications, however, i t is not
necessarily the optimized solution. Stability is guaranteed at
values CQ w 22 mF and an ESR v 5.0 W within the
operating temperature range. Actual limits are shown in a
graph in the typical performance characteristics section.

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NCV4299

V

BAT

CI*

0.1 mF

C

D

I

D

SO

RADJ

NCV4299

GND

RO

Q

R

RADJ1

CQ**

V

DD

22 mF

R

RADJ2

R

S11

SI

R

S12

Microprocessor

I/O

I/O

*CI required if regulator is located far from the power supply filter.

**CQ required for stability. Cap must operate at minimum temperature expected.

Figure 39. Test and Application Circuit Showing all Compensation and Sense

Elements for the 8 Pin Package Part

V

BAT

CI*

0.1 mF

C

D

I

D

RADJ

Q

R

RADJ1

CQ**

V

DD

22 mF

R

RADJ2

R

S11

SI

NCV4299

R

S12

Microprocessor

INHINH
SO

RO

GND

I/O

I/O

*CI required if regulator is located far from the power supply filter.

**CQ required for stability. Cap must operate at minimum temperature expected.

Figure 40. Test and Application Circuit Showing all Compensation and Sense

Elements for the 14 Pin Package Part with Inhibit Function

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NCV4299

Reset Output (RO)

A reset signal, Reset Output (RO, low voltage) is
generated as the IC powers up. After the output voltage V
increases above the reset threshold voltage VRT, the delay
timer D is started. When the voltage on the delay timer V
passes VUD, the reset signal RO goes high. A discharge of
the delay timer (VD) is started when VQ drops and stays
below the reset threshold voltage VRT. When the voltage of

V

I

V

Q

V

RT

V

D

V

UD

V

LD

t

t

V

RO

d

RR

the delay timer (VD) drops below the lower threshold
voltage VLD, the reset output voltage VRO is brought low to
reset the processor.

Q

The reset output RO is an open collector NPN transistor,

controlled by a low voltage detection circuit. The circuit is

D

functionally independent of the rest of the IC, thereby
guaranteeing that RO is valid for VQ as low as 1.0 V.

< t

RR

I

dV

D

+

dt

C

D

t

t

t

VRO,

SAT

Power−on−Reset Thermal

Shutdown

Voltage Dip

at Input

Figure 41. Reset Timing Diagram

Reset Adjust (RADJ)

The reset threshold VRT can be decreased from a typical
value of 4.65 V to as low as 3.5 V by using an external
voltage divider connected from the Q lead to the pin RADJ,
as shown in Figures 39 and 40. The resistor divider keeps the
voltage above the V

RADJ,TH

, (typ. 1.35 V), for the desired
input voltages and overrides the internal threshold detector.
Adjust the voltage divider according to the following
relationship:

V

THRES

+ V

RADJ,TH

·(R

ADJ1

) R

ADJ2

)ńR

ADJ2

(eq. 1)

If the reset adjust option is not needed, the RADJ−pin
should be connected to GND causing the reset threshold to
go to its default value (typ. 4.65 V).

t

Undervoltage Secondary

Spike

Overload
at Output

Reset Delay (D)

The reset delay circuit provides a delay (programmable by
capacitor CD) on the reset output RO lead. The delay lead D
provides charge current ID (typically 8.0 mA) to the external
delay capacitor CD during the following times:

1. During Powerup (once the regulation threshold has
been exceeded).

2. After a reset event has occurred and the device
is back in regulation. The delay capacitor is
set to discharge when the regulation (VRT, reset
threshold voltage) has been violated. When
the delay capacitor discharges to down to VLD,
the reset signal RO pulls low.

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NCV4299

L

Sense

Setting the Delay Time

The delay time is set by the delay capacitor CD and the
charge current ID. The time is measured by the delay
capacitor voltage charging from the low level of V

D,sat

to the

higher level VUD. The time delay follows the equation:

td+ [CD(VUD−V

D,sat

)]ńI

D

(eq. 2)

Example:
Using CD = 100 nF.

Use the typical value for V

D,sat

= 0.1 V.
Use the typical value for VUD = 1.8 V.
Use the typical value for Delay Charge Current ID = 6.5 mA.

td+ [100 nF(1.8−0.1 V)]ń6.5 mA + 26.2 ms

(eq. 3)

When the output voltage VQ drops below the reset
threshold voltage VRT, the voltage on the delay capacitor V
starts to drop. The time it takes to drop below the lower
threshold voltage of VLD is the reset reaction time, tRR. This
time is typically 1.0 ms for a delay capacitor of 0.1 mF. The
reset reaction time can be estimated from the following
relationship:

tRR+ 10 nsńnF C

V

Q

D

(eq. 4)

Sense Input (SI)/Sense Output (SO) Voltage Monitor

An on−chip comparator is available to provide early
warning to the microprocessor of a possible reset signal. The
reset signal typically turns the microprocessor off
instantaneously. This can cause unpredictable results with
the microprocessor. The signal received from the SO pin will
allow the microprocessor time to complete its present task
before shutting down. This function is performed by a
comparator referenced to the band gap voltage. The actual
trip point can be programmed externally using a resistor
divider to the input monitor (SI) (Figures 39 and 40). The
typical threshold is 1.35 V on the SI Pin.

Signal Output

Figure 42 shows the SO Monitor w aveforms a s a r e sul t o f
the circuits depicted in Figures 39 and 40. As the output

D

voltage VQ falls, the monitor threshold V

SI,LOW

This causes the voltage on the SO output to go low sending
a warning s ignal t o t he m icroprocess or t hat a r e set s ignal may
occur in a short period of time. T

WARNING

microprocessor has to complete the function it is currently
working on and get ready for the reset shutdown signal.

Input

Voltage

V

SL, High

is crossed.

is the time the

V

S

I

V

SI,LOW

V

RO

S

O

T

WARNING

Figure 42. SO Warning Timing Waveform Figure 43. Sense Timing Diagram

Calculating Power Dissipation in a Single Output
Linear Regulator

The maximum power dissipation for a single output

regulator is:

P

D(max)

+ [V

I(max)−VQ(min)]IQ(max)

) V

I(max)

Iq

(eq. 5)

where:
V

is the maximum input voltage,

I(max)

V
I

is the minimum output voltage,

Q(min)

is the maximum output current for the application,

Q(max)

SL, Low

Sense

Output

High

Low

t

PD SO LH

Iq is the quiescent current the regulator consumes at I

Once the value of P
permissible value of R

R

The value of R

qJA

D(max)

can be calculated:

qJA

+ (150°C−TA)ńP

qJA

can then be compared with those in the
package section of the data sheet. Those packages with
R

’s less than the calculated value in Equation 6 will keep

qJA

the die temperature below 150°C. In some cases, none of the
packages will be sufficient to dissipate the heat generated by
the IC, and an external heatsink will be required.

and

t

t

PD SO H

t

Q(max)

is known, the maximum

D

(eq. 6)

.

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NCV4299

Heatsinks

A heatsink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.

Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
determine the value of R

R

+ R

qJA

qJA

qJC

:

) R

qCS

) R

qSA

(eq. 7)

where:
R

= the junction−to−case thermal resistance,

qJC

R

= the case−to−heatsink thermal resistance, and

qCS

R

= the heatsink−to−ambient thermal resistance.

qSA

R

appears in the package section of the data sheet. Like

qJC

R

, it too is a function of package type. R

qJA

qCS

and R

qSA

are
functions of the package type, heatsink and the interface
between them. These values appear in heatsink data sheets
of heatsink manufacturers. Thermal, mounting, and
heatsinking are discussed in the ON Semiconductor
application note AN1040/D, available on the
ON Semiconductor website.

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0

R(t) (

C/W)

1000

0

R(t) (

C/W)

0

R(t) (

C/W)

NCV4299

SOIC 8 LEAD

Cu Area = 10 mm2, 1.0 oz

100

25 mm2, 1.0 oz

°

10

1

0.1

0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 100
Time (sec)

Figure 44. Transient Thermal Response Simulation to a Single Pulse 1 oz (Log−Log)

1000

50% Duty Cycle

100

20%
10%

10

5%

°

2%
1%

1

100 mm2, 1.0 oz

250 mm2, 1.0 oz

500 mm2, 1.0 oz

0.1

Single Pulse (SOIC−8)

0.01

0.001

0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 100

Psi LA (SOIC−8)

Pulse Time (sec)

Figure 45. Transient Thermal Response Simulation to a Single Pulse with Duty Cycles Applied (Log−Log)

(PCB = 50 mm

1000

50% Duty Cycle

100

20%

10%

10

5%

°

2%

1

1%

0.1

Single Pulse (SOIC−8)

0.01

0.001

0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 100

Psi LA (SOIC−8)

Pulse Time (sec)

2

1 oz)

Figure 46. Transient Thermal Response Simulation to a Single Pulse with Duty Cycles Applied (Log−Log)

(PCB = 250 mm

2

1 oz)

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0

R(t) (

C/W)

1000

0

R(t) (

C/W)

0

R(t) (

C/W)

NCV4299

SOIC 14 LEAD

Cu Area = 10 mm2, 1.0 oz

100

25 mm2, 1.0 oz

°

10

1

0.1

0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 100
Time (sec)

Figure 47. Transient Thermal Response Simulation to a Single Pulse 1 oz (Log−Log)

1000

50% Duty Cycle

100

20%
10%

10

5%

°

2%

1

1%

100 mm2, 1.0 oz

250 mm2, 1.0 oz

500 mm2, 1.0 oz

0.1

Single Pulse (SOIC−14)

0.01

0.001

0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 100

Psi LA (SOIC−14)

Pulse Time (sec)

Figure 48. Transient Thermal Response Simulation to a Single Pulse with Duty Cycles Applied (Log−Log)

(PCB = 50 mm

100

50% Duty Cycle

20%

10

10%

5%
2%

1

°

1%

0.1

Single Pulse (SOIC−14)

0.01

0.001

0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 100

Psi LA (SOIC−14)

Pulse Time (sec)

2

1 oz)

Figure 49. Transient Thermal Response Simulation to a Single Pulse with Duty Cycles Applied (Log−Log)

(PCB = 250 mm

2

1 oz)

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NCV4299

ORDERING INFORMATION

Device Package Shipping

NCV4299D1 SO−8 98 Units/Rail
NCV4299D1G SO−8

(Pb−Free)
NCV4299D1R2 SO−8 2500 Tape & Reel
NCV4299D1R2G SO−8

(Pb−Free)
NCV4299D2 SO−14 55 Units/Rail
NCV4299D2G SO−14

(Pb−Free)
NCV4299D2R2 SO−14 2500 Tape & Reel
NCV4299D2R2G SO−14

(Pb−Free)
NCV4299D233G SO−14

(Pb−Free)
NCV4299D233R2G SO−14

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

98 Units/Rail

2500 Tape & Reel

55 Units/Rail

2500 Tape & Reel

55 Units/Rail

2500 Tape & Reel

†

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−Y−

−Z−

NCV4299

PACKAGE DIMENSIONS

SOIC−8 NB

CASE 751−07

ISSUE AH

NOTES:

−X−
A

58

B

1

S

0.25 (0.010)

4

M

M

Y

K

G

C

SEATING
PLANE

0.10 (0.004)

H

D

0.25 (0.010) Z

M

Y

SXS

N

X 45

_

M

J

1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.

MILLIMETERS

DIMAMIN MAX MIN MAX

4.80 5.00 0.189 0.197

B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050

M 0 8 0 8

____

N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244

INCHES

SOLDERING FOOTPRINT*

1.52

0.060

7.0

0.275

0.6

0.024

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

4.0

0.155

1.270

0.050

SCALE 6:1

ǒ

inches

mm

Ǔ

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−T−

SEATING
PLANE

−A−

14 8

G

D 14 PL

0.25 (0.010) A

NCV4299

PACKAGE DIMENSIONS

SO−14

D SUFFIX

CASE 751A−03

ISSUE G

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

−B−

P 7 PL

M

71

0.25 (0.010) B

C

R X 45

K

M

S

B

T

S

M

_

M

F

J

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

DIM MIN MAX MIN MAX

A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC

J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7

____

P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019

INCHESMILLIMETERS

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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For additional information, please contact your
local Sales Representative.

NCV4299/D

23