ON Semiconductor NCP3163, NCV3163 Technical data

NCP3163, NCV3163

8

3.4 A, Step−Up/Down/
Inverting 50−300 kHz
Switching Regulator

The NCP3163 Series is a performance enhancement to the popular
MC33163 and MC34163 monolithic DC−DC converters. These
devices consist of an internal temperature compensated reference,
comparator, controlled duty cycle oscillator with an active current
limit circuit, driver and high current output switch. This controller was
specifically designed to be incorporated in step−down, step−up, or
voltage−inverting applications with a minimum number of external
components. The NCP3163 comes in an exposed pad package which
can greatly increase the power dissipation of the built in power switch.

Features

• Output Switch Current in Excess of 3.0 A

• 3.4 A Peak Switch Current

• Frequency is Adjustable from 50 kHz to 300 kHz

• Operation from 2.5 V to 40 V Input

• Externally Adjustable Operating Frequency

• Precision 2% Reference for Accurate Output Voltage Control

• Driver with Bootstrap Capability for Increased Efficiency

• Cycle−by−Cycle Current Limiting

• Internal Thermal Shutdown Protection

• Low Voltage Indicator Output for Direct Microprocessor Interface

• Exposed Pad Power Package

• Low Standby Current

• NCV Prefix for Automotive and Other Applications Requiring Site

and Control Changes

• These are Pb−Free Devices

Current

8

V

in

7

+

V

C

in

CC

6

Oscillator

Limit

−

+

9

10

11

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MARKING

DIAGRAMS

16

1

SOIC−16W

EXPOSED PAD

PW SUFFIX

CASE 751AG

18

1

NCx3163x = Specific Device Code

A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G or G = Pb−Free Package

(Note: Microdot may be in either location)

18−LEAD DFN

MN SUFFIX

CASE 505

16

NCx3163yPW

AWLYYWWG

1

11

NCP3163y

AWLYYWW G

G

x = P or V
y = blank or B

ORDERING INFORMATION

See detailed ordering and shipping information in the package
dimensions section on page 18 of this data sheet.

5

Thermal

4

3

2

LVI

+
+

−

1

+
+

−

R

S

V

CC

(Bottom View)

Figure 1. Typical Buck Application Circuit

© Semiconductor Components Industries, LLC, 2007

January, 2007 − Rev. 4

Q

V

CC

12

13

14

15

16

V

out

+

C

O

1 Publication Order Number:

*For additional information on our Pb−Free strategy

and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.

NCP3163/D

NCP3163, NCV3163

Thermal

+
+

−

Current

Limit

−

+

45 k

+
+

−

1.25 V

1.125 V

(Bottom View)

R

Q

S

Latch

V

CC

2.0 mA

Feedback

Comparator

15 k

9

Driver Collector

10

Switch Collector

11

Q1

Q2

12

60

13

14

Switch Emitter

15

7.0 V

V

CC

16

Bootstrap Input

+

= Sink Only

−

Positive True Logic

Shutdown

I

PKsense

R

SC

V

CC

Timing Capacitor

C

T

R

DT

Gnd

Voltage Feedback 1

Voltage Feedback 2

LVI Output

0.25 V

8

7

V

CC

6

Oscillator

5

4

3

2

1

LVI

Figure 2. Representative Block Diagram

PIN FUNCTION DESCRIPTION

SOIC16 DFN18 PIN NAME DESCRIPTION

1 15 LVI Output This pin will sink current when FB1 and FB2 are less than the LVI threshold (Vth).
2 16 Voltage Feedback 2 Connecting this pin to a resistor divider off of the output will regulate the application

3 17 Voltage Feedback 1 Connecting this pin directly to the output will regulate the device to 5.05 V.
4 18 GND Ground pin for all internal circuits and power switch.
6 1 Timing Capacitor Connect a capacitor to this pin to set the frequency. The addition of a parallel resis-

7 3 V

CC

8 4 Ipk Sense When (VCC−V

9 5 Drive Collector Voltage driver collector
10,11 6,7,8,9 Switch Collector Internal switch transistor collector
14,15 10,11,12,13 Switch Emitter Internal switch transistor emitter

16 14 Bootstrap Input Connect this pin to VCC for operation at low VCC levels. For some topologies, a

5,12,13 2 No Connect These pins have no connection.

Exposed

Pad

Exposed

Pad

Exposed Pad The exposed pad beneath the package must be connected to GND (pin 4). Addi-

according to the V

design equation in Figure 22.

out

tor will decrease the maximum duty cycle and increase the frequency.
Power pin for the IC.

) > 250 mV the circuit resets the output driver on a pulse by

pulse basis.

IPKsense

series resistor and capacitor can be utilized to improve the converter efficiency.

tionally, using proper layout techniques, the exposed pad can greatly enhance the
power dissipation capabilities of the NCP3163.

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2

NCP3163, NCV3163

MAXIMUM RATINGS (Note 1)

Rating

Power Supply Voltage V
Switch Collector Voltage Range V
Switch Emitter Voltage Range V
Switch Collector to Emitter Voltage V
Switch Current I
Driver Collector Voltage (Pin 8) V
Driver Collector Current (Pin 8) I
Bootstrap Input Current Range I
Current Sense Input Voltage Range V
Feedback and Timing Capacitor Input Voltage Range V
Low Voltage Indicator Output Voltage Range V
Low Voltage Indicator Output Sink Current I

Power Dissipation and Thermal Characteristics

Thermal Characteristics

Thermal Resistance, Junction−to−Case

Thermal Resistance, Junction−to−Air
Storage Temperature Range T
Maximum Junction Temperature T
Operating Ambient Temperature (Note 3)

NCP3163PW

NCP3163BPW

NCV3163PW

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.

1. This device series contains ESD protection and exceeds the following tests:
Human Body Model 1500 V per MIL−STD−883, Method 3015.
Machine Model Method 150 V.

2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.

3. Maximum package power dissipation limits must be observed. Maximum Junction Temperature must not be exceeded.

4. The pins which are not defined may not be loaded by external signals.

Symbol Value Unit

CC
CSW
ESW

CESW

SW

CC

CC

BST

IPKSNS

in

CLVI

CLVI

(VCC − 7.0) to (VCC + 1.0) V

0 to +40 V

−1.0 to +40 V

−2.0 to +40 V
+40 V

3.4 A

−1.0 to +40 V
150 mA

−100 to +100 mA

−1.0 to +7.0 V

−1.0 to +40 V

10 mA

°C/W

R

R

Jmax

q

JC

q

JA

stg

T

A

15
56

−65 to +150 °C
+150 °C

°C

0 to +70

−40 to +85

−40 to +125

LVI Output

Voltage Feedback 2

Voltage Feedback 1

GND

N/C

Timing Capacitor

V

Ipk Sense

PIN CONNECTIONS

116

2

3

4

5

6

7

CC

8

(Top View)

Bootstrap Input

15

14

13

12

11

10

9

Driver Collector

Switch
Emitter

N/C

Switch Collector

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Timing Capacitor

Driver Collector
Switch Collector
Switch Collector
Switch Collector
Switch Collector

3

1

N/C

V

Ipk Sense

2
3

CC

4

GND

5
6
7

EP Flag

8
9

Note: Pin 18 must be tied to EP Flag on PCB

18

17
16
15
14
13
12
11
10

GND
Voltage Feedback 1
Voltage Feedback 2

LVI Output
Bootstrap Input
Switch Emitter
Switch Emitter
Switch Emitter
Switch Emitter

NCP3163, NCV3163

ELECTRICAL CHARACTERISTICS (V

values T

is the operating ambient temperature range that applies (Note 7), unless otherwise noted.)

A

Characteristic

= 15 V, Pin 16 = VCC, CT = 270 pF, RT = 15 kW, for typical values TA = 25°C, for min/max

CC

Symbol Min Typ Max Unit

OSCILLATOR

Frequency

T

= 25°C, VCC = 15 V

A

Total Variation over V

= 2.5 V to 40 V and Temperature

CC

Charge Current I
Discharge Current I
Charge to Discharge Current Ratio I
Sawtooth Peak Voltage V
Sawtooth Valley Voltage V

f

OSC

chg

dischg

chg/Idischg

OSC(P)
OSC(V)

225
212

250
250

− 225 −

− 25 −

8.0 9.0 10.5 −

− 1.25 − V

− 0.55 − V

FEEDBACK COMPARATOR 1

Threshold Voltage

TA = 25°C
Total Variation over VCC = 2.5 V to 40 V and Temperature

Threshold Voltage

Line Regulation (VCC = 2.5 V to 40 V, TA = 25°C)

Input Bias Current (V

= 5.05 V) I

FB1

V

th(FB1)

REGline

IB(FB1)

(FB1)

4.9

4.85

5.05

−

− 0.008 0.03

− 100 200

5.25

FEEDBACK COMPARATOR 2

Threshold Voltage

TA = 25°C, VCC = 15 V
Total Variation over VCC = 2.5 V to 40 V and Temperature

Threshold Voltage

Line Regulation (VCC = 2.5 V to 40 V, TA = 25°C)

Input Bias Current (V

= 1.25 V) I

FB2

V

th(FB2)

REGline

IB(FB2)

(FB1)

1.225

1.213

1.25

−

1.275

1.287

− 0.008 0.03

− 0.4 − 0.4

CURRENT LIMIT COMPARATOR

Threshold Voltage

TA = 25°C
Total Variation over VCC = 2.5 V to 40 V, and Temperature

Input Bias Current (V

Ipk (Sense)

= 15 V) I

V

th(Sense)

IB(Sense)

−

225

250

−

− 1.0 20

DRIVER AND OUTPUT SWITCH (Note 6)

Saturation Voltage (ISW = 2.5 A, Pins 14, 15 grounded)

NCP3163 − Non−Darlington (R
NCV3163 − Non−Darlington (R

= 110 W to VCC, ISW/I

Pin 9

= 110 W to VCC, ISW/I

Pin 9

DRV
DRV

≈ 20)
≈ 20)

Darlington Connection (Pins 9, 10, 11 connected)
Collector Off−State Leakage Current (VCE = 40 V) I
Bootstrap Input Current Source (VBS = VCC + 5.0 V) I
Bootstrap Input Zener Clamp Voltage (IZ = 25 mA) V

V

CE(sat)

C(off)

source(DRV)

Z

−

−

−

0.6

0.6

1.0

− 0.02 100

0.5 2.0 4.0 mA

VCC + 6.0 VCC + 7.0 VCC + 9.0 V

LOW VOLTAGE INDICATOR

Input Threshold (V
Input Hysteresis (V
Output Sink Saturation Voltage (I
Output Off−State Leakage Current (VOH = 15 V) I

Increasing) V

FB2

Decreasing) V

FB2

= 2.0 mA) V

sink

th
H

OL(LVI)

OH

1.07 1.125 1.18 V

− 15 − mV

− 0.15 0.4 V

− 0.01 5.0

TOTAL DEVICE

Standby Supply Current (VCC = 2.5 V to 40 V, Pin 8 = VCC,

I

CC

− 6.0 10 mA

Pins 6, 14, 15 = GND, remaining pins open)

5. Maximum package power dissipation limits must be observed.

6. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.

7. T

=0°C for NCP3163 T

low

=−40°C for NCP3163B = + 85°C for NCP3163B

=+70°C for NCP3163

high

=−40°C for NCV3163 = + 125°C for NCV3163

275

kHz

288

mA
mA

V

5.2

%/V

mA

V

%/V

mA

mV

−

270

mA

V

1.0

1.2

1.4

mA

mA

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4

NCP3163, NCV3163

2.0

−2.0

300

250

200

150

FREQUENCY (kHz)

100

Rt = open

50

0

100 200 300 400 500 600 700

CT, TIMER CAPACITANCE (pF)

VCC = 15 V
TA = 25°C

Rt = 15 kW

Figure 3. Oscillator Frequency vs. Timer

Capacitance (C

VCC = 15 V
CT = 620 pF

0

4.0

2.0

−2.0

−4.0

)

T

VCC = 15 V
CT = 230 pF
RT = 20 kW

0

−4.0

, OSCILLATOR FREQUENCY CHANGE (%)Δ

−6.0

OSC

f

−55

−25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C)

Figure 4. Oscillator Frequency Change vs.

Temperature when only C

140

120

100

80

, INPUT BIAS CURRENT (A)μ

IB

I

60

−55

−25 0 25 50 75 100 125

TA, AMBIENT TEMPERATURE (°C)

Figure 6. Feedback Comparator 1 Input Bias

Current vs. Temperature

is connected to Pin 6

T

VCC = 15 V
V

= 5.05 V Vth Max = 1275 mV

FB1

−6.0

−8.0

, OSCILLATOR FREQUENCY CHANGE (%)Δ

−10

OSC

f

−50

−25 0 25 50 75 100 125
TEMPERATURE (°C)

Figure 5. Oscillator Frequency Change vs.

Temperature when C

1300

VCC = 15 V

1280

1260

1240

1220

1200

, COMPARATOR 2 THRESHOLD VOLTAGE (mV)

th(FB2)

V

−55

−25 0 25 50 75 100 125

Figure 7. Feedback Comparator 2 Threshold

and RT are connected to Pin 6

T

Vth Typ = 1250 mV

Vth Min = 1225 mV

TA, AMBIENT TEMPERATURE (°C)

Voltage vs. Temperature

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5

NCP3163, NCV3163

A

5

V

2.8

VCC = 15 V

2.4

2.0

1.6

, BOOTSTRAP INPUT CURRENT SOURCE (m

1.2

−55 −25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C)

source (DRV)

I

−0.4

−0.8

−1.2

, SOURCE SATURATION (V)

−1.6

CE (sat)

V

−2.0

0

Figure 8. Bootstrap Input Current

Source vs. Temperature

V

CC

Bootstrapped, Pin 16 = VCC + 5.0 V

Non−Bootstrapped, Pin 16 = V

0 0.8 2.4 3.2

IE, EMITTER CURRENT (A)

Pin 16 = VCC + 5.0 V

Darlington Configuration
Emitter Sourcing Current to GND
Pins 7, 8, 10, 11 = V
Pins 4, 5, 12, 13 = GND
TA = 25°C, (Note 2)

CC

1.6

CC

Figure 10. Output Switch Source Saturation

vs. Emitter Current

7.6

IZ = 25 mA

7.4

7.2

7.0

6.8

−55 −25 0 25 50 75 100 12

, BOOTSTRAP INPUT ZENER CLAMP VOLTAGE (

Z

V

TA, AMBIENT TEMPERATURE (°C)

Figure 9. Bootstrap Input Zener Clamp

Voltage vs. Temperature

1.2

Darlington, Pins 9, 10, 11 Connected

1.0

0.8

Grounded Emitter Configuration
Collector Sinking Current From V

0.6
Pins 7, 8 = VCC = 15 V

, SINK SATURATION (V)

CE (sat)

V

Pins 4, 5, 12, 13, 14, 15 = GND

0.4
TA = 25°C, (Note 2)

0.2

0

0 0.8 2.4 3.21.6

CC

Saturated Switch, R

GND

IC, COLLECTOR CURRENT (A)

= 110 W to V

Pin9

Figure 11. Output Switch Sink Saturation

vs. Collector Current

CC

0

GND

−0.4

−0.8

−1.2

, EMITTER VOLTAGE (V)

E

V

−1.6

−2.0

−55 −25 0 25 50 75 100 125

IC = 10 mA

IC = 10 mA

VCC = 15 V
Pins 7, 8, 9, 10, 16 = V
Pins 4, 6 = GND
Pin 14 Driven Negative

TA, AMBIENT TEMPERATURE (°C)

Figure 12. Output Switch Negative Emitter

Voltage vs. Temperature

0.5

0.4

0.3

0.2

CC

, OUTPUT SATURATION VOLTAGE (V)

V

OL (LVI)

0.1

0

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6

VCC=5 V
TA=25°C

0 2.0 4.0 6.0 8.0

I

, OUTPUT SINK CURRENT (mA)

sink

Figure 13. Low Voltage Indicator Output Sink

Saturation Voltage vs. Sink Current

NCP3163, NCV3163

254

VCC = 15 V

252

250

, THRESHOLD VOLTAGE (mV

248

th (Ipk Sense)

V

246

−55 −25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C)

Figure 14. Current Limit Comparator Threshold

Voltage vs. Temperature

8.0

6.0

4.0

1.6

μ

1.4

1.2

1.0

INPUT BIAS CURRENT ( A)
,

0.8

IB (Sense)

I

0.6

−55 −25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C)

VCC = 15 V
V

Ipk (Sense)

= 15 V

Figure 15. Current Limit Comparator Input Bias

Current vs. Temperature

7.2
VCC = 15 V

Pins 7, 8, 16 = V

6.4

5.6

Pins 4, 6, 14 = GND
Remaining Pins Open

CC

, SUPPLY CURRENT (mA)

2.0

CC

I

0

0 10203040

VCC, SUPPLY VOLTAGE (V)

Pins 7, 8, 16 = V
Pins 4, 6, 14 = GND
Remaining Pins Open
TA = 25°C

CC

Figure 16. Standby Supply Current

vs. Supply Voltage

3.0

2.6

2.2

1.8

1.4

, MINIMUM OPERATING SUPPLY VOLTAGE (V)

1.0

CC(min)

V

Pin 16 Open

Pin 16 = V

−55 −25 0 25 50 75 100 125

CC

TA, AMBIENT TEMPERATURE (°C)

Figure 18. Minimum Operating Supply

Voltage vs. Temperature

, SUPPLY CURRENT (mA)

4.8

CC

I

4.0

−55 −25 0 25 50 75 100 125

CT = 620 pF
Pins 7,8 = V
Pins 4, 14 = GND
Pin 9 = 1.0 kW to 15 V
Pin 10 = 100 W to 15 V

CC

TA, AMBIENT TEMPERATURE (°C)

Figure 17. Standby Supply Current

vs. Temperature

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7

NCP3163, NCV3163

INTRODUCTION

The NCP3163 is a monolithic power switching regulator
optimized for DC−to−DC converter applications. The
combination of its features enables the system designer to
directly implement step−up, step−down, and voltage−
inverting converters with a minimum number of external
components. Potential applications include cost sensitive
consumer products as well as equipment for the automotive,
computer, and industrial markets. A representative block
diagram is shown in Figure 2.

OPERATING DESCRIPTION

The NCP3163 operates as a fixed on−time, variable
off−time voltage mode ripple regulator. In general, this
mode of operation is somewhat analogous to a capacitor
charge pump and does not require dominant pole loop
compensation for converter stability. The Typical Operating
Waveforms are shown in Figure 19. The output voltage
waveform shown is for a step−down converter with the
ripple and phasing exaggerated for clarity. During initial
converter startup, the feedback comparator senses that the
output voltage level is below nominal. This causes the
output switch to turn on and off at a frequency and duty cycle
controlled by the oscillator, thus pumping up the output filter
capacitor. When the output voltage level reaches nominal,
the feedback comparator sets the latch, immediately
terminating switch conduction. The feedback comparator
will inhibit the switch until the load current causes the output
voltage to fall below nominal. Under these conditions,
output switch conduction can be inhibited for a partial

oscillator cycle, a partial cycle plus a complete cycle,
multiple cycles, or a partial cycle plus multiple cycles.

Oscillator

The oscillator frequency and on−time of the output switch
are programmed by the value selected for timing capacitor
CT. Capacitor CT is charged and discharged by a 9 to 1 ratio
internal current source and sink, generating a negative going
sawtooth waveform at Pin 6. As CT charges, an internal
pulse is generated at the oscillator output. This pulse is
connected to the NOR gate center input, preventing output
switch conduction, and to the AND gate upper input,
allowing the latch to be reset if the comparator output is low .
Thus, the output switch is always disabled during ramp−up
and can be enabled by the comparator output only at the start
of ramp−down. The oscillator peak and valley thresholds are

1.25 V and 0.55 V, respectively, with a charge current of
225 mA and a discharge current of 25 mA, yielding a
maximum on−time duty cycle of 90%. A reduction of the
maximum duty cycle may be required for specific converter
configurations. This can be accomplished with the addition
of an external deadtime resistor (RDT) placed across CT. The
resistor increases the discharge current which reduces the
on−time of the output switch. The converter output can be
inhibited by clamping CT to ground with an external NPN
small−signal transistor. To calculate the frequency when
only CT is connected to Pin 6, use the equations found in
Figure 22. When RT is also used, the frequency and
maximum duty cycle can be calculated with the NCP3163
design tool found at www.onsemi.com.

Comparator Output

1.25 V

Timing Capacitor C

0.55 V

Oscillator Output

Output Switch

Nominal Output

Voltage Level

Output Voltage

1

0

T

t

1

0

On

Off

Figure 19. Typical Operating Waveforms

9t

Startup Quiescent Operation

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8

NCP3163, NCV3163

Feedback and Low Voltage Indicator Comparators

Output voltage control is established by the Feedback
comparator. The inverting i nput i s i nternally b iased a t 1 .25 V
and is not pinned out. The converter output voltage is
typically divided down with two external resistors and
monitored b y t he h igh i mpedance n oninverting i nput a t Pin 2.
The maximum i nput b ias c urrent i s ±0.4 mA, w hich c an c ause
an output voltage error t hat i s e qual to the p roduct o f t he i nput
bias current and the upper divider resistance value. For
applications that require 5.0 V, the converter output can be
directly c onnected t o t he n oninverti ng i nput a t P in 3 . T he h igh
impedance input, Pin 2, must be grounded to prevent noise
pickup. The internal resistor divider is set for a nominal
voltage of 5.05 V. The additional 50 mV compensates for a

1.0% voltage drop in the cable and connector from the
converter output to the load. The Feedback comparator’s

3

+
+

−

1.25 V

+
+

−

1.125 V

Low Voltage

Indicator Output

2

R

LVI

1

C

DLY

LVI

output state is controlled by the highest voltage applied to
either of the two noninverting inputs.

The Low V oltage Indicator (LVI) comparator is designed
for use as a reset controller in microprocessor−based
systems. The inverting input is internally biased at 1.125 V,
which sets the noninverting input thresholds to 90% of
nominal. The LVI comparator has 15 mV of hysteresis to
prevent erratic reset operation. The Open Collector output is
capable of sinking in excess of 6.0 mA (see Figure 13). An
external resistor (R
program a reset delay time (t
below, where V

) and capacitor (C

LVI

DLY

is the microprocessor reset input

th(MPU)

DLY

) by the formula shown

) can be used to

threshold. Refer to Figure 20.

1

V

1 −

V

out

th(MPU)

V

out

Feedback
Comparator

(Bottom View)

t

DLY

= R

LVI

14

15

16

⋅ C

DLY

L

⋅ In

C

O

Ǔǒ

Figure 20. Partial Application Schematic Showing

Implementation of LVI Delay with R

Current Limit Comparator, Latch and Thermal
Shutdown

With a voltage mode ripple converter operating under
normal conditions, output switch conduction is initiated by
the oscillator and terminated by the Voltage Feedback
comparator. Abnormal operating conditions occur when the
converter output is overloaded or when feedback voltage
sensing is lost. Under these conditions, the Current Limit
comparator will protect the Output Switch.

The switch current is converted to a voltage by inserting
a fractional ohm resistor, RSC, in series with VCC and output
switch transistor Q2. The voltage drop across RSC is
monitored by the Current Sense comparator. If the voltage
drop exceeds 250 mV with respect to VCC, the comparator
will set the latch and terminate output switch conduction on
a cycle−by−cycle basis. This Comparator/Latch
configuration ensures that the Output Switch has only a
single on−time during a given oscillator cycle. The
calculation for a value of RSC is:

R

SC

0.25 V

+

Ipk(Switch)

Figures 14 and 15 show that the Current Sense comparator
threshold is tightly controlled over temperature and has a
typical input bias current of 1.0 mA. The propagation delay
from the comparator input to the Output Switch is typically

and C

LVI

DLY

200 ns. The parasitic inductance associated with RSC and the
circuit layout should be minimized. This will prevent
unwanted voltage spikes that may falsely trip the Current
Limit comparator.

Internal thermal shutdown circuitry is provided to protect
the IC in the event that the maximum junction temperature
is exceeded. When activated, typically at 170°C, the Latch
is forced into the “Set” state, disabling the Output Switch.
This feature is provided to prevent catastrophic failures from
accidental device overheating. It is not intended to be used
as a replacement for proper heatsinking.

Driver and Output Switch

To aid in system design flexibility and conversion
efficiency, the driver current source and collector, and
output switch collector and emitter are pinned out
separately. This allows the designer the option of driving the
output switch into saturation with a selected force gain or
driving it near saturation when connected as a Darlington.
The output switch has a typical current gain of 70 at 2.5 A
and is designed to switch a maximum of 40 V collector to
emitter, with up to 3.4 A peak collector current. The
minimum value for RSC is:

R

SC(min)

+

0.25 V

3.4 A

+ 0.0735 W

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9

NCP3163, NCV3163

When configured for step−down or voltage−inverting
applications (see application notes at the end of this
document) the inductor will forward bias the output rectifier
when the switch turns off. Rectifiers with a high forward
voltage drop or long turn−on delay time should not be used.
If the emitter is allowed to go sufficiently negative, collector
current will flow, causing additional device heating and
reduced conversion efficiency.

Figure 12 shows that by clamping the emitter to 0.5 V , the
collector current will be in the range 10 mA over
temperature. A 1N5822 or equivalent Schottky barrier
rectifier is recommended to fulfill these requirements.

A bootstrap input is provided to reduce the output switch
saturation voltage in step−down and voltage−inverting
converter applications. This input is connected through a
series resistor and capacitor to the switch emitter and is used
to raise the internal 2.0 mA bias current source above VCC.
An internal zener limits the bootstrap input voltage to V

CC

+7.0 V. The capacitor’s equivalent series resistance must
limit the zener current to less than 100 mA. An additional
series resistor may be required when using tantalum or other

Vias to 2nd Layer Metal
for Maximum Heat Sinking

low ESR capacitors. The equation below is used to calculate
a minimum value bootstrap capacitor based on a minimum
zener voltage and an upper limit current source.

C

B(min)

+ I

Dt

+ 4.0 mA

DV

t

on

4.0 V

+ 0.001 t

on

Parametric operation of the NCP3163 is guaranteed over
a supply voltage range of 2.5 V to 40 V. When operating
below 3.0 V, the Bootstrap Input should be connected to
VCC. Figure 18 shows that functional operation down to

1.7 V at room temperature is possible.

Package

The NCP3163 is contained in a heatsinkable 16−lead
plastic package in which the die is mounted on a special heat
tab copper alloy pad. This pad is designed to be soldered
directly to a GND connection on the printed circuit board to
improve thermal conduction. Since this pad directly
contacts the substrate of the die, it is important that this pad
be always soldered to GND, even if surface mount heat
sinking is not being used. Figure 21 shows recommended
layout techniques for this package.

Exposed Pad

0.175

0.188

0.145

Flare Metal for Maximum Heat Sinking

Figure 21. Layout Guidelines to Obtain Maximum

Package Power Dissipation

Minimum
Recommended
Exposed Copper

APPLICATIONS

Figures 23 through 30 show the simplicity and flexibility
of the NCP3163. Three main converter topologies are
demonstrated with actual test data shown below each of the
circuit diagrams. Figure 22 gives the relevant design

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equations for the key parameters. Additionally, a complete
application design aid for the NCP3163 can be found at
www.onsemi.com.

10

NCP3163, NCV3163

The following Converter Characteristics must be chosen:

Calculation Step−Down Step−Up Voltage−Inverting

(See Notes 1,2,3)

t

on

t

off

V

out

Vin* V

) V

sat

F

* V

out

V

out

) VF–V

Vin–V

in

sat

|V

| ) V

out

Vin* V

F

sat

t

on

C

T

I

L(avg)

I

pk (Switch)

R

SC

L

V

ripple(pp)

V

out

32.143 · 10

f

Vin* V

ǒ

DI

L

t

ǒ

ƒ

t

*6

I

L(avg)

I

pk (Switch)

1

ǒ

ƒ

8C

V

ref

t

on

t

off

on

) 1

off

* 20@ 10

I

out

)

0.25

* V

sat

DI

L

2

Ǔ

) (ESR)

O

R

2

ǒ

) 1

R

1

DI

Ǔ

2

*12

L

out

Ǔ

Ǔt

on

2

32.143 · 10

f

ǒ

ƒ

*6

I

out

I

L(avg)

I

pk (Switch)

Vin* V

ǒ

[

V

ref

t

on

t

off

t

on

) 1

t

off

* 20@ 10

t

on

ǒ

) 1

t

off

)

0.25

sat

DI

L

tonI

out

C

O

R

2

ǒ

) 1

R

1

DI

Ǔ

2

Ǔt

*12

Ǔ

L

on

Ǔ

32.143 · 10

f

ǒ

ƒ

*6

I

out

I

L(avg)

I

pk (Switch)

Vin* V

ǒ

[

V

ref

t

on

t

off

t

on

) 1

t

off

* 20@ 10

t

on

ǒ

) 1

t

off

)

0.25

sat

DI

L

tonI

out

C

O

R

2

ǒ

) 1

R

1

DI

Ǔt

Ǔ

*12

Ǔ

L

2

on

Ǔ

Vin −

Nominal operating input voltage.

V

−

Desired output voltage.

out

I

−

Desired output current.

out

DI

−

Desired peak−to−peak inductor ripple current. For maximum output current it is suggested that DIL be chosen to be less

L

than 10% of the average inductor current I
threshold set by RSC. If the design goal is to use a minimum inductance value, let DIL = 2(I
proportionally reduce converter output current capability.

p −

V

ripple(pp)

NOTES: 1. V

NOTES: 2. VF − Output rectifier forward voltage drop. Typical value for 1N5822 Schottky barrier rectifier is 0.5 V.
NOTES: 3. The calculated ton/t
NOTES: 3. operating input voltage.

Maximum output switch frequency.

−

Desired peak−to−peak output ripple voltage. For best performance the ripple voltage should be kept to a low value
since it will directly affect line and load regulation. Capacitor CO should be a low equivalent series resistance (ESR)
electrolytic designed for switching regulator applications.

− Saturation voltage of the output switch, refer to Figures 10 and 11.

sat

must not exceed the minimum guaranteed oscillator charge to discharge ratio of 8, at the minimum

off

. This will help prevent I

L(avg)

Figure 22. Design Equations

pk (Switch)

from reaching the current limit

L(avg)

). This will

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11

NCP3163, NCV3163

0.25 V

8

R

SC

V

in

R

T

7

C

in

C

T

6

V

CC

Oscillator

5

Thermal

4

3

R

1

R

2

+
+

1

2

LVI

−

Figure 23. Typical Buck Application Schematic

Value of Components

Name Value

L
D 2 A, 40 V Schottky Rectifier
C

in

C

out

C

t

R

t

47 mH

47 mF, 35 V

100 mF, 10 V

270 pF ±10%

15 kW

−
+

45 k

1.125 V

Current

+
+

−

Limit

Latch

V

CC

Feedback
Comparator

15 k1.25 V

(Bottom View)

9

10

11

Q

1

Q

R

Q

S

2

12

60

13

14

15

D

2.0 mA
16

7.0 V

V

CC

R

C

B

B

L

V

C

O

out

Name Value

R

1

R

2

R

sc

C

b

R

b

15 kW

24.9 kW

80 mW, 1 W

4.7 nF
200 W

Test Results for V

= 3.3 V

out

Test Condition Results

Line Regulation Vin = 8.0 V to 24 V, I
Load Regulation Vin = 12 V, I
Output Ripple Vin = 12 V, I
Efficiency V
Short Circuit Current

Test Results for V

= 5.05 V

out

= 12 V, I

in

V

= 12 V, RL = 0.1 W

in

= 0 to 2.5 A 25 mV

out

= 0 to 2.5 A 100 mVpp

out

= 2.5 A 70.3%

out

Test Condition Results

Line Regulation Vin = 10.2 V to 24 V, I
Load Regulation Vin = 12 V, I
Output Ripple Vin = 12 V, I
Efficiency V
Short Circuit Current

= 12 V, I

in

V

= 12 V, RL = 0.1 W

in

= 0 to 2.5 A 28 mV

out

= 0 to 2.5 A 150 mVpp

out

= 2.5 A 75.5%

out

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12

= 2.5 A 13 mV

out

= 2.5 A 54 mV

out

3.1 A

3.1 A

NCP3163, NCV3163

Figure 24. Buck Layout

APPLICATION SPECIFIC CHARACTERISTICS

85

80

75

70

65

EFFICIENCY (%)

60

55
50

I

out

Figure 25. Efficiency vs. Output Current for the

Buck Demo Board at V

5.0 V Eff

3.3 V Eff

(A)

= 12 V, TA = 255C

in

2.52.01.51.00.50

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13

NCP3163, NCV3163

−
+

Thermal

Current

Limit

Q

1

R

Q

S

Q

60

Latch

V

CC

0.25 V

8

R

SC

V

in

R

T

7

+

C

in

C

T

6

V

CC

Oscillator

5

4

3

L

9

10

11

2

12

13

D

14

45 k

+

2

+
+

1

−

LVI

R

2

R

1

+

−

1.25 V

1.125 V

(Bottom View)

Feedback
Comparator

15 k

15

2.0 mA

7.0 V

V

CC

16

V

+

C

O

out

Figure 26. Typical Boost Application Schematic

Value of Components for V

out

= 24 V

Name Value

L

33 mH
D 2 A, 40 V Schottky Rectifier
C

in

C

t

R

t

Test Results for V

330 mF, 35 V

270 pF ±10%

15 kW

= 24 V

out

Test Condition Results

Line Regulation Vin = 10 V to 20 V, I
Load Regulation Vin = 12 V, I
Output Ripple Vin = 12 V, I
Efficiency V
Short Circuit Current

out
out

= 12 V, I

in

V

in

out

= 12 V, RL = 0.1 W

Name Value

R

1

R

2

C

out

R

sc

= 700 mA 90 mV

out

42.2 kW

2.32 kW

330 mF, 25 V

80 mW, 1 W

= 0 to 700 mA 80 mV
= 0 to 700 mA 300 mVpp
= 700 mA 83%

3.1 A

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14

NCP3163, NCV3163

Figure 27. Boost Demo Board Layout

86

84

82

80

78

EFFICIENCY (%)

76

74

I

(A)

out

Figure 28. Efficiency vs. Output Current for the

Boost Demo Board at V

= 12 V, TA = 255C

in

0.6

0.70.50.40.30.20.1

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15

NCP3163, NCV3163

−

+

Thermal

Current

Limit

9

10

11

Q

1

Q

R

Q

S

Latch

V

CC

2

12

60

13

14

0.25 V

R

V

in

R

T

8

SC

7

+

C

in

C

T

6

V

CC

Oscillator

5

4

3

45 k

+

2

+
+

1

−

LVI

R

1

R

2

+

−

1.125 V

(Bottom View)

Feedback
Comparator

15 k1.25 V

15

2.0 mA

7.0 V

V

CC

16

Figure 29. Typical Voltage Inverting Application Schematic

L

R

B

C

B

D

V

C

O

+

out

Value of Components for V

= −15 V

out

Name Value

L

47 mH
D 2 A, 40 V Schottky Rectifier
C

in

C

out

C

t

Test Results for V

270 mF, 16 V

2 X 270 mF, 16 V

150 pF ±10%

= −15 V

out

Test Condition Results

Line Regulation Vin = 7.0 V to 16 V, I
Load Regulation Vin = 12 V, I
Output Ripple Vin = 12 V, I
Efficiency V
Short Circuit Current

out
out

= 12 V, I

in

V

in

out

= 12 V, RL = 0.1 W

Name Value

R

1

R

2

R

sc

C

b

R

b

= 500 mA 35 mV

out

1.07 kW

80 mW, 1 W

200 mW

= 0 to 500 mA 20 mV
= 0 to 500 mA 100 mVpp
= 500 mA 68%

3.1 A

11.8 kW

4.7 nF

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16

NCP3163, NCV3163

Figure 30. Voltage Inverting Demo Board Layout

70

66

62

58

EFFICIENCY (%)

54

50

0.350.30.250.20.150.1

I

(A)

out

Figure 31. Efficiency vs. Output Current for the

Voltage Inverting Demo Board at V

= 12 V, TA = 255C

in

0.50.450.4

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17

NCP3163, NCV3163

ORDERING INFORMATION

Device Package Shipping

NCP3163PWG SOIC−16 W Exposed Pad

NCP3163PWR2G SOIC−16 W Exposed Pad

NCP3163BPWG SOIC−16 W Exposed Pad

NCP3163BPWR2G SOIC−16 W Exposed Pad

NCP3163MNR2G DFN18

NCP3163BMNR2G DFN18

NCV3163PWG SOIC−16 W Exposed Pad

NCV3163PWR2G SOIC−16 W Exposed Pad

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

(Pb−Free)

(Pb−Free)

(Pb−Free)

(Pb−Free)

(Pb−Free)

(Pb−Free)

(Pb−Free)

(Pb−Free)

47 Units / Rail

1000 / Tape & Reel

47 Units / Rail

1000 / Tape & Reel

2500 / Tape & Reel

2500 / Tape & Reel

47 Units / Rail

1000 / Tape & Reel

†

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18

0.25 (0.010) W

M

PIN 1 I.D.

0.10 (0.004) T

SOIC 16 LEAD WIDE BODY, EXPOSED PAD

A

16 9

P

1

M

TOP SIDE

D16 PL

0.25 (0.010) T UW

H

−U−

8

G

14 PL

M

NCP3163, NCV3163

PACKAGE DIMENSIONS

PW SUFFIX

CASE 751AG−01

ISSUE O

B

−W−

C

K

S S

−T−

SEATING
PLANE

R x 45

_

DETAIL E

DETAIL E

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

M

F

J

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL BE

0.13 (0.005) TOTAL IN EXCESS OF THE D DIMENSION
AT MAXIMUM MATERIAL CONDITION.

6. 751R−01 OBSOLETE, NEW STANDARD 751R−02.

MILLIMETERS

DIMAMIN MAX MIN MAX

10.15 10.45 0.400 0.411

B 7.40 7.60 0.292 0.299
C 2.35 2.65 0.093 0.104
D 0.35 0.49 0.014 0.019
F 0.50 0.90 0.020 0.035
G 1.27 BSC 0.050 BSC
H 3.31 3.51 0.130 0.138
J 0.25 0.32 0.010 0.012
K 0.00 0.10 0.000 0.004
L 4.58 4.78 0.180 0.188
M 0 7 0 7
P 10.05 10.55 0.395 0.415
R 0.25 0.75 0.010 0.029

INCHES

____

EXPOSED PAD

18

L

16

9

BACK SIDE

SOLDERING FOOTPRINT*

0.350

0.175

0.050

C

L

0.200

0.074

0.024

0.145

DIMENSIONS: INCHES

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

C

L

Exposed
Pad

0.188

0.376

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19

NCP3163, NCV3163

PACKAGE DIMENSIONS

DFN18

CASE 505−01

ISSUE D

PIN 1 LOCATION

2X

2X

18X

18X

D

A

B

E

C0.15

C0.15

TOP VIEW

C0.10

(A3)

A

C0.08

SIDE VIEW

A1

C

SEATING

PLANE

NOTES:

1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.

2. DIMENSIONS IN MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN

0.25 AND 0.30 MM FROM TERMINAL

4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.

MILLIMETERS

DIM MIN MAX

A 0.80 1.00
A1 0.00 0.05
A3 0.20 REF

b 0.18 0.30

D 6.00 BSC
D2 3.98 4.28

E 5.00 BSC
E2 2.98 3.28

e 0.50 BSC

K 0.20 −−−

L 0.45 0.65

SOLDERING FOOTPRINT*

D2

L

e

19

1

5.30

18X

0.75

0.50

K18X

1018

BOTTOM VIEW

E2

b18X

0.05 C

4.19

A0.10 BC

NOTE 3

PITCH

18X

0.30

3.24

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
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For additional information, please contact your local
Sales Representative

NCP3163/D

20