ON Semiconductor NCP81071 User Manual

Dual 5 A High Speed Low-Side MOSFET Drivers with Enable

NCP81071

NCP81071 is a high speed dual low−side MOSFETs driver. It is capable of providing large peak currents into capacitive loads. This driver can deliver 5 A peak current at the Miller plateau region to help reduce the Miller effect during MOSFETs switching transition. This driver also provides enable functions to give users better control capability in different applications. ENA and ENB are implemented on pin 1 and pin 8 which were previously unused in the industry standard pin−out. They are internally pulled up to driver’s input voltage for active high logic and can be left open for standard operations. This part is available in MSOP8−EP package, SOIC8 package and WDFN8 3 mm x 3 mm package.

Features

•High Current Drive Capability ±5 A

•TTL/CMOS Compatible Inputs Independent of Supply Voltage

•Industry Standard Pin−out

•High Reverse Current Capability (6 A) Peak

•Enable Functions for Each Driver

•8 ns Typical Rise and 8 ns Typical Fall Times with 1.8 nF Load

•Typical Propagation Delay Times of 20 ns with Input Falling and 20Éns with Input Rising

•Input Voltage from 4.5 V to 20 V

•Dual Outputs can be Paralleled for Higher Drive Current

•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant

Applications

•Server Power

•Telecommunication, Datacenter Power

•Synchronous Rectifier

•Switch Mode Power Supply

•DC/DC Converter

•Power Factor Correction

•Motor Drive

•Renewable Energy, Solar Inverter

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		MARKING
		DIAGRAMS
		8
	SOIC−8	XXXX
	SOIC−8	ALYW
	D SUFFIX	ALYW
	D SUFFIX	G
	CASE 751	1
		1
		XXXX
	MSOP−8	AYW
	MSOP−8	G
	Z SUFFIX
	CASE 846AM
		1
	1	XX MG
	WDFN8	XX MG
	WDFN8	G
	MN SUFFIX
	CASE 511CD

XX = Specific Device Code

A = Assembly Location

L= Wafer Lot

Y= Year

W= Work Week

M= Date Code

G= Pb−Free Package

(Note: Microdot may be in either location)

PIN CONNECTIONS

1	8
ENA	ENB
INA	OUTA
GND	VDD
INB	OUTB
	(Top View)

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet.

♥ Semiconductor Components Industries, LLC, 2016	1	Publication Order Number:
March, 2021 − Rev. 4		NCP81071/D

NCP81071

VDD

ENA			VDD	ENA			VDD
Ref	Logic				Ref	Logic
VDD	Logic	VDD				Logic	VDD
VDD	A Channel	VDD				A Channel	VDD
	A Channel		OUTA			A Channel	OUTA
INA	VDD		OUTA	INA		VDD	OUTA
Ref	VDD				Ref	VDD
Ref					Ref

VDD	UVLO	VDD	VDD	UVLO	VDD
	UVLO			UVLO

ENB		OUTB	ENB	OUTB
Ref				Ref
VDD	Logic			Logic
VDD	B Channel			B Channel
	B Channel			B Channel

INB		GND	INB	GND
	Ref			Ref
	NCP81071A			NCP81071B
	VDD			VDD
	ENA			VDD
	Ref
	VDD		Logic	VDD
	VDD		A Channel	VDD
			A Channel	OUTA
	INA		VDD	OUTA
	Ref		VDD
	Ref
	VDD	UVLO		VDD
		UVLO

ENB	OUTB
	Ref
	Logic
	B Channel

INB

GND

Ref

NCP81071C

Figure 1. NCP81071 Block Diagram

Table 1. PIN DESCRIPTION

Pin No.

Symbol

Description

ENA

Enable input for the driver channel A with logic compatible threshold and hysteresis. This pin is used to en-

able and disable the driver output. It is internally pulled up to VDD with a 200 kW resistor for active high op-

eration. The output of the pin when the device is disabled will be always low.

INA

Input of driver channel A which has logic compatible threshold and hysteresis. If not used, this pin should be

connected to either VDD or GND. It should not be left unconnected.

GND

Common ground. This ground should be connected very closely to the source of the power MOSFET.

INB

Input of driver channel B which has logic compatible threshold and hysteresis. If not used, this pin should be

connected to either VDD or GND. It should not be left unconnected.

OUTB

Output of driver channel B. The driver is able to provide 5 A drive current to the gate of the power MOSFET.

VDD

Supply voltage. Use this pin to connect the input power for the driver device.

OUTA

Output of driver channel A. The driver is able to provide 5 A drive current to the gate of the power MOSFET.

ENB

Enable input for the driver channel B with logic compatible threshold and hysteresis. This pin is used to en-

able and disable the driver output. It is internally pulled up to VDD with a 200 kW resistor for active high op-

eration. The output of the pin when the device is disabled will be always low.

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NCP81071

TYPICAL APPLICATION CIRCUIT

NCP81071

ENA

ENB

INA

OUTA

GND

VDD

INB

OUTB

Table 2. ABSOLUTE MAXIMUM RATINGS

Value

Min

Max

Unit

Supply Voltage

VDD

−0.3

Output Current (DC)

Iout_dc

0.3

Reverse Current (Pulse< 1 ms)

6.0

Output Current (Pulse < 0.5 ms)

Iout_pulse

6.0

Input Voltage

INA, INB

−6.0

VDD+0.3

Enable Voltage

ENA, ENB

−0.3

VDD+0.3

Output Voltage

OUTA, OUTB

−0.3

VDD+0.3

Output Voltage (Pulse < 0.5 ms)

OUTA, OUTB

−3.0

VDD+3.0

Junction Operation Temperature

−40

150

°C

Storage Temperature

Tstg

−65

160

Electrostatic Discharge

Human body model, HBM

4000

Charge device model, CDM

1000

OUTA OUTB Latch−up Protection

500

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

Table 3. RECOMMENDED OPERATING CONDITIONS

Parameter	Rating	Unit

VDD supply Voltage	4.5 to 20	V

INA, INB input voltage	−5.0 to VDD	V

ENA, ENB input voltage	0 to VDD	V

Junction Temperature Range	−40 to +140	°C

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability.

Table 4. THERMAL INFORMATION

Package	qJA (5C/W)	qJC (5C/W)	YJT (5C/W) (Note 1)
SOIC−8	115	50

MSOP−8 EP	39	4.7	11

WDFN8 3x3	39	4.7

1. YJT: approximate thermal impedance, junction−to−case top.

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NCP81071

Table 5. INPUT/OUTPUT TABLE

				NCP81071A		NCP81071B		NCP81071C

ENA	ENB	INA	INB	OUTA	OUTB	OUTA	OUTB	OUTA	OUTB

H	H	L	L	H	H	L	L	H	L

H	H	L	H	H	L	L	H	H	H

H	H	H	L	L	H	H	L	L	L

H	H	H	H	L	L	H	H	L	H

L	L	Any	Any	L	L	L	L	L	L

Any	Any	x (Note 2)	x (Note 2)	L	L	L	L	L	L

x (Note 2)	x (Note 2)	L	L	H	H	L	L	H	L

x (Note 2)	x (Note 2)	L	H	H	L	L	H	H	H

x (Note 2)	x (Note 2)	H	L	L	H	H	L	L	L

x (Note 2)	x (Note 2)	H	H	L	L	H	H	L	H

2. Floating condition, internal resistive pull up or pull down configures output condition

PRODUCT MATRIX

NCP81071A

NCP81071B

NCP81071C

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NCP81071

Table 6. ELECTRICAL CHARACTERISTICS

(Typical values: VDD =12 V, 1 mF from VDD to GND, TA = TJ = −40°C to 140°C, typical at TAMB = 25°C, unless otherwise specified)

Parameter	Symbol	Test Conditions	Min	Typ	Max	Units

SUPPLY VOLTAGE

VDD Under Voltage Lockout (rising)	VCCR	VDD rising	3.5	4.0	4.5	V
VDD Under Voltage Lockout	VCCH			400		mV
(hysteresis)

Operating Current (no switching)	IDD	INA = 0, INB = 5 V, ENA = ENB = 0		1.4	3	mA
		INA = 5 V, INB = 0, ENA = ENB = 0
		INA = 0, INB = 5 V, ENA = ENB = 5 V
		INA = 5 V, INB = 0, ENA = ENB = 5 V

VDD Under Voltage Lockout to Output		VDD rising		10		ms
Delay (Note 3)

INPUTS

High Threshold	VthH	Input rising from logic low	1.8	2.0	2.2	V
Low Threshold	VthL	Input falling from logic high	0.8	1.0	1.2	V
INA, INB Pull−Up Resistance		OUTA = OUTB = Inverter Configuration		200		kW

INA, INB Pull−Down Resistance		OUTA = OUTB = Buffer Configuration		200		kW

OUTPUTS

Output Resistance High	ROH	IOUT = −10 mA		0.8	2	W
Output Resistance Low	ROL	IOUT = +10 mA		0.8	2	W
Peak Source Current (Note 4)	ISource	OUTA/OUTB = GND		5		A
		200 ns Pulse

Miller Plateau Source Current (Note 4)	ISource	OUTA/OUTB = 5.0 V		4.5		A
		200 ns Pulse

Peak Sink Current (Note 4)	ISink	OUTA/OUTB = VDD		5		A
		200 ns Pulse

Miller Plateau Sink Current (Note 4)	ISink	OUTA/OUTB = 5.0 V		3.5		A
		200 ns Pulse

ENABLE

High−Level Input Voltage	VIN_H	Low to High Transition	1.8	2.0	2.2	V
Low−Level Input Voltage	VIN_L	High to Low Transition	0.8	1.0	1.2	V
ENA, ENB pull−up resistance				200		kW

Propagation Delay Time (EN to OUT)	td3	CLoad = 1.8 nF	16	20	29	ns
(Notes 3, 5)

Propagation Delay Time (EN to OUT)	td4	CLoad = 1.8 nF	16	20	29	ns
(Notes 3, 5)

SWITCHING CHARACTERISTICS

Propagation Delay Time Low to High,	td1	CLoad = 1.8 nF	16	20	29	ns
IN Rising (IN to OUT) (Notes 3, 5)

Propagation Delay Time High to Low,	td2	CLoad = 1.8 nF	16	20	29	ns
IN Falling (IN to OUT) (Notes 3, 5)

Rise Time (Note 5)	tr	CLoad = 1.8 nF		8	15	ns
Fall Time (Note 5)	tf	CLoad = 1.8 nF		8	15	ns
Delay Matching between 2 Channels	tm	INA = INB, OUTA and OUTB at 50%		1	4	ns
(Note 6)		Transition Point

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.

3.Guaranteed by design.

4.Not production tested, guaranteed by design and statistical analysis.

5.See timing diagrams in Figure 2, Figure 3, Figure 4 and Figure 5.

6.Guaranteed by characterization.

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