ON Semiconductor NCP51561 User Manual

NCP51561 EVBUM

Isolated Dual Channel Gate Driver Evaluation Board User's Manual

Introduction

This user manual supports the evaluation board for the NCP51561. It should be used in conjunction with the NCP51561 datasheets as well as ON’s application notes and technical support team. Please visit ON’s website at www.onsemi.com

This document describes the proposed solution for 5 kV

RMS

EVAL BOARD USER’S MANUA

isolated dual channel gate driver using the NCP51561. This user’s guide also includes information regarding operating procedures, input/output connections, an electrical schematic, printed circuit board (PCB) layout, and a bill of material (BOM) for the evaluation board.

Description

The NCP51561 are isolated dual−channel gate driver with

4.5 A / 9 A source and sink peak current respectively. They are designed for fast switching to drive power MOSFETs, and SiC

Figure 1. Evaluation Board Photo

MOSFET power switches. The NCP51561 offers short and matched propagation delays.

Two independent and 5 kV

galvanically isolated gate driver

RMS

channels can be used in any possible configuration of two low−side, two high−side switches or a half−bridge driver with programmable dead time. A Enable pin shutdown both outputs simultaneously when is set low.

The NCP51561 offers other important protection functions such as independent under−voltage lockout for both gate drivers and enable function.

Key Features

• Flexible: Dual Low−Side, Dual High−Side or Half−Bridge Gate

Driver

• Independent UVLO Protections for Both Output Drivers

• Output Supply Voltage from 9.5 V to 30 V with 8 V for MOSFET,

17 V UVLO for SiC, Thresholds

• 4.5 A Peak Source, 9 A Peak Sink Output Current Capability

• Common Mode Transient Immunity CMTI > 200 V/ns

• Propagation Delay Typical 36 ns with

♦ 8 ns Max Delay Matching per channel ♦ 8 ns Max Pulse−Width Distortion

• User Programmable Input Logic

♦ Single or Dual−input modes via ANB ♦ ENABLE or DISABLE Mode

• User Programmable Dead−Time

FUNCTIONAL BLOCK DIAGRAM

INA

INB

ANB

NA/DIS

GND

• Isolation & Safety

♦ 5 kV

Galvanic Isolation from Input to each Output and

RMS

1500 V Peak Differential Voltage between Output Channels (per UL1577 Requirements)

♦ 1200 V Working Voltage (per VDE0884−11 Requirements)

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PIN CONNECTIONS

INA

INB

GND

ENA/DIS DT

ANB

VDD UVLO

INA

INB

LOGIC

DEAD

TIME

CONTROL

INA

INB

Tx Rx

VCCA

OUTA

VSSA

VCCB

OUTB

VSSB

Isolation

Input to Output

UVLO

[5V, 8V, 17V]

UVLO

[5V, 8V, 17V]

Functional

Isolation

VCC

LOGIC

OUT

VSS

VCC

OUT

VSS

March, 2021 − Rev. 1

1 Publication Order Number:

EVBUM2771/D

NCP51561 EVBUM

EVALUATION BOARD OPERATION

This section describes how to operate the NCP51561 evaluation board (EVB). Make external connections to the NCP51561 EVB using either the installed test−points or by installing wires into the connectors. The main connections that must be made to the EVB are the analog supply voltage, input signal, and output load and monitoring equipment.

Features

• Evaluation board for the NCP5156x product family in a

wide body SOIC−16 package

• 3 V to 5.0 V VDD power supply range, and up to 30 V

VCCA/VCCB power supply range

• 4.5 A and 9 A source/sink current driving capability

• 5 kV

Isolation for 1 minute per UL 1577

RMS

• TTL −compatible inputs

• Allowable input voltage up to 18 V with for INA, INB,

and ANB pins

• Onboard trimmer potentiometer for dead−time

programming

• 3−position header with for INA, INB, ENA/DIS and

• 2−position header with for ANB

• Support for half−bridge test with MOSFETs, IGBTs

and SiC MOSFETs with connection to external power stage

Power and Ground

NOTE: Connecting the all power supplies in reverse

polarity (backwards) will instantly device when power is turned on and device damage can result.

The primary side of the EVM (V 3 V to 5.0 V power supply and connected via J2. T est point

DD) operates from a single

(TP6 and TP7) is available for monitoring the primary power supply.

The EVM provides connections for evaluating the output

side (V

CCA, VSSA, VCCB, and VSSB) power supplies for the

channel A and B, from a minimum 9.5 V to maximum 30 V for 8 V UVLO version as shown in Figure 4. V

CCA and VCCB

can be monitored via TP9 and TP13, respectively.

The V

CCA and VCCB pin should be bypassed with a

capacitor with a value of at least ten times the gate capacitance, and over 100 nF and located as close to the device as possible for the purpose of decoupling. A low ESR, ceramic surface mount capacitor is necessary. We had recommends using 2 capacitors; a over 100 nF ceramic surface−mount capacitor, and another a tantalium or electrolytic capacitor of few microfarads added in parallel.

Input and Output

1. Connection of primary−side power supply to the V

connector [J2].

2. Connection of secondary−side power supply to the V

CCA

and V

connector [J9, and J13].

CCB

3. Connection of INA signal to the SIGNAL connector [J1−1, and J4].

4. Connection of INB signal to the SIGNAL connector [J1−2, and J5].

5. Connection of ENABLE signal to the ENA/DIS connector [J1−3, and J15].

6. Connection of ANB signal to the ANB jumper [J11].

7. Connection of DC link power supply to the V

connector [J6].

8. Connection of bridge output to the V

connector

SSA

[J7 and J12].

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Evaluation Board Jumper Setting

Table 1. EVB JUMPER SETTING

Jumper

Jumper Setting Options

Default

Option1

Jumper not installed, INA/PWM signal provided by external signal and this pin is default low if left open

Option2

Jumper on J4−INA−2 and J4−INA−3 set INA low

Option3

Jumper on J4−INA−2 and J4−INA−1 set INA high

Option1

Jumper not installed, INB signal provided by external signal and this pin is default low if left open

Option2

Jumper on J5−INB−2 and J5−INB−3 set INB low

Option3

Jumper on J5−INB−2 and J5−INB−1 set INB high

Option1

Jumper on J11−ANB−2 and J11−ANB−4 set ANB low for dual input mode

Option2

Jumper on J11−ANB−1 and J11−ANB−3 set ANB high for single input (PWM) mode

Option1

Jumper not installed, DISABLE signal provided by external signal and this pin is default low if left open

Option2

Jumper on J15−ENA/DIS−2 and J15−ENA/DIS−3 set DISABLE low (Or ENABLE low)

Option3

Jumper on J15−ENA/DIS−2 and J15−ENA/DIS−1 set DISABLE high (Or ENABLE high)

Option1

Jumper not installed and R13 is open or below 1 kW, shoot−through prevention with 10−ns dead time

Option2

Jumper on J14−DT−1 and J14−DT−2 set DT VDD for allows driver both output overlap or driver output

Option3

Jumper on J14−DT−3 and J14−DT−4 set DT for fixed resistance for 20 kW.

Option4

Jumper not installed and R13 = 100 kW. It is recommended close to the DT pin to achieve better noise

Option5

Jumper on J14−DT−5 and J14−DT−6 set the dead time by DT (in ns) = R

(in kW) × 10. For better

Option1

Jumper on T.P1−1 and T.P1−2 for half−bridge application

Option2

Jumper off T.P1−1 and T.P1−2 for bench test.

Option1

Jumper on T.P2−1 and T.P2−2 and jumper on J16−2 and J16−4 for single power supply (VCCA=VCCB)

Option2

Jumper on T.P2−1 and T.P2−2 and and jumper on J16−1 and J16−3 for VCCA bootstrap supply

Option1

Jumper on T.P3−1 and T.P3−2 for single power supply (e.g. VSSA=VSSB)

Option2

Jumper off T.P3−1 and T.P3−2 for dual power supply

J4−INA

NCP51561 EVBUM

Setting

Option1

J5−INB

J11−ANB

J15−EN

A/DIS

J14_DT

T.P1

T.P2

T.P3

Option1

Option

Option2

Option

follow input signals (INA & INB)

immunity.

noise immunity and dead−time matching, We recommends to parallel a 2.2−nF or above bypassing capacitor from DT pin to GND.

Option2

Option1

Evaluation Board Setting before Power Up

1. If the ENABLE function is used, ENA/DIS pin (PIN5) should be connected to VDD (PIN3 or PIN8) through a wire−bridge between pin 1 and

In addition, Cross−conduction between both driver outputs (OUTA, and OUTB) is not allowed with minimum dead time (t

the DT pin is floating (Open). pin 2 of J15 or this pin is default HIGH if left open.

On the other hand, if using the Disable mode , should be connect ENA/DIS pin to GND pin through a wire−bridge between pin 2 and pin 3 of J15.

2. If using the dual input mode, should be ANB pin (PIN7) connected to GND (PIN4) through a wire−bridge between pin 2 and pin 4 of J11 or this pin is default low if left open. On the other hand, if using the single input mode, should be connect ANB pin to VDD pin through a wire−bridge between pin 1 and pin 3 of J11.

3. Should be connect to the resistance between DT pin (pin6) and GND (pin4) for dead−time control

Bench Setup

The bench setup diagram includes the function generator,

power supplies and oscilloscope connections.

Follow the connection procedure below and use Figure 2

as a reference

• Make sure all the output of the function generator,

power supplies are disabled before connection

• Function generator channel−A channel applied on INA

(J3 or J1 pin−1) ↔ TP1 as seen in Figure 2.

• Function generator channel−B channel applied on INB

(J10 or J1 pin−2) ↔ TP2 as seen in Figure 2.

• If the ENABLE function is not used, ENA/DIS pin

(PIN5) should be connected to VDD (PIN3 or PIN8)

mode.

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DTMIN) typically 10 ns when

NCP51561 EVBUM

through a wire−bridge between pin 1 and pin 2 of J15 or this pin is default HIGH if left open.

• If using the dual input signals (INA and INB) with

same polarity, should be DT pin (PIN6) connected to VDD (PIN3 or 8) through a wire−bridge between pin 1 and pin 2 of J14. On the other hand, if using the dual input signals with opposite polarity, should be connect to the resistance (R13) between DT pin (pin6) and GND (pin4) or DT pin is floating (Open).

• If using the dual input mode, should be ANB pin

(PIN7) connected to GND (PIN4) through a wire−bridge between pin 2 and pin 4 of J11 or this pin is default low if left open. On the other hand, if using the single input mode,

should be connect ANB pin to VDD pin through a wire−bridge between pin 1 and pin 3 of J11.

• Power supply #1: positive node applied on J2 pin−1 (or

TP6), and negative node applied on J2 pin−2.

• Power supply #2: positive node applied on J9 pin−1(or

TP14), negative node connected directly to J9 pin−2 (or TP10) and should be connected to VAIN and VCCA through a wire−bridge between pin 2 and pin 4 of J16.

• Power supply #3: positive node applied on J13 pin−1

(or TP13), negative node connected directly to J13 pin−2 (or TP17)

• Oscilloscope channel−A probes TP8 ↔ TP10, smaller

measurement loop is preferred

• Oscilloscope channel−B probes TP14 ↔ TP17, smaller

measurement loop is preferred

POWER

SUPPLY #1

(5V/0.05A)

Figure 2. Bench Setup Diagram and Configuration

POWER

SUPPLY #2

(12V/0.1A)

POWER

SUPPLY #3

(12V/0.1A)

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Power Up and Power Down Procedure

Power Up

1. Could be connect VSSA pin to VSSB pin through a wire−bridge between pin 1 and pin 2 of T.P3, if the Half−Bridge application is not used.

2. Enable power supply through pin1 of J2 VDD connector in primary−side

3. Enable power supply through pin1 of J9 VCCA connector and through pin1 of J13 VCCB connector in secondary−side Measure the quiescent current of VCCA, and VCCB on DMM1 and DMM2 ranges from 0.5 mA to approximately 1.0 mA if everything is set correctly;

NCP51561 EVBUM

4. Enable the function generator, two−channel outputs: channel−A and channel−B;

5. There will be: A. Stable pulse output on the channel−A and channel−B in the oscilloscope B. Scope frequency measurement is the same with function generator output; C. DMM #1 and #2 read measurement results should be around 2.5 mA ± 1 mA under no load conditions. For more information about operating current, refer to the NCP51561 data sheet.

CH1: INA, CH2: INB, CH3: OUTA, and CH4: OUTB

Figure 3. Experimental Waveforms of Input to Output

Power Down

1. Disable function generator

2. Disable power supply of VCCA, and VCCB in secondary−side

3. Disable power supply of VDD in primary−side

4. Disconnect cables and probes

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