ON Semiconductor NCP51199, NCV51199 User Manual

NCP51199, NCV51199

DDR 2-Amp Source / Sink
V

Termination Regulator

TT

The NCP/NCV51199 is a linear regulator designed to supply a

regulated V

termination voltage for DDR−2 and DDR−3 memory

TT

applications. The regulator is capable of actively sourcing and sinking

±2 A peak currents for DDR−2, and DDR−3 up to ±1.5 A while

regulating the V
termination voltage is regulated to track V
voltage divider resistors connected to the PV

output voltage to within ±10 mV. The output

TT

/ 2 by two external

DDQ

, GND, and V

CC

REF

pins.

The NCP/NCV51199 incorporates a high−speed differential
amplifier to provide ultra−fast response to line and load transients.
Other features include source/sink current limiting, soft−start and
on−chip thermal shutdown protection.

Features

• Supports DDR−2 V

• Stable with 10 mF Ceramic Capacitance on V

Termination to ±2 A, DDR−3 to ±1.5 A (peak)

TT

Output

TT

• Integrated Power MOSFETs

• High Accuracy V

Output at Full−Load

TT

• Fast Transient Response

• Built−in Soft−Start

• Shutdown for Standby or Suspend Mode

• Integrated Thermal and Current−Limit Protection

• NCV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable

• These Devices are Pb−Free and are RoHS Compliant

Typical Applications

• SDRAM Termination Voltage for DDR−2 / DDR−3

• Motherboard, Notebook, and VGA Card Memory Termination

• Set Top Box, Digital TV, Printers

www.

onsemi.com

MARKING
DIAGRAM

8

1

NCPVCC
NC
V

NCV

CC

XXXXXX

ALYW

G

8

See detailed ordering, marking and shipping information in the
package dimensions section on page 6 of this data sheet.

SOIC8−NB EP

PD SUFFIX

CASE 751BU

1

XXXXXX = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
WW = Work Week
G = Pb−Free Package

PIN CONNECTION

18

GND

VREF

TT

SOIC−8 EP

ORDERING INFORMATION

© Semiconductor Components Industries, LLC, 2017

April, 2017 − Rev. 3

1 Publication Order Number:

NCP51199/D

= 1.5 to 5.0 V*

PV

CC

NCP51199, NCV51199

NCP51199

1

PV

CC

C2

6

V

CC

5 V

C3

Enable

R2

100k

R1

100k

C1

2

3

GND

V

REF

= 0.75 to 2.5 V*

V

C4

TT

R3

4

V

TT

*For DDR2: PVCC = 1.8 V, VTT = 0.9 V

DDR3: PV

= 1.5 V , VTT = 0.75 V

CC

C1 = 1 mF (Low ESR) C4 = 1000 mF + 10 mF (10 mF ceramic)
C2 = 470 mF (Low ESR) R3 = Optional V

discharge resistor

TT

C3 = 47 mF N−ch MOSFET = Optional Enable / Disable

Figure 1. Application Diagram

PIN FUNCTION DESCRIPTION

Pin No. Pin Name Description

1 PV

CC

2 GND Common Ground
3 V

4 V

REF

TT

5 NC True No Connect
6 V

CC

7 NC True No Connect
8 NC True No Connect

EP Thermal Pad Pad for thermal connection. The exposed pad must be connected to the ground plane using multiple

Input voltage which supplies current to the output pin. CIN = 470 mF with low ESR.

Buffered reference voltage input equal to ½ of V
divider dividing down the PV
(0.15 V maximum) turns the device off.

voltage creates the regulated output voltage. Pulling the pin to ground

CC

and active low shutdown pin. An external resistor

DDQ

Regulator output voltage capable of sourcing and sinking current while regulating the output rail.

= 1000 mF + 10 mF ceramic with low ESR.

C

OUT

The VCC pin is a 5 V input pin that provides internal bias to the controller. PVCC should always be kept
lower or equal to V

.

CC

vias for maximum power dissipation performance.

www.onsemi.com

2

NCP51199, NCV51199

ABSOLUTE MAXIMUM RATINGS

Rating Symbol Value Unit

Input Supply Voltage Range (Vcc w PVCC) (Note 1) PVCC,

V

CC

Output Voltage Range V
Reference Input Range V
Maximum Junction Temperature T

TT

REF

J(max)

Storage Temperature Range TSTG −65 to 150 °C
ESD Capability, Human Body Model (Note 2) ESDHBM 2 kV
ESD Capability, Machine Model (Note 2) ESDMM 150 V
Lead Temperature Soldering

Reflow (SMD Styles Only), Pb−Free Versions (Note 3)

T

SLD

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.

1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.

2. This device series incorporates ESD protection and is tested by the following methods:

ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Latchup Current Maximum Rating: ≤150 mA per JEDEC standard: JESD78

3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D

−0.3 to 6 V

−0.3 to 6 V

−0.3 to 6 V
125 °C

260 °C

THERMAL CHARACTERISTICS

Rating Symbol Value Unit

Thermal Characteristics, SO8−EP (Note 4)

Thermal Resistance, Junction−to−Air (Note 5)
Power Rating at 25°C Ambient = 1.19 W, derate 12 mW/°C
Thermal Reference, Junction−to−Lead2 (Note 5)

4. Refer to ELECTRICAL CHARACTERISTIS and APPLICATION INFORMATION for Safe Operating Area.

5. Values based on copper area of 645 mm

2

(or 1 in2) of 1 oz copper thickness and FR4 PCB substrate.

R

q

JA

R

Y

JL

OPERATING RANGES (Note 6)

Rating

Input Voltage PV
Bias Supply Voltage V
Ambient Temperature T
Junction Temperature T

6. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.

Symbol Min Max Unit

CC

CC

A

J

1.5 5.5 V

4.75 5.25 V

−40 85 °C

−40 125 °C

84

°C/W

20

www.onsemi.com

3