ON Semiconductor NCP5106BA36WGEVB User Manual

NCP5106BA36WGEVB

NCP5106B 36W Ballast
Evaluation Board User's
Manual

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EVAL BOARD USER’S MANUAL

Introduction

This document describes how the NCP5106B driver can
be implemented in a ballast application. The scope of this
application note is to highlight the NCP5106B driver and not
to explain or detailed how to build electronic ballast.

The NCP5106B is a high voltage power MOSFET driver
providing two outputs for direct drive of 2 N−channel power
MOSFETs arranged in a half−bridge configuration with a
cross conduction protection between the 2 channels.

It uses the bootstrap technique to insure a proper drive of
the High−side power switch. The driver works with 2
independent inputs to accommodate any topology
(including half−bridge, asymmetrical half−bridge, active
clamp and full−bridge).

Evaluation Board Specification

• Input range : 85 − 145 Vac or 184 − 265 Vac

• Ballast Output power : 36 W (type PL−L 36W)

♦ Pre−Heating current : 295 mA
♦ Pre−heating time : 1 second
♦ Nominal current : 414 mA

BEFORE PLUGGING IN THE DEMO BOARD, MAKE
SURE THE JUMPER IS ON THE CORRECT POSITION:
IF J2 IS USED, THEN Vin MUST BE LOWER THAN
145 Vac.

Detailed Operation

The lamp ballast is powered via a half bridge
configuration. The 2 power MOSFETs are driven with the
NCP5106B driver. The driver is supplied by the VCC rail,
and the high side driver is supplied by the bootstrap diode:
when the low side power MOSFET (Q2) is switched ON, the
BRIDGE pin is pulled down to the ground, thus the capacitor
connected between BRIDGE pin and VBOOT pin is
refuelled via the diode D3 and the resistor R5 connected to
V

. When Q2 is switched OFF the bootstrap capacitor C6

CC

supplies the high side driver with a voltage equal to V
level minus the D3 forward voltage diode. Given the
NCP5106B architecture, it is up to the designer to generate
the right input signal polarity with the desired dead time.
Nevertheless the NCP5106B provides a cross conduction
protection with an internal fixed dead time. Thus in case of
overlap on the inputs signal, the both outputs driver will be
kept in low state, or a minimum of 100 ns dead time will be
applied between the both drivers.

The 555 timer generates only one signal for the driver, the
second one, in opposite phase is built by inserting a NPN
transistor (Q4) for inverting the signal. Afterwards the dead
time is built with R2, D2 and C13 (typically 400 ns, see
Figure 2).

CC

© Semiconductor Components Industries, LLC, 2012

November, 2012 − Rev. 1

Figure 1. Evaluation Board Photo

1 Publication Order Number:

EVBUM2154/D

NCP5106BA36WGEVB

DRV_HI

Dead time 40 0 ns

Figure 2. Dead Time Between the High and Low Side Driver

(5 V/div)

DRV_LO
(5 V/div)

Time
(400 ns/div)

IN_HI
(10 V/div)

Figure 3. Input Output Timing Diagram

DRV_HI
(10 V/div)

IN_LO
(10 V/div)

DRV_LO
(10 V/div)

Time
(4 ms/div)

Tube
Voltage
(100 V /div)

Tube
current
(0.5 V/div)

Figure 4. Tube Signals

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2

Tube
Power

(50 W/div)

Tube average
power = 32 W

NCP5106BA36WGEVB

C7

220nF

400V

B1

L1

Q1

IRF840LC

R8

10k

R6

10R

C6

100nF

R5

10R

D3

1N4936

C5

100nF

C4

4.7uF

R4

82k

2W

R3

82k

2W

C1

47 uF

400 V

SerieM Panasonic

C1

47 uF

400 V

SerieM Panasonic

1

1

PT1

4

J1

2

DF06

2

GND

F1

T500 mA

1

2

CON2

VCC

J2

3

US−jumper

R1

GND

C3

D1

7

8

VBOOT

VCC1IN_HI2IN_LO3GND

GND GND

110k

D2

R2

22k

220uF

15V

1.3W

GND GND

DRV_HI

6

BRIDGE

1N4148

VCC

U1

R10

1.4mH

5

DRV_LO

U2

4

R13

15k

3

Q

VCC8GND

R

TLC555C

4

33k

C8

220nF

400V

C15

BALLAST

R7

10R

C14

NCP5106B

GND

C13

18pF

C12

18pF

Q4

BC547B

7

DIS

TRIG

2

6.8nF

1kV

Q2

IRF840LC

R9

10k

R14

390k

D6

220pF/400V

D5

1N4936

GND GND

GND

6

THR

1

CVolt

5

C11

10nF

VCC

1N4936

GND

R11

47k

C9

GND

220pF

GND

GND

GND

GND

VCC

Q3

R12

D4

BC547B

27k

5V1

R16

C17

R15

C10

C16

68k

100 uF

22k

GND

220pF

NC

Figure 5. Evaluation Board Schematic

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