NCP302155
Integrated Driver and
MOSFET
The NCP302155 integrates a MOSFET driver, high−side MOSFET
and low−side MOSFET into a single package.
The driver and MOSFETs have been optimized for high−current
DC−DC buck power conversion applications. The NCP302155
integrated solution greatly reduces package parasitics and board space
compared to a discrete component solution.
Features
• Capable of Average Currents up to 55 A
• Capable of Switching at Frequencies up to 2 MHz
• Compatible with 3.3 V or 5 V PWM Input
• Responds Properly to 3−level PWM Inputs
• Option for Zero Cross Detection with 3−level PWM
• Internal Bootstrap Diode
• Undervoltage Lockout
• Supports Intel® Power State 4
• Thermal Warning output
• Thermal Shutdown
Applications
• Notebook, Tablet PC and Ultrabook
• Servers and Workstations, V−Core and Non−V−Core DC−DC
Converters
• Desktop and All−in−One Computers, V−Core and Non−V−Core
DC−DC Converters
• High−Current DC−DC Point−of−Load Converters
• Small Form−Factor Voltage Regulator Modules
5V
VCCD
VCC VIN
Zero Current
Detect Enable
DRVON from controller
PWM from controller
SMOD from controller
ZCD_EN
DISB#
PWM
SMOD#
CGND PGND
THWN
BOOT
VSW
VOUT
PGND
PGND
PGND
PGND
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PQFN31 5X5, 0.5P
CASE 483BR
MARKING DIAGRAM
NCP
302155
AWLYYWW
Pin1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
PINOUT DIAGRAM
BOOT
nc
PHASE
VIN
8 7 6 5 4 3 2 1
9 10 11 12 13 14 15
VIN
VIN
VIN
16 17 18 19 20 21 22 23
VSW
VSW
VSW
VSW
PWM
SMOD#
VC C
CGND
DISB#
32
AGND
33
GL
VSW
VSW
VSW
THWN
VCCD
PGND
GL
VSW
VSW
VSW
24 25 26 27 28 29 30 31
VSW
Figure 1. Application Schematic
© Semiconductor Components Industries, LLC, 2018
March, 2021 − Rev. 4
ORDERING INFORMATION
Device Package Shipping
NCP302155MNTWG PQFN31
3000 / Tape &
5x5
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
1 Publication Order Number:
NCP302155/D
†
Reel
VCCD
VCC
SMOD#
PWM
DISB#
THWN
AGND
CGND
NCP302155
29
3
UVLO
VCC
2
1
31
30
32
4
ZCD
CONTROL
DEAD
TIME
CONTROL
LEVEL
SHIFT
LEVEL
SHIF
SHUTDOWN
WARNING
TEMP
SENSE
Figure 2. Block Diagram
8−11
16−26
12−15
27
33
5
7
28
BOOT
VIN
VSW
PHASE
PGND
PGND
GL
GL
Table 1. PIN LIST AND DESCRIPTION
Pin No. Symbol Description
1 PWM PWM Control Input and Zero Current Detection Enable
2 SMOD# Skip Mode pin. 3−state input (see Table 6):
SMOD# = High ³ State of PWM determine whether the NCP302155 performs ZCD or not.
SMOD# = Mid ³ Connects PWM to internal resistor divider placing a bias voltage on PWM pin.
Otherwise, logic is equivalent to SMOD# in the high state.
SMOD# = Low ³ Placing PWM into mid−state pulls GH and GL low without delay.
There is an internal pull−up resistor to VCC on this pin.
3 VCC Control Power Supply Input
4, 32 CGND, AGND Signal Ground (pin 4 and pad 32 are internally connected)
5 BOOT Bootstrap Voltage
6 nc Open pin (not used)
7 PHASE Bootstrap Capacitor Return
8−11 VIN Conversion Supply Power Input
12−15, 28 PGND Power Ground
16−26 VSW Switch Node Output
27, 33 GL Low Side FET Gate Access (pin 27 and pad 33 are internally connected)
29 VCCD Driver Power Supply Input
30 THWN Thermal warning indicator. This is an open−drain output. When the temperature at the driver die
31 DISB# Output disable pin. When this pin is pulled to a logic high level, the driver is enabled. There is an
reaches T
, this pin is pulled low.
THWN
internal pull−down resistor on this pin.
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2
NCP302155
Table 2. ABSOLUTE MAXIMUM RATINGS (Electrical Information − all signals referenced to PGND unless noted otherwise)
Pin Name / Parameter
VCC, VCCD −0.3 6.5 V
VIN −0.3 30 V
BOOT (DC) −0.3 35 V
BOOT (< 20 ns) −0.3 40 V
BOOT to PHASE (DC) −0.3 6.5 V
VSW, PHASE (DC) −0.3 30 V
VSW, PHASE (< 20 ns) −5 35 V
PHASE (< 5 ns) −15 35 V
All Other Pins −0.3 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 3. THERMAL INFORMATION
Rating Symbol Value Unit
Thermal Resistance (under On Semi SPS Thermal Board)
Operating Junction Temperature Range (Note 1) T
Operating Ambient Temperature Range T
Maximum Storage Temperature Range T
Maximum Power Dissipation 10.5 W
Moisture Sensitivity Level MSL 1
1. The maximum package power dissipation must be observed.
2. JESD 51−5 (1S2P Direct−Attach Method) with 0 LFM
3. JESD 51−7 (1S2P Direct−Attach Method) with 0 LFM
Min Max Unit
+ 0.3 V
VCC
q
q
J−PCB
JA
J
A
STG
12.4
1.8
−40 to +150
−40 to +125
−55 to +150
_C/W
_C/W
_C
_C
_C
Table 4. RECOMMENDED OPERATING CONDITIONS
Parameter Pin Name Conditions Min Typ Max Unit
Supply Voltage Range VCC, VCCD 4.5 5.0 5.5 V
Conversion Voltage VIN 4.5 19 24 V
Continuous Output Current
Peak Output Current
FSW = 1 MHz, VIN = 12 V, V
FSW = 300 kHz, VIN = 12 V, V
Duration = 5 ms, Period = 10 ms
= 1.0 V, TA = 25_C
OUT
= 1.0 V, TA = 25_C
OUT
Junction Temperature −40 125
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
55 A
60 A
85 A
_C
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NCP302155
Table 5. ELECTRICAL CHARACTERISTICS
(V
= V
VCC
temperature range −40°C ≤ T
VCC SUPPLY CURRENT
Operating
No switching DISB# = 5 V, PWM = 0 V − − 2 mA
Disabled
UVLO Start Threshold V
UVLO Hysteresis 150 − − mV
VCCD SUPPLY CURRENT
Enabled, No switching
Disabled DISB# = 0 V − 0.4 1
Operating DISB# = 5 V, PWM = 400 kHz − − 26 mA
DISB# INPUT
Input Resistance
Upper Threshold V
Lower Threshold V
Hysteresis V
Enable Delay Time Time from DISB# transitioning HI
Disable Delay Time Time from DISB# transitioning
SMOD# INPUT
SMOD# Input Voltage High
SMOD# Input Voltage Mid−state V
SMOD# Input Voltage Low V
SMOD# Input Resistance R
SMOD# Propagation Delay, Falling T
SMOD# Propagation Delay, Rising T
PWM INPUT
Input Voltage High
Input Mid−state Voltage V
Input Low Voltage V
Input Resistance R
Input Resistance R
PWM Input Bias Voltage V
Non−overlap Delay, Leading Edge T
Non−overlap Delay, Trailing Edge T
PWM Propagation Delay, Rising T
VCCD
= 5.0 V, V
Parameter
= 12 V, V
VIN
≤ 125°C unless noted otherwise, and are guaranteed by test, design or statistical correlation.)
J
DISB#
= 2.0 V, C
VCCD
= C
= 0.1 mF unless specified otherwise) Min/Max values are valid for the
VCC
Symbol Conditions Min. Typ. Max. Unit
DISB# = 5 V, PWM = 400 kHz − 1 2 mA
DISB# = 0 V, SMOD# = VCC − 0.4 1
DISB# = 0 V, SMOD# = GND 6 15
UVLO
VCC rising 2.89 − 3.37 V
DISB# = 5 V, PWM = 0 V,
V
PHASED
= 0 V
− 175 300
To Ground − 467 −
UPPER
LOWER
UPPER
− V
LOWER
− − 2.0 V
0.8 − − V
200 − − mV
− − 40
to when VSW responds to PWM.
− 21 50 ns
LOW to when both output FETs
are off.
V
SMOD_HI
SMOD#_MID
SMOD_LO
SMOD#_UP
SMOD#_PD_F
SMOD#_PD_R
V
PWM_HI
PWM_MID
PWM_LO
PWM_HIZ
PWM_BIAS
PWM_BIAS
NOL_L
NOL_T
PWM,PD_R
Pull−up resistance to VCC − 455 −
SMOD# = Low to GL = 90%,
PWM = MID
SMOD# = High to GL = 10%,
PWM = MID
SMOD# = V
V
SMOD#_LO
SMOD# = V
SMOD# = V
SMOD#_HI
SMOD#_MID
SMOD#_MID
or
GL Falling = 1 V to GH−VSW Rising = 1 V
GH−VSW Falling = 1 V to
GL Rising = 1 V
PWM = High to GL = 90% − 13 35 ns
2.65 − − V
1.4 − 2.0 V
− − 0.7 V
− 34 42 ns
− 22 30 ns
2.65 − − V
1.4 − 2.1 V
− − 0.7 V
10 − −
− 68 −
− 1.7 − V
− 13 − ns
− 12 − ns
mA
mA
mA
mA
kW
ms
kW
MW
kW
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NCP302155
Table 5. ELECTRICAL CHARACTERISTICS
(V
= V
VCC
temperature range −40°C ≤ T
PWM Propagation Delay, Falling T
Exiting PWM Mid−state Propagation
Delay, Mid−to−Low
Exiting PWM Mid−state Propagation
Delay, Mid−to−High
ZD FUNCTION
Zero Cross Detect Threshold
ZCD Blanking + Debounce Time t
THERMAL WARNING & SHUTDOWN
Thermal Warning Temperature
Thermal Warning Hysteresis T
Thermal Shutdown Temperature T
Thermal Shutdown Hysteresis T
THWM Open Drain Current I
BOOST STRAP DIODE
Forward Voltage
HIGH−SIDE DRIVER
Output Impedance, Sourcing
Output Sourcing Peak Current I
Output Impedance, Sinking R
Output Sinking Peak Current I
LOW−SIDE DRIVER
Output Impedance, Sourcing
Output Sourcing Peak Current I
Output Impedance, Sinking R
Output Sinking Peak Current I
GL Rise Time T
GL Fall Time T
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
VCCD
= 5.0 V, V
= 12 V, V
VIN
J
DISB#
≤ 125°C unless noted otherwise, and are guaranteed by test, design or statistical correlation.)
Parameter UnitMax.Typ.Min.ConditionsSymbol
= 2.0 V, C
PWM,PD_F
T
PWM_EXIT_L
T
PWM_EXIT_H
V
ZCD
BLNK
T
THWN
THWN_HYS
THDN
THDN_HYS
THWN
R
SOURCE_GH
SOURCE_GH
SINK_GH
SINK_GH
R
SOURCE_GL
SOURCE_GL
SINK_GH
SINK_GL
R_GL
F_GL
= C
VCCD
= 0.1 mF unless specified otherwise) Min/Max values are valid for the
VCC
PWM = Low to SW = 90% − 47 52 ns
PWM = Mid−to−Low to GL = 10% − 14 25 ns
PWM = Mid−to−High to SW = 10% − 13 25 ns
− −6 − mV
− 330 − ns
Temperature at Driver Die − 150 −
− 15 −
Temperature at Driver Die − 180 −
− 25 −
− − 5 mA
Forward Bias Current = 2.0 mA − 380 − mV
Source Current = 100 mA − 0.9 −
− 2 − A
Source Current = 100 mA − 0.7 −
− 2.5 − A
Source Current = 100 mA − 0.9 −
GL = 2.5 V − 2 − A
Sink Current = 100 mA − 0.4 −
GL = 2.5 V − 4.5 − A
GL = 10% to 90%, C
GL = 90% to 10%, C
= 3.0 nF − 12 − ns
LOAD
= 3.0 nF − 6 − ns
LOAD
_C
_C
_C
_C
W
W
W
W
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NCP302155
Table 6. LOGIC TABLE
INPUT TRUTH TABLE
DISB# PWM SMOD# (Note 4) GH (not a pin) GL
L X X L L
H H X H L
H L X L H
H MID H or MID L ZCD (Note 5)
H MID L L L (Note 6)
4. PWM input is driven to mid−state with internal divider resistors when SMOD# is driven to mid−state and PWM input is undriven externally.
5. GL goes low following 80 ns de−bounce time, 250 ns blanking time and then SW exceeding ZCD threshold.
6. There is no delay before GL goes low.
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NCP302155
TYPICAL PERFORMANCE CHARACTERISTICS
Test Conditions: VIN = 12 V, VCC = V
otherwise noted.
Figure 3. Efficiency − 19 V Input, 1.0 V Output Figure 4. Efficiency − 19 V Input, 1.8 V Output
CCD
= 5 V, V
OUT
= 1 V, L
= 250 nH, TA = 25 °C and natural convection cooling, unless
OUT
Figure 5. Efficiency − 12 V Input, 1.0 V Output Figure 6. Efficiency − 12 V Input, 1.8 V Output
Figure 7. Power Iosses vs. Output Current, 12 Vin Figure 8. Power Iosses vs. Output Current, 19 Vin
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TYPICAL PERFORMANCE CHARACTERISTICS
Test Conditions: VIN = 12 V, VCC = PVCC = 5 V, V
otherwise noted.
Figure 9. Power Loss vs. Switching Frequency Figure 10. Power Loss vs. Input Voltage
OUT
= 1 V, L
NCP302155
= 250 nH, TA = 25 °C and natural convection cooling, unless
OUT
Figure 11. Power Loss vs. Driver Supply Voltage Figure 12. Power Loss vs. Output Voltage
Figure 13. Driver Supply Current vs. Switching
Frequency
Figure 14. Driver Supply Current vs. Driver Supply
Voltage
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NCP302155
Theory of Operation
The NCP302155 is an integrated driver and MOSFET
module designed for use in a synchronous buck converter
topology. The NCP302155 supports numerous application
control definitions including ZCD (Zero Current Detect)
and alternately PWM Tristate control. A PWM input signal
is required to control the drive signals to the high−side and
low−side integrated MOSFETs.
Low−Side Driver
The low−side driver drives an internal,
ground−referenced low−R
(on) N−Channel MOSFET.
DS
The voltage supply for the low−side driver is internally
connected to the VCCD and PGND pins.
High−Side Driver
The high−side driver drives an internal, floating
low−R
(on) N−channel MOSFET. The gate voltage for the
DS
high side driver is developed by a bootstrap circuit
referenced to Switch Node (VSW and PHASE) pins.
The bootstrap circuit is comprised of the integrated diode
and an external bootstrap capacitor and resistor. When the
NCP302155 is starting up, the VSW pin is at ground,
allowing the bootstrap capacitor to charge up to VCCD
through the bootstrap diode (See Figure 1). When the PWM
input is driven high, the high−side driver turns on the
high−side MOSFET using the stored charge of the bootstrap
capacitor. As the high−side MOSFET turns on, the voltage
at the VSW and PHASE pins rises. When the high−side
MOSFET is fully turned on, the switch node settles to VIN
and the BST pin settles to VIN + VCCD (excluding parasitic
ringing).
Bootstrap Circuit
The bootstrap circuit relies on an external charge storage
capacitor (C
) and an integrated diode to provide current
BST
to the HS Driver. A multi−layer ceramic capacitor (MLCC)
with a value greater than 100 nF should be used as the
bootstrap capacitor. An optional 1 to 4 W resistor in series
with the bootstrap capacitor decreases the VSW overshoot.
Power Supply Decoupling
The NCP302155 sources relatively large currents into the
MOSFET gates. In order to maintain a constant and stable
supply voltage (VCCD) a low−ESR capacitor should be
placed near the power and ground pins. A multi−layer
ceramic capacitor (MLCC) between 1 mF and 4.7 mF is
typically used.
A separate supply pin (VCC) is used to power the analog
and digital circuits within the driver. A 1 mF ceramic
capacitor should be placed on this pin in close proximity to
the NCP302155. It is good practice to separate the VCC and
VCCD decoupling capacitors with a resistor (10 W typical)
to avoid coupling driver noise to the analog and digital
circuits that control the driver function (See Figure 1).
Safety Timer and Overlap Protection Circuit
It is important to avoid cross−conduction of the two
MOSFETS which could result in a decrease in the power
conversion efficiency or damage to the device.
The NCP302155 prevents cross−conduction by
monitoring the status of the MOSFETs and applying the
appropriate amount of non−overlap (NOL) time (the time
between the turn−off of one MOSFET and the turn−on of the
other MOSFET). When the PWM input pin is driven high,
the gate of the low−side MOSFET (LSGATE) goes low after
a propagation delay (tpdlGL). The time it takes for the
low−side MOSFET to turn off is dependent on the total
charge on the low−side MOSFET gate.
The NCP302155 monitors the gate voltage of both
MOSFETs and the switch node voltage to determine the
conduction status of the MOSFETs. Once the low−side
MOSFET is turned off an internal timer delays (tpdhGH) the
turn−on of the high−side MOSFET. When the PWM input
pin goes low, the gate of the high−side MOSFET (HSGATE)
goes low after the propagation delay (tpdlGH). The time to
turn off the high−side MOSFET (tfGH) is dependent on the
total gate charge of the high−side MOSFET. A timer is
triggered once the high−side MOSFET stops conducting, to
delay (tpdhGL) the turn−on of the low−side MOSFET.
Zero Current Detect
The Zero Current Detect PWM (ZCD_PWM) mode is
enabled when SMOD# is high (see tables 6 and 8).
With PWM set to > VPWM_HI, GL goes low and GH
goes high after the non−overlap delay. When PWM is driven
to < VPWM_HI and to > VPWM_LO, GL goes high after
the non−overlap delay, and stays high for the duration of the
ZCD blanking timer (T
ZCD_BLANK
) and an 80 ns de−bounce
timer. Once this timer expires, VSW is monitored for zero
current detection, and GL is pulled low once zero current is
detected. The threshold on VSW to determine zero current
undergoes an auto−calibration cycle every time DISB# is
brought from low to high. This auto−calibration cycle
typically takes 25 ms to complete.
PWM Input
The PWM Input pin is a tri−state input used to control the
HS MOSFET ON/OFF state. It also determines the state of
the LS MOSFET. See Table 6 for logic operation. The PWM
in some cases must operate with frequency programming
resistances to ground. These resistances can range from
10 kW to 300 kW depending on the application. When
SMOD# is set to > VSMOD#_HI or to < VSMOD#_LO, the
input impedance to the PWM input is very high in order to
avoid interferences with controllers that must use
programming resistances on the PWM pin.
If SMOD# is set to < VSMOD#_HI and > VSMOD#_LO
(Mid−State), the PWM pin undriven default voltage is set to
Mid−State with internal divider resistances.
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NCP302155
Disable Input (DISB#)
The DISB# pin is used to disable the GH to the High−Side
FET to prevent power transfer. The pin has a pull−down
resistance to force a disabled state when it is left
unconnected. DISB# can be driven from the output of a logic
device or set high with a pull−up resistance to VCC.
Table 7. Table 2. UVLO/DISB# LOGIC TABLE
UVLO DISB# Driver State
L X Disabled (GH = GL = 0)
H L Disabled (GH = GL = 0)
H H Enabled (See Table 1)
H Open Disabled (GH = GL = 0)
Thermal Warning/Thermal Shutdown Output
The THWN pin is an open drain output. When the
temperature of the driver exceeds T
, the THWN pin is
THWN
pulled low indicating a thermal warning. At this point, the
part continues to function normally. When the temperature
drops T
THWN_HYS
the driver temperature exceeds T
below T
, the THWN pin goes high. If
THWN
, the part enters
THDN
thermal shutdown and turns off both MOSFETs. Once the
temperature falls T
THDN_HYS
below T
, the part resumes
THDN
normal operation.
VCC Undervoltage Lockout
The VCC pin is monitored by an Undervoltage Lockout
Circuit (UVLO). VCC voltage above the rising threshold
enables the NCP302155.
enables the low side synchronous MOSFET to operate
independently of the internal ZCD function. When the
SMOD# pin is set low during the PWM cycle it disables the
low side MOSFET to allow discontinuous mode operation.
The NCP302155 has the capability of internally
connecting a resistor divider to the PWM pin. To engage this
mode, SMOD# needs to be placed into mid−state. While in
SMOD# mid−state, the IC logic is equivalent to SMOD#
being in the high state.
Skip Mode Input (SMOD#)
The SMOD# tri−state input pin has an internal pull−up
resistance to VCC. When driven high, the SMOD# pin
NOTE: If the Zero Current Detect circuit detects zero current after the ZCD Wait timer period, the GL is driven low by
the Zero Current Detect signal.
If the Zero Current Detect circuit detects zero current before the ZCD Wait timer period expires, the Zero Current
detect signal is ignored and the GL is driven low at the end of the ZCD Wait timer period.
NOTE: If the SMOD# input is driven low at any time after the GL has been driven high, the SMOD# Falling edge
triggers the GL to go low.
If the SMOD# input is driven low while the GH is high, the SMOD# input is ignored.
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10
NCP302155
SMOD#
triggered
Inductor
Current
PWM
GH
GL
SMOD#
Figure 15. SMOD# Timing Diagram
NOTE: If the SMOD# input is driven low at any time after the GL has been driven high, the SMOD# Falling edge
triggers the GL to go low.
If the SMOD# input is driven low while the GH is high, the SMOD# input is ignored.
For Use with Controllers with 3−State PWM and No
Zero Current Detection Capability:
Table 8. LOGIC TABLE − 3−STATE PWM CONTROLLERS WITH NO ZCD
PWM SMOD# GH (not a pin) GL
H H ON OFF
M H OFF ZCD
L H OFF ON
This section describes operation with controllers that are
capable of 3 states in their PWM output and relies on the
NCP302155 to conduct zero current detection during
discontinuous conduction mode (DCM).
The SMOD# pin needs to either be set to 5 V or left
disconnected. The NCP302155 has an internal pull−up
resistor that connects to VCC that sets SMOD# to the logic
high state if this pin is disconnected.
To operate the buck converter in continuous conduction
mode (CCM), PWM needs to switch between the logic high
and low states. To enter into DCM, PWM needs to be
switched to the mid−state.
Whenever PWM transitions to mid−state, GH turns off
and GL turns on. GL stays on for the duration of the
de−bounce timer and ZCD blanking timers. Once these
timers expire, the NCP302155 monitors the SW voltage and
turns GL off when SW exceeds the ZCD threshold voltage.
By turning off the LS FET, the body diode of the LS FET
allows any positive current to go to zero but prevents
negative current from conducting.
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NCP302155
Figure 16. Timing Diagram − 3−state PWM Controller, No ZCD
FOR USE WITH CONTROLLERS WITH 3−STATE
PWM CONTROLLERS DETECTION CAPABILITY:
Table 9. LOGIC TABLE − 3−STATE PWM CONTROLLERS WITH ZCD
PWM SMOD# GH (not a pin) GL
H L ON OFF
M L OFF OFF
L L OFF ON
This section describes operation with controllers that are
capable of 3 PWM output levels and have zero current
detection during discontinuous conduction mode (DCM).
The SMOD# pin needs to be pulled low (below
V
SMOD#_LO
).
To operate the buck converter in continuous conduction
and low states. During DCM, the controller is responsible
for detecting when zero current has occurred, and then
notifying the NCP302155 to turn off the LS FET. When the
controller detects zero current, it needs to set PWM to
mid−state, which causes the NCP302155 to pull both GH
and GL to their off states without delay.
mode (CCM), PWM needs to switch between the logic high
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NCP302155
SMOD# 0 V
IL 0 A
PWM
GH
GL
SMOD# = Low
Controller detects zero current →
Sets
PWM to mid−state.
PWM in mid−state pulls GL
low.
Figure 17. Timing Diagram − 3−state PWM Controller, with ZCD
Figure 18. Top Copper Layer
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NCP302155
Figure 19. Bottom Copper Layer
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14
NCP302155
RECOMMENDED PCB FOOTPRINT
(Option 1)
LAND PATTERN
RECOMMENDATION
RECOMMENDED MOUNTING FOOTPRINT
For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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15
NCP302155
RECOMMENDED PCB FOOTPRINT
(Option 2)
LAND PATTERN
RECOMMENDATION
RECOMMENDED MOUNTING FOOTPRINT
For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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16
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SCALE 2.5:1
PQFN31 5X5, 0.5P
CASE 483BR
ISSUE A
DATE 24 APR 2020
GENERIC
MARKING DIAGRAM*
XXXXXXXX
XXXXXXXX
AWLYYWWG
G
DOCUMENT NUMBER:
DESCRIPTION:
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
98AON13680G
PQFN31 5X5, 0.5P
XXXX = Specific Device Code
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
PAGE 1 OF 1
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