The NCP139 is a 1 A VLDO equipped with NMOS pass transistor
and a separate bias supply voltage (V
stable, accurate output voltage with low noise suitable for space
constrained, noise sensitive applications. In order to optimize
performance for battery operated portable applications, the NCP139
features low I
consumption. The WLCSP6 1.2 mm x 0.8 mm Chip
Q
Scale package is optimized for use in space constrained applications.
OUT
to 5.5 V
Features
• Input Voltage Range: V
• Bias Voltage Range: 3.0 V to 5.5 V
• Adjustable and Fixed Voltage Version Available
• Output Voltage Range: 0.4 V to 1.8 V (Fixed)
Output Voltage Range: 0.5 V to 3.0 V (Adjustable)
• ±1% Accuracy over Temperature, 0.5% V
• Ultra−Low Dropout: Typ. 50 mV at 1 A
• Very Low Bias Input Current of Typ. 35 mA
• Very Low Bias Input Current in Disable Mode: Typ. 0.5 mA
• Logic Level Enable Input for ON/OFF Control
• Output Active Discharge Option Available
• Stable with a 10 mF Ceramic Capacitor
• Available in WLCSP6 − 1.2 mm x 0.8 mm, 0.4 mm pitch Package
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
• Battery−powered Equipment
• Smartphones, Tablets
• Cameras, DVRs, STB and Camcorders
). The device provides very
BIAS
@ 25°C
OUT
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MARKING
DIAGRAM
WLCSP6, 1.2x0.8
CASE 567MV
XX = Specific Device Code
M= Month Code
XXM
PIN CONNECTIONS
12
A
VOUTVIN
B
SNS/FB
C
GND
Top View
EN
VBIAS
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 7 of this data sheet.
*Active output discharge function is present only in NCP139A option devices.
+
−
THERMAL
LIMIT
DISCHARGE
150 W
*Active
Figure 2. Simplified Schematic Block Diagram − Adjustable Version
CURRENT
LIMIT
OUT
FB
OUT
EN
BIAS
GND
ENABLE
BLOCK
UVLO
VOLTAGE
REFERENCE
*Active output discharge function is present only in NCP139A option devices.
+
−
THERMAL
LIMIT
DISCHARGE
150 W
*Active
Figure 3. Simplified Schematic Block Diagram − Fixed Version
SNS
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2
Page 3
NCP139
PIN FUNCTION DESCRIPTION
Pin No.
WLCSP6
A1VOUTRegulated Output Voltage pin
A2VINInput Voltage Supply pin
B1
(ADJ devices)
B1
(Fix Volt devices)
B2ENEnable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator
C1GNDGround pin
C2VBIASBias voltage supply for internal control circuits. This pin is monitored by internal Under-Voltage
ABSOLUTE MAXIMUM RATINGS
Input Voltage (Note 1)V
Output VoltageV
Chip Enable, Bias, FB and SNS InputV
Output Short Circuit Durationt
Maximum Junction TemperatureT
Storage TemperatureT
ESD Capability, Human Body Model (Note 2)ESD
ESD Capability, Machine Model (Note 2)ESD
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection (except OUT pin) and is tested by the following methods:
ESD Human Body Model tested per EIA/JESD22−A114
ESD Machine Model tested per EIA/JESD22−A115
Latchup Current Maximum Rating tested per JEDEC standard: JESD78.
Pin NameDescription
FBAdjustable Regulator Feedback Input. Connect to output voltage resistor divider central node.
SNSOutput voltage Sensing Input. Connect to Output on the PCB to output the voltage
corresponding to the part version.
into shutdown mode.
Lockout Circuit.
RatingSymbolValueUnit
IN
OUT
EN, VBIAS, VFB
SC
J
STG
HBM
MM
, V
SNS
−0.3 to 6V
−0.3 to (VIN+0.3) ≤ 6V
−0.3 to 6V
unlimiteds
150°C
−55 to 150°C
2000V
200V
THERMAL CHARACTERISTICS
RatingSymbolValueUnit
Thermal Characteristics, WLCSP6 1.2 mm x 0.8 mm
Thermal Resistance, Junction−to−Air (Note 3)
R
q
JA
69°C/W
3. This junction−to−ambient thermal resistance under natural convection was derived by thermal simulations based on the JEDEC JESD51
series standards methodology. Only a single device mounted at the center of a high_K (2s2p) 80 mm x 80 mm multilayer board with 1−ounce
internal planes and 2−ounce copper on top and bottom. Top copper layer has a dedicated 1.6 sqmm copper area.
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3
Page 4
NCP139
ELECTRICAL CHARACTERISTICS −40°C ≤ T
0.3 V, I
Min/Max values are for −40°C ≤ T
Operating Input Voltage
Range
Operating Bias Voltage
Range
Undervoltage Lock−outV
Reference Voltage
(Adj devices)
Output Voltage AccuracyV
Output Voltage Accuracy −40°C ≤ TJ ≤ 85°C, V
VIN Line RegulationV
V
BIAS
Load RegulationI
VIN Dropout VoltageI
V
BIAS
Output Current Limit
FB/SNS Pin Operating
Current
Bias Pin Quiescent
Current
Bias Pin Disable CurrentVEN ≤ 0.4 VI
Vinput Pin Disable
Current
EN Pin Threshold Voltage
EN Pull Down CurrentVEN = 5.5 VI
Turn−On TimeFrom assertion of V
Power Supply Rejection
Ratio
(Adj devices)
Output Noise Voltage
(Adj devices)
= 1 mA, VEN = 1 V, CIN = 10 mF, C
OUT
≤ 85°C unless otherwise noted. (Notes 4, 5)
J
Parameter
Rising
BIAS
Hysteresis
NCP139Axxxx05ADJT2G, TJ = +25°C
NCP139Axxxx06ADJT2G, TJ = +25°C0.600
V
OUT(NOM)
1.6 V), whichever is greater < V
1 mA < I
OUT
OUT(NOM)
Line Regulation3.0 V or (V
greater < V
= 1 mA to 1.0 ALoad
OUT
= 1.0 A (Notes 6, 7)V
OUT
Dropout VoltageI
= 1.0 A, VIN = V
OUT
V
= 90% V
OUT
V
= 90% V
OUT
V
= 3.0 V, I
BIAS
VEN ≤ 0.4 VI
EN Input Voltage “H”V
EN Input Voltage “L”V
98% V
OUT(NOM)
= 10 mF
C
OUT
VIN to V
OUT
VIN≥ V
OUT
= 10 mF
C
OUT
V
to V
BIAS
V
IN≥ V
OUT
= 10 mF
C
OUT
VIN = V
OUT
V
OUT(NOM)
Test ConditionsSymbolMinTypMaxUnit
+ 1.0 V, 3.0 V or (V
< 1.0 A
+ 0.3 V ≤ V
OUT(NOM)
< 5.5 V
BIAS
OUT(NOM)
OUT(NOM)
OUT
. V
, f = 1 kHz, I
+0.5 V, V
, f = 1 kHz, I
OUT
+0.5 V, V
+0.5 V, f = 10 Hz to 100 kHz,
= 1.0 V, C
≤ 85°C; V
J
= 10 mF, C
OUT
OUT(NOM)
OUT(NOM)
≤ 5.0 VLine
IN
= 3.0 V or (V
BIAS
= 1 mF, unless otherwise noted. Typical values are at TJ = +25°C.
BIAS
+ 0.3 V ≤ V
< 5.5 V,
BIAS
≤
IN
+
+ 1.6 V), whichever is
(Notes 6, 8, 9)V
BIAS
, −30°C ≤ TJ ≤ 85°CI
= 0 mAI
to V
EN
OUT(NOM)
OUT(NOM)
OUT(NOM)
OUT
OUT
= 10 mA,
OUT
OUT
= 10 mF
=
= 1.0 V,
= 1.0 V,
= 10 mA,
= 1.0 V,
+ 1.6 V), whichever is greater, VIN = V
OUT
V
V
IN
BIAS
V
+
OUT
V
DO
(V
+
OUT
1.60) ≥ 3.0
OUT(NOM)
5.5V
5.5V
UVLO1.6
0.2
V
REF
OUT
V
OUT
Reg
Line
Reg
Reg
DO
DO
I
CL
CL
IFB, I
SNS
BIASQ
BIAS(DIS)
VIN(DIS)
EN(H)
EN(L)
EN
t
ON
−1.0+1.0%
150020002600mA
155020002600mA
0.9
0.500
±0.5%
0.01%/V
0.01%/V
2.0
5080mV
1.051.5V
0.10.5
3550
0.51
0.51
0.4
0.31
160
PSRR(VIN)70dB
PSRR(V
)85dB
BIAS
V
N
35 x
V
OUT/VREF
mV
+
V
V
mV
mA
mA
mA
mA
V
mA
ms
RMS
4. Performance guaranteed over the indicated operating temperature range by design and/or characterization. Production tested at TA =
25°C. Low duty cycle pulse techniques are used during the testing to maintain the junction temperature as close to ambient as possible.
= V
5. Adjustable devices tested at V
6. Dropout voltage is characterized when V
7. For adjustable devices, V
8. For adjustable devices, V
9. For Fixed Voltages below 1.8 V, V
OUT
dropout voltage tested at V
IN
dropout voltage tested at V
BIAS
unless otherwise noted; external resistor tolerance is not taken into account.
REF
falls 3% below V
OUT
dropout voltage does not apply due to a minimum Bias operating voltage of 3.0 V.
BIAS
OUT(NOM)
OUT(NOM)
OUT(NOM)
= 2 x V
= 3 x V
.
.
REF
due to a minimum Bias operating voltage of 3.0 V.
REF
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4
Page 5
NCP139
ELECTRICAL CHARACTERISTICS −40°C ≤ T
0.3 V, I
Min/Max values are for −40°C ≤ T
= 1 mA, VEN = 1 V, CIN = 10 mF, C
OUT
≤ 85°C unless otherwise noted. (Notes 4, 5)
J
= 10 mF, C
OUT
≤ 85°C; V
J
= 3.0 V or (V
BIAS
= 1 mF, unless otherwise noted. Typical values are at TJ = +25°C.
BIAS
+ 1.6 V), whichever is greater, VIN = V
OUT
OUT(NOM)
+
ParameterUnitMaxTypMinSymbolTest Conditions
Power Supply Rejection
Ratio (Fixed Voltage
devices)
Output Noise Voltage
(Fixed Voltage devices)
Thermal Shutdown
Threshold
Output Discharge
Pull−Down
V
to V
IN
V
OUT
V
BIAS
V
OUT
C
OUT
V
= V
IN
V
OUT(NOM)
, f = 1 kHz, I
OUT
+0.5 V, V
to V
+0.5 V, V
= 10 mF
OUT(NOM)
, f = 1 kHz, I
OUT
OUT(NOM)
+0.5 V, f = 10 Hz to 100 kHz,
OUT
= 1.8 V, C
OUT
= 1.8 V, C
= 1.8 V, V
OUT
OUT
= 10 mF
= 10 mA, VIN ≥
= 10 mF
OUT
= 10 mA, VIN ≥
= 4.0 V,
BIAS
PSRR(VIN)75dB
PSRR(V
)85dB
BIAS
V
N
48
Temperature increasing160
Temperature decreasing140
VEN ≤ 0.4 V, V
only
= 0.5 V, NCP139A options
OUT
R
DISCH
150
mVRMS
°C
W
4. Performance guaranteed over the indicated operating temperature range by design and/or characterization. Production tested at TA =
25°C. Low duty cycle pulse techniques are used during the testing to maintain the junction temperature as close to ambient as possible.
= V
5. Adjustable devices tested at V
6. Dropout voltage is characterized when V
7. For adjustable devices, V
8. For adjustable devices, V
9. For Fixed Voltages below 1.8 V, V
OUT
dropout voltage tested at V
IN
dropout voltage tested at V
BIAS
unless otherwise noted; external resistor tolerance is not taken into account.
REF
falls 3% below V
OUT
dropout voltage does not apply due to a minimum Bias operating voltage of 3.0 V.
BIAS
OUT(NOM)
OUT(NOM)
OUT(NOM)
= 2 x V
= 3 x V
.
.
REF
due to a minimum Bias operating voltage of 3.0 V.
REF
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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5
Page 6
VBAT
NCP139
APPLICATIONS INFORMATION
NCP139
Switch−mode DC/DC
Processor
I/O
I/O
= 1.5 V
V
OUT
IN
ENFB
GND
LX
Figure 4. Typical Application: Low−Voltage DC/DC Post−Regulator with ON/OFF Functionality
The NCP139 dual−rail very low dropout voltage regulator
is using NMOS pass transistor for output voltage regulation
from V
circuitry is powered from the V
voltage. All the low current internal control
IN
voltage.
BIAS
The use of an NMOS pass transistor offers several
advantages in applications. Unlike PMOS topology devices,
the output capacitor has reduced impact on loop stability.
Vin to Vout operating voltage difference can be very low
compared with standard PMOS regulators in very low Vin
applications.
The NCP139 offers smooth monotonic start-up. The
controlled voltage rising limits the inrush current.
The Enable (EN) input is equipped with internal
hysteresis. NCP139 Voltage linear regulator Fixed and
Adjustable version is available.
Output Voltage Adjust
The required output voltage of Adjustable devices can be
adjusted from V
to 3.0 V using two external resistors.
REF
Typical application schematics is shown in Figure 5.
V
BIAS
C
BIAS
V
IN
C
IN
V
EN
V
OUT
NCP139 ADJ
BIAS
IN
EN
GND
+ V
REF
OUT
R1
FB
R2
ǒ1 ) R1ńR2
V
OUT
μF
10
Ǔ
Figure 5. Typical Application Schematics
It is recommended to keep the total serial resistance of
resistors (R1 + R2) no greater than 100 kW.
1.5 V
EN
BIAS
IN
GND
OUT
R1
FB
R2
To other circuits
1.0 V
LOAD
Dropout Voltage
Because of two power supply inputs VIN and V
one V
regulator output, there are two Dropout voltages
OUT
BIAS
specified.
The first, the V
difference (V
IN
Dropout voltage is the voltage
IN
– V
OUT
) when V
starts to decrease by
OUT
percent specified in the Electrical Characteristics table.
is high enough; specific value is published in the
V
BIAS
Electrical Characteristics table.
The second, V
difference (V
BIAS
joined together and V
Input and Output Capacitors
dropout voltage is the voltage
BIAS
– V
) when VIN and V
OUT
starts to decrease.
OUT
BIAS
pins are
The device is designed to be stable for ceramic output
capacitors with Effective capacitance in the range from
10 mF to 22 mF. The device is also stable with multiple
capacitors in parallel, having the total effective capacitance
in the specified range.
In applications where no low input supplies impedance
available (PCB inductance in V
example), the recommended C
IN
and/or V
IN
= 1 mF and C
BIAS
BIAS
inputs as
= 0.1 mF
or greater. Ceramic capacitors are recommended. For the
best performance all the capacitors should be connected to
the NCP139 respective pins directly in the device PCB
copper layer, not through vias having not negligible
impedance.
When using small ceramic capacitor, their capacitance is
not constant but varies with applied DC biasing voltage,
temperature and tolerance. The effective capacitance can be
much lower than their nominal capacitance value, most
importantly in negative temperatures and higher LDO
output voltages. That is why the recommended Output
capacitor capacitance value is specified as Effective value in
the specific application conditions.
and
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6
Page 7
NCP139
Enable Operation
The enable pin will turn the regulator on or off. The
threshold limits are covered in the electrical characteristics
table in this data sheet. If the enable function is not to be used
then the pin should be connected to V
IN
or V
BIAS
.
Thermal Protection
Internal thermal shutdown (TSD) circuitry is provided to
protect the integrated circuit in the event that the maximum
junction temperature is exceeded. When TSD activated , the
regulator output turns off. When cooling down under the low
temperature threshold, device output is activated again. This
Current Limitation
The internal Current Limitation circuitry allows the
device to supply the full 1 A nominal current and short time
current peaks up to 1.3 A but protects the device against
Current Overload or Short.
TSD feature is provided to prevent failures from accidental
overheating.
Activation of the thermal protection circuit indicates
excessive power dissipation or inadequate heatsinking. For
reliable operation, junction temperature should be limited to
+85°C maximum.
ORDERING INFORMATION
Nominal
Output
Device
NCP139AFCT05ADJT2GADJ0.5 VAYOutput Active Discharge
NCP139AFCTC05ADJT2GADJ0.5 VAYOutput Active Discharge,
NCP139AFCT06ADJT2GADJ0.6 VA6Output Active Discharge
NCP139AFCTC06ADJT2GADJ0.6 VA6Output Active Discharge,
NCP139AFCT100T2G1.00 V−AKOutput Active Discharge
NCP139AFCT105T2G1.05 V−ACOutput Active Discharge
NCP139AFCT110T2G1.10 V−AJOutput Active Discharge
NCP139AFCTC110T2G1.10 V−AJOutput Active Discharge,
NCP139AFCT120T2G1.20 V−ALOutput Active Discharge
NCP139AFCT180T2G1.80 V−AZOutput Active Discharge
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Spe-
cifications Brochure, BRD8011/D.
To order other package and voltage variants, please contact your ON Semiconductor sales representative
Voltage
Reference
Voltage
MarkingOptionPackageShipping
Back Side Coating
Back Side Coating
WLCSP6
(Pb−Free)
Back Side Coating
5000 / Tape & Reel
†
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7
Page 8
WLCSP6, 1.20x0.80
8
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SCALE 4:1
CASE 567MV
ISSUE B
DATE 05 JUN 201
REFERENCE
2X
2X
NOTE 3
0.03
C
PIN A1
6X
A0.05BC
0.05 C
0.05 C
0.05 C
0.05 C
A1
b
BOTTOM VIEW
E
TOP VIEW
SIDE VIEW
e
C
B
A
12
A
A2
B
D
A
C
e
SEATING
PLANE
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
MILLIMETERS
DIMAMINMAX
A1
A20.23 REF
b0.240.30
D1.20 BSC
E
e0.40 BSC
0.33
−−−
0.040.08
0.80 BSC
GENERIC
MARKING DIAGRAM*
XXM
XX = Specific Device Code
M= Month Code
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
RECOMMENDED
SOLDERING FOOTPRINT*
PACKAGE
A1
OUTLINE
0.40
PITCH
PITCH
0.40
DIMENSIONS: MILLIMETERS
6X
0.20
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
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ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
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