ON Semiconductor NCP1239FDR2G, NCP1239FDR2, NCP1239VDR2, NCP1239VDR2G Reference Manual

© Semiconductor Components Industries, LLC, 2005

October, 2005 − Rev. 5

1 Publication Order Number

NCP1239/D

NCP1239

Low−Standby High
Performance PWM Controller

Housed in SO−16 the NCP1239 represents a major leap toward
ultra−compact Switch Mode Power Supplies specifically tailored for
medium to high power off−line applications, e.g. notebook adapters.
The NCP1239 offers everything needed to build a rugged and efficient
power supply, including a dedicated event management to drive a
Power Factor Correction (PFC) front−end circuitry. The circuit
disables the front−end PFC stage while still in fault or standby
conditions by interrupting the PFC controller powering for improved
no−load consumption figures. As soon as normal operating mode
recovers, the NCP1239 feeds back the PFC that wakes−up.

When power demand is low, the IC automatically enters the
so−called skip−cycle mode and provides excellent efficiency at light
loads. Because this occurs at a user adjustable low peak current, no
acoustic noise takes place.

Features

• Current−Mode Operation with Internal Ramp Compensation

• Internal High−Voltage Current Source for loss−less Startup

• Adjustable Skip−Cycle Capability

• Selectable Soft−Start Period

• Internal Frequency Dithering for Improved EMI Signature

• Go−to−Standby Signal for PFC Front−Stage

• Large V

CC

Operation from 12.2 V to 36 V

• 500 mV Overcurrent Limit

• 500 mA/−800 mA Peak Current Capability

• 5 V/10 mA Pinned−out Reference Voltage

• Adjustable Switching Frequency up to 250 kHz.

• Overload Protection Independent of the Auxiliary V

CC

• Adjustable Over Power Compensation (NCP1239F)

• Programmable Maximum Duty Cycle (NCP1239V)

• Pb−Free Packages are A vailable*

Typical Applications

• High Power AC/DC Adapters for Notebooks etc.

• Offline Battery Chargers

• Telecom and PC Power Supplies

• Flyback Applications (NCP1239F) and Forward Applications

(NCP1239V)

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.

NCP1239xD = Device Code
x = F or V
A = Assembly Location
WL = Wafer Lot
Y = Year
WW = Work Week
G = Pb−Free Package

MARKING DIAGRAM

16

SO−16

FD or VD SUFFIX

CASE 751B

NCP1239xDG

AWLYWW

1

1

16

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PIN CONNECTIONS

Over Power
Limit

FB

1

16

CSSkip Adjust

GNDSS/Timer

DrvBrown−out

V

CC

Rt

NCFault Detect

NCREF5V

HVGTS

Max Duty−
Cycle

FB

1

16

CSSkip Adjust

GNDSS/Timer

DrvBrown−out

V

CC

Rt

NCFault Detect

NCREF5V

HVGTS

NCP1239F

NCP1239V

See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.

ORDERING INFORMATION

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2

Figure 1. NCP1239F Typical Application Example

Cbulk

Vbulk

+

to PFC_V

CC

BO

1 16
2
3
4

15
14
13

NCP1239F

OVP

+

GND

V

out

Rbo1

GND

Rcomp

Cbo

5 12
6
7
8

11
10

9

Rramp

V

CC

REF5V

+

REF5V (5V/10mA)

Css

Rbo2

Rt

NTC

Thermistor

Figure 2. NCP1239V Typical Application Example

Cbulk

Vbulk

+

to PFC_V

CC

BO

1 16
2
3
4

15
14
13

NCP1239V

OVP

V

out

Rbo1

GND

Rdmax

Cbo

5 12
6
7
8

11
10

9

Rramp

V

CC

REF5V

+

REF5V (5V/10mA)

Css

Rbo2

Rt

NTC

Thermistor

D3

D4

+

GND

L2

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MAXIMUM RATINGS

Rating Symbol Value Unit

Power Supply Voltage V

CC

36 V
Pins 1 to 10 (except Vref Pin) Maximum Voltage −0.3, +10 V
Maximum Voltage on Pin 16 (HV) 500 V
Thermal Resistance, Junction−to−Air, SOIC Version

R



JA

145 °C/W

Maximum Junction Temperature TJ

MAX

150 °C
Storage Temperature Range −60 to +150 °C
ESD Capability, HBM Model (All Pins except HV) 2 kV
ESD Capability Machine Model (All Pins except VCC)

Machine Model (VCC Pin)

200

160

V

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.

ELECTRICAL CHARACTERISTICS (For typical values T

J

= 25°C, for min/max values TJ = 0°C to +125°C, V

pin16

= 48 V,

VCC = 20 V unless otherwise noted.)

Symbol Rating Pin Min Typ Max Unit

Supply Section

V

CCON

Turn−on Threshold Level, VCC Going up 13 15.5 16.4 17.5 V

V

CCOFF

Minimum Operating Voltage after Turn−on 13 10.5 11.2 12.2 V

HYST1 Difference (V

CCON

− V

CCOFF

) 13 4.5 5.1 − V

V

CCLATCH

VCC Decreasing Level at which the Latch−off Phase ends 13 6.5 6.9 7.2 V

V

CCRESET

VCC Level at which the Internal Logic gets reset 13 − 4.0 − V

I

CC1

Internal IC Consumption, no output load on Pin 12 (@I

Rt

= 20 A)

NCP1239F
NCP1239V

13

−

−

2.1

2.6

3.0

4.0

mA

I

CC2a

Internal IC Consumption, 1 nF output load on Pin 12

NCP1239F (65 kHz)

NCP1239V (118 kHz)

13

−

−

3.1

4.2

3.8

6.5

mA

I

CC2b

Internal IC Consumption, 1 nF output load on Pin 12

NCP1239F (100 kHz)
NCP1239V (182 kHz)

13

−

−

3.9

5.5

5.0

8.5

mA

I

CC2c

Internal IC Consumption, 1 nF output load on Pin 12

NCP1239F (130 kHz)
NCP1239V (236 kHz)

13

−

−

4.6

6.7

5.9

9.6

mA

I

CC3

Internal IC Consumption, latchoff phase

(NCP1239F and NCP1239V)

13 −

0.40 0.75

mA

Internal Startup Current Source

I

C1_hv

High−Voltage Current Source (sunk by Pin 16), VCC = 10 V 16 2.0 4.0 5.3 mA

I

C1_VCC

Startup Charge Current flowing out of the VCC Pin, VCC=10 V 13 1.8 3.6 4.5 mA

I

C2

High−Voltage Current Source, VCC = 0 16 − 4.2 − mA

5 V Reference Voltage (REF5V)

REF5V Reference Voltage

@ No load on Pin 2
@ I

pin2

= 5 mA

2

4.7

4.6

5.0

4.9

5.2

5.1

V

Iref Current Capability 2 5.0 10 − mA

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4

ELECTRICAL CHARACTERISTICS (For typical values T

J

= 25°C, for min/max values TJ = 0°C to +125°C, V

pin16

= 48 V,

VCC = 20 V unless otherwise noted.)

Symbol UnitMaxTypMinPinRating

Drive Output

Vcl Output Voltage Positive Clamp 12 11.5 13.6 16 V

T

rise

Output Voltage Rise−Time @ CL = 1 nF, 10−90% of output signal 12 − 40 − ns

T

fall

Output Voltage Fall−Time @ CL = 1 nF, 10−90% of output signal 12 − 25 − ns

V

source

High State Voltage Drop @ I

pin12

= 3 mA and VCC = 12 V 12 − 2.5 3.3 V

I

source

Source Current Capability (@ V

pin12

= 0 V) 12 − 500 − mA

R

OL

Sink Resistance @ V

pin12

=1 V 12 − 3.8 7.5



I

sink

Sink Current Capability (@ V

pin12

= 10 V) 12 − 800 − mA

Oscillator

fsw Recommended Switching Frequency Range 12 25 − 250 kHz

Vosc

Pin 4 Voltage @ Rt = 100 k

4 − 1.6 − V

Kosc Product (Switching Frequency times the Rt Pin 4 resistance) (Note 1)

@ 65 kHz and 130 kHz (NCP1239F)
@ 118 kHz and 236 kHz (NCP1239V)

6050

11000

6500

11800

6950

12600

kHz*k

fsw

Internal Modulation Swing, in percentage of fsw − ±3.5 − %

Dmax Maximum Duty−Cycle 75.5 80.0 83.0 %

Current Limitation

I

Limit

Maximum Internal Set−Point 10 0.84 0.90 0.95 V

T

DEL_CS

Propagation Delay from V

pin10

> I

Limit

to gate turned off

(Pin 12 loaded by 1 nF)

10 − 130 220 ns

T

LEB−65kHz

Leading Edge Blanking Duration (Pins 9 and 10) @ 65 kHz

(NCP1239F)

9, 10 − 420 − ns

T

LEB−130kHz

Leading Edge Blanking Duration (Pins 9 and 10) @ 130 kHz

(NCP1239F)

9, 10 − 230 − ns

T

LEB−118kHz

Leading Edge Blanking Duration (Pin 10) @ 118 kHz (NCP1239V) 10 − 320 − ns

T

LEB−236kHz

Leading Edge Blanking Duration (Pin 10) @ 236 kHz (NCP1239V) 10 − 170 − ns

Over Power Limit (NCP1239F)

I

ocp

Internal Current Source of the Over Power Limit Pin

@ 1 V on Pin 5 and V

pin9

= 0.5 V

@ 2 V on Pin 5 and V

pin9

= 0.5 V

9

60

120

80

160

100
185

A

V

opl

Over Power Limitation Threshold

@ TJ = 25°C
@ TJ = 0°C to 125°C

9

0.48

0.47

0.50

0.50

0.52

0.52

V

T

DEL_OCP

Propagation Delay from V

pin9

> V

opl

to gate turned off

(Pin 12 loaded by 1 nF)

9 − 130 220 ns

Maximum Duty−Cycle (Dmax) Control (NCP1239V)

I

Dmax

Pin 9 Current Source @ V

pin9

= 1.0 V and V

pin9

= 2.0 V 9 46 55 63

A

D

max

Maximum Duty Cycle @ 118 kHz and V

pin9

= 1.0 V 9 20 24 29 %

K

Dmax

Dmax Coefficient @ 118 kHz and V

pin9

= 1.0 V (Note 2) 9 1.10 1.30 1.53

%/k

1. The nominal switching frequency fsw equals: fsw = K

OSC

/Rt. The implemented jittering makes the switching frequency continuously vary

around this nominal value ($3.5% variation).

2. K

Dmax

is the proportionality coefficient that links the maximum duty−cycle to the Pin 9 resistor: Dmax = K

Dmax*Rpin9

. K

Dmax

is defined in

the “Maximum Duty−Cycle Limitation” section of the operating description.

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ELECTRICAL CHARACTERISTICS (For typical values T

J

= 25°C, for min/max values TJ = 0°C to +125°C, V

pin16

= 48 V,

VCC = 20 V unless otherwise noted.)

Symbol UnitMaxTypMinPinRating

Soft−Start and Timer

I

ch

Soft−Start or Jittering charge current @ V

pin6

= 2.4 V 6 60 95 110

A

I

disch

Jittering Discharge Current @ V

pin6

= 2.4 V 6 77 107 137

A

V

jitter

Jittering Saw−Tooth Lower Threshold 6 1.67 1.80 1.89 V

V

jitter

H Jittering Saw−Tooth Upper Threshold 6 2.85 3.00 3.20 V

V

timer

L Timer Peak Threshold 6 4.0 4.3 4.6 V

I

timerC

Timer Charge Current @ V

pin6

= 3.5 V and Pin 8 open 6 3.9 5.2 6.4

A

I

timerD

Timer Discharge Current @ V

pin6

= 3.5 V and Pin 8 open 6 − 400 −

A

Feedback Section

Rup Internal Pullup Resistor 8 − 20 −

k

Ifb Source Current @ V

pin8

= 0.5 V 8 − 200 −

A

Iratio Pin 8 to current Setpoint division ratio − − 3.0 − −

Internal Ramp Compensation

R

ramp

Internal Resistor 10 − 32 −

k

V

ramp

Internal Saw−Tooth Amplitude 10 − 3.2 − V

Skipping Mode and Standby Management

Rgts Pin 1 output impedance in standby state

(Pin 8 grounded, V

pin6

> 4.5 V) @ VCC = 12.5 V

1 4.0 8.0 18

k

Igts Sink Current Source in Normal Mode

@ V

pin8

= 2 V, Pin 7 open @ V

CC

− V

pin1

=0.7 V

1 0.6 1.0 − mA

FB−skip Default Feedback Level for Skip−Cycle Operation and Standby

Detection

7 380 430 480 mV

FB_stby−out Default Feedback Level to Leave Standby 7 650 740 810 mV

V

stby−out/Vskip

Ratio leave standby Setpoint to skip−cycle Setpoint 1.5 1.7 1.9 −

R

pin7

Internal Pin 7 Impedance 7 − 110 −

k

Pin 7 to Skipping Setpoint ratio − 3.0 − −

Brown−Out Detection

BO

thH

Brown−Out Detection Upper Threshold 5 0.45 0.50 0.55 V

BO

thL

Brown−Out Detection Low Threshold 5 0.20 0.24 0.28 V

BO

hyst

Brown−Out Hysteresis 5 0.20 0.26 0.30 V

Protections

TSD Thermal Shutdown:

Thermal Shutdown Threshold
Hysteresis

140

30

°C

Vfault Fault Detection Threshold 3 2.2 2.4 2.6 V

ORDERING INFORMATION

Device Package Shipping

†

NCP1239FDR2 SOIC−16 2500 / Tape & Reel
NCP1239FDR2G SOIC−16

(Pb−Free)

2500 / Tape & Reel

NCP1239VDR2 SOIC−16 2500 / Tape & Reel
NCP1239VDR2G SOIC−16

(Pb−Free)

2500 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

NCP1239

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6

PIN FUNCTION DESCRIPTION

Pin No. Pin Name Function Pin Description

1 GTS Shuts the PFC down in

standby

The standby detection block changes Pin 1 state in accordance to the mode
(standby or normal mode). Pin1 is designed to drive an external pnp transistor that
connects or disconnects the NCP1239’s VCC to the PFC’s.

2 REF5V A 5V reference voltage This pin helps to internally bias the controller but can also be used to power

surrounding logic gates for any purposes. The typical output current is 10 mA. This
voltage source is disabled during the circuit startup and latched−off phases. A
100 nF filtering capacitor must be placed between Pin 2 and ground.

3 Fault Detect Enables to permanently

shutdown the part

If the Pin 3 voltage exceeds 2.4 V, the circuit is permanently shut down. This pin
can be used to monitor the voltage across a thermistor in order to protect the
application from excessive heating and/or to detect an overvoltage condition.

4 Rt Timing resistor Pin 4 resistor allows a precise frequency programming. The circuit is optimized to

operate between 50 kHz and 150 kHz (NCP1239F) and between 100 kHz and
250 kHz (NCP1239V).

5 Brown−Out Brown−Out This pin receives a portion of the bulk capacitor to authorize operation above a

certain level of mains only. It also serves to elaborate an offset voltage on Pin 9
used for Over Power Compensation.

6 SS/Timer Performs soft−start and

fault timeout

During Power on and fault conditions, the capacitor connected to this pin ensures a
soft−start period. When a fault is detected, this pin is internally brought high by a
current source. If 4.3 V are reached, the fault is confirmed and the circuit enters an
auto−recovery burst mode, otherwise the pin goes back to a lower value and
oscillates to perform frequency jittering.

7 Skip Adjust Adjust skip level By adjusting the skip−cycle level, it is possible to fight against noisy transformers

and modify the standby detection thresholds. Keep Pin 7 open to operate with the
default levels (skip threshold setpoint: 140 mV, normal mode recovery setpoint:

250 mV).
8 FB Feedback signal An opto−coupler collector pulls this pin low to regulate
9 Over Power

Limit

(NCP1239F)

Enables a precise peak

current clamp and then an

accurate Over Power

Detection

This pin delivers a current proportional to V

pin5

, an image of the high voltage rail.
Inserting a resistor between Pin 9 and the current sense resistor, an offset
proportional to the input voltage is built. Such offset compensates the circuit and
power switch propagation delays for an accurate power limitation in the whole input
voltage range.

9 Max Duty−

Cycle

(NCP1239V)

Enables to precisely
clamp the maximum

duty−cycle.

This terminal sources a constant current. Connect a resistor between Pin 9 and
Ground to select the maximum duty−cycle.

10 CS The current sense input This pin receives the primary current information via a sense element. By inserting

a resistor in series with this pin, it becomes possible to introduce ramp
compensation.

11 Ground The IC ground −
12 Drv Drives the MOSFET By offering up to +500 mA/−800 mA peak, this pin lets you drive large Qg

MOSFET’s. It is clamped to 16 V maximum not to exceed the maximum
gate−source voltage of most power MOSFET’s.

13 V

CC

Supplies the controller This pin accepts up to 36 V from an auxiliary winding.
14 NC − Creepage distance.
15 NC − Creepage distance.
16 HV The high−voltage startup This pin connects to the bulk capacitor to generate the startup current.

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7

Figure 3. NCP1239F Internal Circuit Architecture

−
+

7

S

R

Q
Q

Vcc < 4V

450mV

5V

0.5V / 0.25V

Rt

BO

REF5V

SS / timer

PFC_Vcc

Fault
detect

Skip
adjust

Vdd

/ 3

to Skip

20k

0.9V

Oscillator

GND

32k

CS

Drv

Vcc

Vdd

Regul

UVLOs
Latch
Reset

Error flag

HV

Over Power
Limit

Vdd

2.5V

Vdd

2.5V

100k

Fault

Vdd Vdd

Soft−Start
and timer
management

Stby_detect

Error_Flag

Stby

OVL

OVL

Vcc<7V

stdwn

Vstop

PWM Latch

Output
Buffer

BO_out

Jittering
Modulation

“Jittered”
Reference

Jittering
Modulation

CLK

CLK

0.5V

BO_in

Soft−Start
Ipk limit

Soft−Start
Ipk limit

Internal
Thermal
Shutdown

TSD

FB

Divider by 2

+

−

Skip

Skip

FB

Startup Phase

(Vcc<VccOFF)

1mA

Vcc

10k

Vstop

regOUT

Stby_detect

25r

15r

S

R

Q
Q

FB<Vpin1 => Skip high

FB>1.6*Vpin1 =>Stby_detect RESET

pfcOFF

pfcON

UVLO

14V

clamp

pfcON

OUTon

Ramp
Compensation

3.2V

BO_in

75 mA/V x V

pin5

LEB

LEB

+

−

+

16

15

14

13

−

+

3

1

S

R

Q
Q

6

2

+

12

11

10

5

+

S

R

Q
Q

9

+

−

+

−
+

−

+

8

4

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8

Figure 4. NCP1239V Internal Circuit Architecture

−
+

7

S

R

Q
Q

Vcc < 4V

450mV

5V

0.5V / 0.25V

Rt

BO

REF5V

SS / timer

PFC_Vcc

Fault
detect

Skip
adjust

Vdd

/ 3

to Skip

20k

0.9V

Oscillator

GND

32k

CS

Drv

Vcc

Vdd

Regul

UVLOs
Latch
Reset

Error flag

HV

Dmax

Vdd

2.5V

Vdd

2.5V

100k

Fault

Vdd Vdd

Soft−Start
and timer
management

Stby_detect

Error_Flag

Stby

OVL

OVL

Vcc<7V

stdwn

Vstop

PWM Latch

Output
Buffer

BO_out

Jittering
Modulation

“Jittered”
Reference

Jittering
Modulation

CLK

CLK

BO_in

Soft−Start
Ipk limit

Soft−Start
Ipk limit

Internal
Thermal
Shutdown

TSD

FB

Divider by 2

+

−

Skip

Skip

FB

Startup Phase

(Vcc<VccOFF)

1mA

Vcc

10k

Vstop

regOUT

Stby_detect

25r

15r

S

R

Q
Q

FB<Vpin1 => Skip high

FB>1.6*Vpin1 =>Stby_detect RESET

pfcOFF

pfcON

UVLO

14V

clamp

pfcON

OUTon

Ramp
Compensation

3.2V

Idmax

LEB

+

−

+

16

15

14

13

−

+

3

1

S

R

Q
Q

6

2

+

12

11

10

5

+

S

R

Q
Q

9

+

−

−

+

−

+

8

4

OSC

OSC

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9

Figure 5. High Voltage Current Source

vs. Temperature @ V

CC

= 10 V

Figure 6. Startup Current Sourced by V

CC

Pin

vs. Temperature @ V

CC

= 10 V

TEMPERATURE (°C)

100755025−25

I

C1_VCC

(mA)

TEMPERATURE (°C)

125100755025

6.0

I

C1_HV

, (mA)

5.0

−25

0

4.0

3.0

2.0

1.0

0

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5
0

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 7. High Voltage Current Source

vs. Temperature @ V

CC

= 0 V

TEMPERATURE (°C)

125100755025−25

I

C2

(mA)

6.0

0

5.0

4.0

3.0

2.0

1.0

0

Figure 8. High Voltage Pin Leakage Current

vs. Temperature

12

5

TEMPERATURE (°C)

12

5

100755025

0

10

20

30

Pin16 Leakage Current (A)

40

50

60

0

Figure 9. VCC Startup Threshold

vs. Temperature

TEMPERATURE (°C)

125100755025

V

CCON

(V)

16.7

0

16.6

16.5

16.4

16.3

16.2

16.1

16.0

15.9

Figure 10. VCC Turn−Off Threshold

vs. Temperature

11.5

TEMPERATURE (°C)

1

25

100755025−25

V

CCOFF

(V)

0

11.4

11.3

11.2

11.1

11.0

10.9

10.8

0

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TEMPERATURE (°C)

125100755025−25

6.75

6.80

6.85

6.90

V

CCLATCH

(V)

6.95

0

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 11. VCC Latched−Off vs. Temperature

TEMPERATURE (°C)

12

5

100755025−25

1.6

2.2

2.8

I

CC1

(mA)

Figure 12. No Load Circuit Consumption

vs. Temperature

1.8

2.0

2.4

2.6

0

TEMPERATURE (°C)

125100755025−25

2.0

2.5

3.0

3.5

4.0

I

CC2

(mA)

Figure 13. NCP1239F Circuit Consumption

(1 nF on driver Pin 12) vs. Temperature

130 kHz

4.5

5.0

100 kHz

65 kHz

0

TEMPERATURE (°C)

12

5

100755025−25

I

CC2

(mA)

Figure 14. NCP1239V Circuit Consumption

(1 nF on driver Pin 12) vs. Temperature

7.3

200 kHz

130 kHz

0

6.9

6.5

6.1

5.7

5.3

4.9

4.5

4.1

3.7

3.3

260 kHz

TEMPERATURE (°C)

125100755025−25

I

CC3

(mA)

Figure 15. Latched−Off Mode Consumption

vs. Temperature

4.70

4.85

4.90

4.95

TEMPERATURE (°C)

12

5

100755025−25

REF5V (V)

4.80

0 mA

5 mA

10 mA

0.6

5.00

5.05

0

4.75

0

0.5

0.4

0.3

0.2

0.1

0

Figure 16. REF5V Voltage Source

vs. Temperature

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TEMPERATURE (°C)

125100755025−25

2.0

3.0

8.0

Vdrop (V)

TEMPERATURE (°C)

12

5

100755025−25

Rsink ()

0

5.0

6.0

4.0

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 17. Driver High State Voltage Drop

vs. Temperature

Figure 18. Driver Sink Resistance

vs. Temperature

3.0

00

12300

TEMPERATURE (°C)

TEMPERATURE (°C)

12

5

100755025−25

79

81

83

125100755025−25

6700

Dmax (%)

K

osc

(kHz*k)

130 kHz

77

78

80

82

Figure 19. Driver Voltage Clamp vs. Temperature Figure 20. Maximum Duty Cycle vs. Temperatur

e

(NCP1239F)

Figure 21. Oscillator K

osc

Parameter vs. Temperature

(K

osc

= fsw * R

pin4

) (NCP1239F)

TEMPERATURE (°C)

125100755025−25

16

Vcl CLAMP VOLTAGE (V)

65 kHz

0 0

0

TEMPERATURE (°C)

12

5

100755025

K

osc

(kHz*k)

K

osc1

@ 130 kHz

Figure 22. Oscillator K

osc

Parameter vs. Temperature

(K

osc

= fsw * R

pin4

) (NCP1239V)

K

osc2

@ 260 kHz

−25

2.9

2.8

2.7

2.6

2.5

2.4

2.3

2.2

2.1

2.0

7.0

1.0

15

14

13

12

10

11

10

6650

6600

6550

6500

6450

6400

12150

12000

11850

11700

11550

11400

11250

0

NCP1239

http://onsemi.com

12

TEMPERATURE (°C)

12

5

100755025−25

410

415

420

430

435

FB

skip

(mV)

425

445

450

440

0

125

40

60

80

120

140

180

TEMPERATURE (°C)

100755025−25

I

ocp

(



A)

100

160

BO = 2 V

BO = 1 V

0

TYPICAL PERFORMANCE CHARACTERISTICS

TEMPERATURE (°C)

1

25

100755025−25

0.508

V

opl

(V)

Figure 23. Pin 9 Current vs. Temperature

(@ V

pin9

= 0.5 V) (NCP1239F)

Figure 24. Over Power Limitation Threshold vs

.

Temperature (NCP1239F)

0

0.506

0.504

0.502

0.500

0.498

0.496

0.494

0.492

TEMPERATURE (°C)

12

5

100755025−25

BO_H (V)

0.510

TEMPERATURE (°C)

125100755025−25

FB

stby−out

(mV)

780

0

0

TEMPERATURE (°C)

125100755025−25

0.920

I

Limit

(V)

0

Figure 25. Maximum Current Setpoint vs.

Temperature

Figure 26. Default Feedback Threshold for

Standby Detection vs. Temperature

Figure 27. Default Feedback Level for Normal

Operation Recovery

Figure 28. Brown−Out Upper Threshold vs.

Temperature

0.915

0.910

0.905

0.900

0.895

0.890

0.890

0.885

0.880

770
760
750
740
730
720
710
700

0.505

0.500

0.495

0.490

0.485

0.480