ON Semiconductor NCN51205GEVB User Manual

NCN51205GEVB

KNX Evaluation Board
User'sManual

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EVAL BOARD USER’S MANUAL

Introduction

The NCN5120 Development Board is the ideal solution
for developing your KNX application with the
ON Semiconductor KNX transceiver NCN5120. The
development board contains the NCN5120 KNX
Transceiver which handles the transmission and reception of
data on the bus. It will also generate all necessary voltages
to power the board and external loads.

It also contains a microcontroller with debug interface for
custom firmware development. Up to 8 external switches
can be monitored and up to 4 external loads can be
controlled. A voltage between 3.3 V and 21 V is available to
drive the external loads.

The NCN5120 Development Board assures safe coupling
to and decoupling from the KNX bus. Bus monitoring warns
the external microcontroller for loss of power so that critical
data can be stored in time.

Key Features

• 9,600 baud KNX Communication Speed

• Supervision of KNX Bus Voltage

• High Efficient 3.3 V to 21 V Selectable DC−DC

Converter to Drive External Loads

• Monitoring of Power Regulators

• No Additional Power Supply Required

• Buffering of Sent Data Frames

(Extended Frames Supported)

• Selectable UART or SPI Interface to Host Controller

• Selectable UART and SPI Baud Rate to Host Controller

• Optional CRC on UART to the Host

• Optional MARKER Character to the Host

• Optional Direct Coupling of RxD and TxD to Host

(Analog Mode)

• Auto Polling (Optional)

• Temperature Monitoring

• Contains Freely Programmable Microcontroller for

Custom Applications

• Monitoring of 8 External Switches

• Controlling of 4 External (High Voltage) Loads

(e.g. LED’s)

• One Freely Usable Push Button

• 3 Freely Usable LED’s

• Operating Temperature Range −25°C to +85°C

Figure 1. NCN5120 Development Board

© Semiconductor Components Industries, LLC, 2013

May, 2013 − Rev. 0

1 Publication Order Number:

EVBUM2186/D

NCN51205GEVB

BLOCK DIAGRAM

Connector J4

3.3 V

RESETb, SAVEb

J1

Diode + TVS

Reverse Protection

NCN5120

Adj.

Reg.

Figure 2. NCN5120 Development Board Block Diagram

CONNECTOR DESCRIPTION

Table 1. CONNECTOR LIST AND DESCRIPTION

Connector Description

J1 KNX Bus Connection

J2 Power Supply and UART Connection

J3 External Switch Inputs and External Outputs

J4 Microcontroller Debug Interface

Clock

Interface

UART or SPI

MSP430

Drive

Low Side

3 LED +

Switch

LED1,2,3, SW1

ESD Protection

Connector J3

KNX Bus

4 Push Buttons

(with each one blue LED)

TYPICAL APPLICATION

Figure 3. Typical Application

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NCN51205GEVB

ELECTRICAL SPECIFICATION

Recommend Operation Conditions

Operating ranges define the limits for functional
operation and parametric characteristics of the development
board. Note that the functionality of the development board

Table 2. OPERATING RANGES

Symbol Parameter Min Max Unit

V

BUS

V

DIG1

V

DIG2

V

DD1

V

DD2

V

20V

T

a

1. Voltage indicates DC value. With equalization pulse bus voltage must be between 11 V and 45 V

2. Higher voltages are possible. See Adjustable DC−DC Converter page 15 for more details. Only valid if R12, R17, R22 and R25 are not

mounted.

3. See Adjustable DC−DC Converter page 15 for the limitations!

Voltage on Positive Pin of J1 (Note 1) +20 +33 V

Input Voltage on J4 and J3 (Pins 9, 11, 13 and 15) and J2 (Pin 8) 0 3.3 V

Input Voltage on J3 (Pins 1, 3, 5 and 7) (Note 2) 0 5 V

Output Voltage on J2 (Pin 1) 0 3.3 V

Output Voltage on J3 (Pins 2, 4, 6 and 8) and J2 (Pins 3 and 7)
(Note 3)

Output Voltage on J2 (Pin 5) 0 22 V

Ambient Temperature −25 +85 °C

outside these operating ranges is not guaranteed. Operating
outside the recommended operating ranges for extended
periods of time may affect device reliability.

3.3 21 V

Table 3. DC PARAMETERS

(The DC parameters are given for a development board operating within the Recommended Operating Conditions unless otherwise
specified.)
Convention: currents flowing in the circuit are defined as positive.

Con-

Symbol

nector

Power Supply

V

BUS

I

BUS

V

BUSH

V

BUSL

V

BUS_Hyst

J1 1

KNX Bus Coupler

I

coupler_lim

J1 1 Bus Coupler Current

Fixed DC−DC Converter

V

DD1

V

DD1_rip

I

DD1_lim

η

VDD1

J2 1

Pin(s) Parameter

Bus DC Voltage Excluding Active and

Bus Current Consumption Normal Operating Mode,

Undervoltage Release Level V

Undervoltage Trigger Level V

Undervoltage Hysteresis 0.6 V

Limitation

Output Voltage 3.13 3.3 3.47 V

Output Voltage Ripple V

Overcurrent Threshold −100 −200 mA

Power Efficiency Vin=26V, I

Remark/Test

Conditions

Min Typ Max Unit

20 33 V

Equalization Pulse

5 mA
No External Load, DC1
and DC2 Enabled,
Continuous Transmission
of ‘0’ on the KNX Bus by
another KNX Device

Rising

BUS

(Figure NO TAG)

Falling

BUS

(Figure NO TAG)

18.0 V

16.8 V

J5 open 13 30 mA

J5 shorted 26 60 mA

BUS

=26V, I

=40mA 40 mV

DD1

=35mA 90 %

DD1

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NCN51205GEVB

Table 3. DC PARAMETERS (continued)

(The DC parameters are given for a development board operating within the Recommended Operating Conditions unless otherwise
specified.)
Convention: currents flowing in the circuit are defined as positive.

Con-

Symbol UnitMaxTypMin

nector

ParameterPin(s)

Adjustable DC−DC Converter

V

V

DD2

DD2H

J2, J3 3 (J2),

2, 4, 6

and

Output Voltage V

Undervoltage Release Level V

8 (J3)

V

DD2L

V

DD2_rip

I

DD2_lim

η

VDD2

Undervoltage Trigger Level V

Output Voltage Ripple V

Overcurrent Threshold −100 −200 mA

Power Efficiency Vin=26V, V

20 V Regulator

V

20V

I

20V_Lim

V

20VH

V

20VL

V

20V_hys

J2 5

20 V Output Voltage I

20 V Output Current
Limitation

20 V Undervoltage Release
Level

20 V Undervoltage Trigger
Level

Overcurrent Threshold V

Digital Inputs

V

IL

J2 7

Logic Low Threshold Pin 1, 3, 5 and 7 (J3) only

J3 1, 3,

5, 7, 9, 11,

13, 15

J4 2, 3, 4, 5,

6, 8

V

IH

J2 7

Logic High Threshold 2.65 3.3 V

J3 1, 3,

5, 7, 9, 11,

13, 15

J4 2, 3, 4, 5,

6, 8

Digital Outputs

V

V

V

OL_OD

OL

OH

J2 7

J3 1, 3, 5, 7 Logic Low Level Open Drain IOL=5mA − − 0.4 V

Logic Low Output Level 0 − 0.6 V

Logic High Output Level V

Remark/Test

Conditions

BUS>VDD2

Rising

DD2

(Figure NO TAG)

Faling

DD2

(Figure NO TAG)

=26V, V

BUS

I

=40mA

DD2

=35mA

< 4 mA, V

DD2

BUS

I

DD2

20V

= 3.3 V,

DD2

= 3.3 V,

> 25 V 18 20 22 V

3.3 21 V

0.9 × V

DD2

0.8 × V

DD2

40 mV

90 %

−4 −11 mA

20 V Rising 12.6 13.4 14.2 V

20 V Falling 11.8 12.6 13.4 V

= V

20V_hyst

20VH

− V

20VL

0.8 V

0 0.7 V
valid if R12, R17, R22
and/or R25 are mounted
and Q1, Q2, Q3 and/or Q4
are not mounted.

− 0.6 − V

DD1

DD1

V

V

V

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NCN51205GEVB

Table 4. AC PARAMETERS

(The AC parameters are given for a development board operating within the Recommended Operating Conditions unless otherwise
specified.)

Symbol

Power Supply

t

BUS_FILTER

MASTER Serial Peripheral Interface (MASTER SPI)

t

sck

t

SCK_HIGH

t

SCK_LOW

t

SDI_SET

t

SDI_HOLD

t

SDO_VALID

t

CS_HIGH

t

CS_SET

t

CS_HOLD

t

TREQ_LOW

t

TREQ_HIGH

t

TREQ_SET

t

TREQ_HOLD

Universal Asynchronous Receiver/Transmitter (UART)

f

UART

Pin(s) Parameter Remark/Test Conditions Min Ty p Max Unit

VBUS1 VBUS1 Filter Time (Figure x3) − 2 − ms

SCK SPI Clock Period SPI Baudrate Depending on

Configuration Input Bits (see Interface
Mode page 16). Tolerance is Equal to

SPI Clock High Time − t

Xtal Oscillator Tolerance. (Figure 7)

SPI Clock Low Time − t

SDI

SPI Data Input Setup Time 125 − − ns

− 2 −

− 8 −

/2 −

sck

/2 −

sck

SPI Data Input Hold Time 125 − − ns

SDO SPI Data Output Valid Time CL= 20 pF (Figure 7) − − 100 ns

(Figure 7)

(Figure 7)

0.5 × t

SCK

SCK

SCK

− −

− −

− −

125 − − ns

CSBCSB

TREQ

SPI Chip Select High Time

SPI Chip Select Setup Time 0.5 × t

SPI Chip Select Hold Time 0.5 × t

TREQ Low Time

TREQ High Time 125 − − ns

TREQ Setup Time 125 − − ns

TREQ Hold Time 125 − − ns

TXD,
RXD

UART Interface Baudrate Baudrate Depending on Configuration

Input Pins (see Interface Mode

− 19,200 − Baud

page 16).
Tolerance is equal to tolerance of Xtal

− 38,400 − Baud

oscillator tolerance.

ms

ms

V

BUS

V

BUSH

V

BUSL

t

BUS_FILTER

<VBUS>

Comments:

<VBUS> is an internal signal which can be verified with the Internal State Service.

Figure 4. Bus Voltage Undervoltage Threshold

t

BUS_FILTER

t

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NCN51205GEVB

V

DD2

V

DD2H

V

DD2L

<VDD2>

Comments:

<VDD2> is an internal signal which can be verified with the System State Service.

Figure 5. VDD2 Undervoltage Threshold

V

20V

V

20VH

V

20VL

t

CS

CLK

DO

20V_hyst

V

t

<V20V>

Comments:
<V20V> is an internal signal which can be verified with the System State Service.

Figure 6. V20V Undervoltage Threshold levels

DI

t

t

SDI_SET

t

CS _SET

SDI_ HOLD

t

SCK_ HIGH

t

SDO_VALID

t

SCK_ LOW

t

SCK

t

CS_HOLD

t

CS _HIGH

Figure 7. SPI Bus Timing Diagram

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