ON Semiconductor NCN51205GEVB User Manual

NCN51205GEVB

KNX Evaluation Board
User'sManual

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EVAL BOARD USER’S MANUAL

Introduction

The NCN5120 Development Board is the ideal solution
for developing your KNX application with the
ON Semiconductor KNX transceiver NCN5120. The
development board contains the NCN5120 KNX
Transceiver which handles the transmission and reception of
data on the bus. It will also generate all necessary voltages
to power the board and external loads.

It also contains a microcontroller with debug interface for
custom firmware development. Up to 8 external switches
can be monitored and up to 4 external loads can be
controlled. A voltage between 3.3 V and 21 V is available to
drive the external loads.

The NCN5120 Development Board assures safe coupling
to and decoupling from the KNX bus. Bus monitoring warns
the external microcontroller for loss of power so that critical
data can be stored in time.

Key Features

• 9,600 baud KNX Communication Speed

• Supervision of KNX Bus Voltage

• High Efficient 3.3 V to 21 V Selectable DC−DC

Converter to Drive External Loads

• Monitoring of Power Regulators

• No Additional Power Supply Required

• Buffering of Sent Data Frames

(Extended Frames Supported)

• Selectable UART or SPI Interface to Host Controller

• Selectable UART and SPI Baud Rate to Host Controller

• Optional CRC on UART to the Host

• Optional MARKER Character to the Host

• Optional Direct Coupling of RxD and TxD to Host

(Analog Mode)

• Auto Polling (Optional)

• Temperature Monitoring

• Contains Freely Programmable Microcontroller for

Custom Applications

• Monitoring of 8 External Switches

• Controlling of 4 External (High Voltage) Loads

(e.g. LED’s)

• One Freely Usable Push Button

• 3 Freely Usable LED’s

• Operating Temperature Range −25°C to +85°C

Figure 1. NCN5120 Development Board

© Semiconductor Components Industries, LLC, 2013

May, 2013 − Rev. 0

1 Publication Order Number:

EVBUM2186/D

NCN51205GEVB

BLOCK DIAGRAM

Connector J4

3.3 V

RESETb, SAVEb

J1

Diode + TVS

Reverse Protection

NCN5120

Adj.

Reg.

Figure 2. NCN5120 Development Board Block Diagram

CONNECTOR DESCRIPTION

Table 1. CONNECTOR LIST AND DESCRIPTION

Connector Description

J1 KNX Bus Connection

J2 Power Supply and UART Connection

J3 External Switch Inputs and External Outputs

J4 Microcontroller Debug Interface

Clock

Interface

UART or SPI

MSP430

Drive

Low Side

3 LED +

Switch

LED1,2,3, SW1

ESD Protection

Connector J3

KNX Bus

4 Push Buttons

(with each one blue LED)

TYPICAL APPLICATION

Figure 3. Typical Application

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NCN51205GEVB

ELECTRICAL SPECIFICATION

Recommend Operation Conditions

Operating ranges define the limits for functional
operation and parametric characteristics of the development
board. Note that the functionality of the development board

Table 2. OPERATING RANGES

Symbol Parameter Min Max Unit

V

BUS

V

DIG1

V

DIG2

V

DD1

V

DD2

V

20V

T

a

1. Voltage indicates DC value. With equalization pulse bus voltage must be between 11 V and 45 V

2. Higher voltages are possible. See Adjustable DC−DC Converter page 15 for more details. Only valid if R12, R17, R22 and R25 are not

mounted.

3. See Adjustable DC−DC Converter page 15 for the limitations!

Voltage on Positive Pin of J1 (Note 1) +20 +33 V

Input Voltage on J4 and J3 (Pins 9, 11, 13 and 15) and J2 (Pin 8) 0 3.3 V

Input Voltage on J3 (Pins 1, 3, 5 and 7) (Note 2) 0 5 V

Output Voltage on J2 (Pin 1) 0 3.3 V

Output Voltage on J3 (Pins 2, 4, 6 and 8) and J2 (Pins 3 and 7)
(Note 3)

Output Voltage on J2 (Pin 5) 0 22 V

Ambient Temperature −25 +85 °C

outside these operating ranges is not guaranteed. Operating
outside the recommended operating ranges for extended
periods of time may affect device reliability.

3.3 21 V

Table 3. DC PARAMETERS

(The DC parameters are given for a development board operating within the Recommended Operating Conditions unless otherwise
specified.)
Convention: currents flowing in the circuit are defined as positive.

Con-

Symbol

nector

Power Supply

V

BUS

I

BUS

V

BUSH

V

BUSL

V

BUS_Hyst

J1 1

KNX Bus Coupler

I

coupler_lim

J1 1 Bus Coupler Current

Fixed DC−DC Converter

V

DD1

V

DD1_rip

I

DD1_lim

η

VDD1

J2 1

Pin(s) Parameter

Bus DC Voltage Excluding Active and

Bus Current Consumption Normal Operating Mode,

Undervoltage Release Level V

Undervoltage Trigger Level V

Undervoltage Hysteresis 0.6 V

Limitation

Output Voltage 3.13 3.3 3.47 V

Output Voltage Ripple V

Overcurrent Threshold −100 −200 mA

Power Efficiency Vin=26V, I

Remark/Test

Conditions

Min Typ Max Unit

20 33 V

Equalization Pulse

5 mA
No External Load, DC1
and DC2 Enabled,
Continuous Transmission
of ‘0’ on the KNX Bus by
another KNX Device

Rising

BUS

(Figure NO TAG)

Falling

BUS

(Figure NO TAG)

18.0 V

16.8 V

J5 open 13 30 mA

J5 shorted 26 60 mA

BUS

=26V, I

=40mA 40 mV

DD1

=35mA 90 %

DD1

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NCN51205GEVB

Table 3. DC PARAMETERS (continued)

(The DC parameters are given for a development board operating within the Recommended Operating Conditions unless otherwise
specified.)
Convention: currents flowing in the circuit are defined as positive.

Con-

Symbol UnitMaxTypMin

nector

ParameterPin(s)

Adjustable DC−DC Converter

V

V

DD2

DD2H

J2, J3 3 (J2),

2, 4, 6

and

Output Voltage V

Undervoltage Release Level V

8 (J3)

V

DD2L

V

DD2_rip

I

DD2_lim

η

VDD2

Undervoltage Trigger Level V

Output Voltage Ripple V

Overcurrent Threshold −100 −200 mA

Power Efficiency Vin=26V, V

20 V Regulator

V

20V

I

20V_Lim

V

20VH

V

20VL

V

20V_hys

J2 5

20 V Output Voltage I

20 V Output Current
Limitation

20 V Undervoltage Release
Level

20 V Undervoltage Trigger
Level

Overcurrent Threshold V

Digital Inputs

V

IL

J2 7

Logic Low Threshold Pin 1, 3, 5 and 7 (J3) only

J3 1, 3,

5, 7, 9, 11,

13, 15

J4 2, 3, 4, 5,

6, 8

V

IH

J2 7

Logic High Threshold 2.65 3.3 V

J3 1, 3,

5, 7, 9, 11,

13, 15

J4 2, 3, 4, 5,

6, 8

Digital Outputs

V

V

V

OL_OD

OL

OH

J2 7

J3 1, 3, 5, 7 Logic Low Level Open Drain IOL=5mA − − 0.4 V

Logic Low Output Level 0 − 0.6 V

Logic High Output Level V

Remark/Test

Conditions

BUS>VDD2

Rising

DD2

(Figure NO TAG)

Faling

DD2

(Figure NO TAG)

=26V, V

BUS

I

=40mA

DD2

=35mA

< 4 mA, V

DD2

BUS

I

DD2

20V

= 3.3 V,

DD2

= 3.3 V,

> 25 V 18 20 22 V

3.3 21 V

0.9 × V

DD2

0.8 × V

DD2

40 mV

90 %

−4 −11 mA

20 V Rising 12.6 13.4 14.2 V

20 V Falling 11.8 12.6 13.4 V

= V

20V_hyst

20VH

− V

20VL

0.8 V

0 0.7 V
valid if R12, R17, R22
and/or R25 are mounted
and Q1, Q2, Q3 and/or Q4
are not mounted.

− 0.6 − V

DD1

DD1

V

V

V

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NCN51205GEVB

Table 4. AC PARAMETERS

(The AC parameters are given for a development board operating within the Recommended Operating Conditions unless otherwise
specified.)

Symbol

Power Supply

t

BUS_FILTER

MASTER Serial Peripheral Interface (MASTER SPI)

t

sck

t

SCK_HIGH

t

SCK_LOW

t

SDI_SET

t

SDI_HOLD

t

SDO_VALID

t

CS_HIGH

t

CS_SET

t

CS_HOLD

t

TREQ_LOW

t

TREQ_HIGH

t

TREQ_SET

t

TREQ_HOLD

Universal Asynchronous Receiver/Transmitter (UART)

f

UART

Pin(s) Parameter Remark/Test Conditions Min Ty p Max Unit

VBUS1 VBUS1 Filter Time (Figure x3) − 2 − ms

SCK SPI Clock Period SPI Baudrate Depending on

Configuration Input Bits (see Interface
Mode page 16). Tolerance is Equal to

SPI Clock High Time − t

Xtal Oscillator Tolerance. (Figure 7)

SPI Clock Low Time − t

SDI

SPI Data Input Setup Time 125 − − ns

− 2 −

− 8 −

/2 −

sck

/2 −

sck

SPI Data Input Hold Time 125 − − ns

SDO SPI Data Output Valid Time CL= 20 pF (Figure 7) − − 100 ns

(Figure 7)

(Figure 7)

0.5 × t

SCK

SCK

SCK

− −

− −

− −

125 − − ns

CSBCSB

TREQ

SPI Chip Select High Time

SPI Chip Select Setup Time 0.5 × t

SPI Chip Select Hold Time 0.5 × t

TREQ Low Time

TREQ High Time 125 − − ns

TREQ Setup Time 125 − − ns

TREQ Hold Time 125 − − ns

TXD,
RXD

UART Interface Baudrate Baudrate Depending on Configuration

Input Pins (see Interface Mode

− 19,200 − Baud

page 16).
Tolerance is equal to tolerance of Xtal

− 38,400 − Baud

oscillator tolerance.

ms

ms

V

BUS

V

BUSH

V

BUSL

t

BUS_FILTER

<VBUS>

Comments:

<VBUS> is an internal signal which can be verified with the Internal State Service.

Figure 4. Bus Voltage Undervoltage Threshold

t

BUS_FILTER

t

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NCN51205GEVB

V

DD2

V

DD2H

V

DD2L

<VDD2>

Comments:

<VDD2> is an internal signal which can be verified with the System State Service.

Figure 5. VDD2 Undervoltage Threshold

V

20V

V

20VH

V

20VL

t

CS

CLK

DO

20V_hyst

V

t

<V20V>

Comments:
<V20V> is an internal signal which can be verified with the System State Service.

Figure 6. V20V Undervoltage Threshold levels

DI

t

t

SDI_SET

t

CS _SET

SDI_ HOLD

t

SCK_ HIGH

t

SDO_VALID

t

SCK_ LOW

t

SCK

t

CS_HOLD

t

CS _HIGH

Figure 7. SPI Bus Timing Diagram

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NCN51205GEVB

T

T

TSD

T

TW

DT

Hyst

T

<TW>

SAVEB

RESETB

No rm a l

Comments :

−< TW> is an internal signal which can be verified with the System State Service.

−No SPI / UART communication possible when RESETB is low!

−It’s assumed all voltage supplies are within their operating condition.

Stand−By

Reset

Sta rt−Up

Stand−By

Hyst

T

t

Analog State

No rm a l

CS

CLK

DO

TREQ

Figure 8. Temperature Monitoring Levels

DI

t

TREQ _SET

LSB 1 72

Dummy Dummy Dummy Dummy

t

TREQ _LOW

t

TREQ_HIGH

t

TREQ_HOLD

Figure 9. TREQ Timing Diagram

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NCN51205GEVB

APPLICATION SCHEMATIC

Figure 10. Schematic of NCN5120 Development Board (Part 1)

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NCN51205GEVB

APPLICATION SCHEMATIC

Figure 11. Schematic of NCN5120 Development Board (Part 2)

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NCN51205GEVB

Figure 12. Top Layer of NCN5120 Development Board

Figure 13. Bottom Layer of NCN5120 Development Board

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NCN51205GEVB

Figure 14. Inner Layer 1 of NCN5120 Development Board

Figure 15. Inner Layer 2 of NCN5120 Development Board

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NCN51205GEVB

Figure 16. Top Silkscreen of NCN5120 Development Board

Figure 17. Bottom Silkscreen of NCN5120 Development Board

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NCN51205GEVB

Table 5. BILL OF MATERIALS (Note 1)

Reference Part Number Value Voltage Power Tol Type Manufacturer Footprint

CON1 243-211 Wago NA

C1, C2 C1005COG1H100D 10 pF 6.3 V ±5% Ceramic Multilayer TDK 0402

C3, C4, C7 C1005X5R0J104M 100 nF 6.3 V ±20% Ceramic Multilayer TDK 0402

C5 C1608X5R1H473M 47 nF 50 V ±20% Ceramic Multilayer TDK 0603

C6 C1005X5R1H472K 4.7 nF 50 V ±10% Ceramic Multilayer TDK 0402

C8 B41145A7107M000

C9 C1608X5R1H105K

C10

(Note 2)

C11 C2012X5R1E106M

C12 C1608X5R0J106M

C13 C1608X5R1H105M

C14

(Note 2)

C15, C16 C1005X5R0J105M

C17 C1005C0G1H120J 12 pF 6.3 V ±5% Ceramic Multilayer TDK 0402

D1 SS16T3G ON Semiconductor SMA

D2 1SMA40AT3G ON Semiconductor SMA

D3, D13

(Note 2)

D4, D9,

D10, D11,

D12

D5, D6, D7,

D8

J1 RT−01T−1.0B(LF) JST 5.75 mm pitch

J2 (Note 2) 620 008 211 21 Wurth Elektronik 2 mm pitch

J3 620 016 211 21 Wurth Elektronik 2 mm pitch

J4 620 008 211 21 Wurth Elektronik 2 mm pitch

J5, J6, J7,

J8

L1, L2 DA54NP−221K

LED1,
LED2,

LED3

Q1, Q2,

Q3, Q4

R1 D3082F05 Harwin See datasheet

R4 RC1218JK−xx22RL

R5 RC0402JR−xx0RL

R6 RC0402JR−xx33KL

R7, R8 RC0402JR−xx1RL

R9 RC0402JR−xx180KL

R11

(Note 2)

R12, R17,

R22, R25

(Note 2)

R13

(Note 2)

R15, R18,

R23, R26

R16, R19,

R24, R27

C1005COG1H100D 10 pF 6.3 V ±5% Ceramic Multilayer TDK 0402

C1005X5R1H222K 2.2 nF 6.3 V ±10% Ceramic Multilayer TDK 0402

NSR0520V2T1G ON Semiconductor SOD-523

SMF5.0AT1G ON Semiconductor SOD-123FL

ESD5Z3.3T1G ON Semiconductor SOD-523

620 002 111 21 Wurth Elektronik 2 mm pitch

HSMG−C190 Avago

2N7002L ON Semiconductor SOT-23

RC0402JR−xx47KL

RC0402JR−xx0RL 0 R 0.0625 W NA Thick Film Yageo 0402

RC0402JR−xx0RL 0 R 0.0625 W NA Thick Film Yageo 0402

RC0402JR−xx1KL

RC0402JR−xx1ML

100 mF

1 mF

10 mF

10 mF

1 mF

1 mF

220 mH

22 W

0 W

33 kW

1 W

180 kW

47 kW

1kW

1MW

1. All devices are Pb-Free.

2. Not mounted.

35 V ±20% Aluminum Electrolytic Epcos 8 × 10

35 V ±10% Ceramic Multilayer TDK 0603

25 V ±20% Ceramic Multilayer TDK 0805

6.3 V ±20% Ceramic Multilayer TDK 0603

50 V ±20% Ceramic Multilayer TDK 0603

6.3 V ±20% Ceramic Multilayer TDK 0402

±10% Coils Electronic See Datasheet

Technologies

1W ±10% Thick Film Yageo 1218

0.0625 W NA Thick Film Yageo 0402

0.0625 W ±5% Thick Film Yageo 0402

0.0625 W ±5% Thick Film Yageo 0402

0.0625 W ±5% Thick Film Yageo 0402

0.0625 W ±5% Thick Film Yageo 0402

0.0625 W ±5% Thick Film Yageo 0402

0.0625 W ±5% Thick Film Yageo 0402

1.6 × 0.8

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NCN51205GEVB

Table 5. BILL OF MATERIALS (continued)(Note 1)

Reference FootprintManufacturerTypeTolPowerVoltageValuePart Number

R20, R28,

R29

R21 RC0402JR−xx100KL

SW1 MCIPTG33K−V Multicomp See Datasheet

TP1 …

TP19

U1 NCN5120 ON Semiconductor QFN-40

U2 MSP430F2370IRHAx Texas Instruments VQFN-40

Y1 FA-238, 16 MHz, 50 ppm,

1. All devices are Pb-Free.

2. Not mounted.

RC0402JR−xx1KL

20−2137 Vero 1.02 mm

10 pF

1kW

100 kW

0.0625 W ±5% Thick Film Yageo 0402

0.0625 W ±5% Thick Film Yageo 0402

Epson Toyocom 3.2 × 2.5

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NCN51205GEVB

FUNCTIONAL DESCRIPTION

Because the NCN5120 Development Board contains the
NCN5120 KNX Transceiver (KNX Certified) no details on
KNX will be given in this document. Detailed information
on the Certified KNX Transceiver NCN5120 can be found
in the NCN5120 datasheet (www.onsemi.com

). Detailed
information on the KNX Bus can be found on the KNX
website and in the KNX standards (www.knx.org

KNX Bus Connection

).

Connection to the KNX bus is done by means of J1. A
standard Wago connector (type 243−211) can be used for
this (see Figure 18). A reverse protection diode (D1,
Figure 11) is foreseen (mandatory) as also a Transient
Voltage Suppressor (D2, Figure 11).

Figure 18. KNX Bus Connector

Above formula gives only an estimation and will mainly
depend on the firmware loaded on the microcontroller (U2,
see Figure 11). One must always verify that the KNX bus
loading is in line with the KNX Specification under all
operating conditions!

Xtal Oscillator

A crystal of 16 MHz (Y1, see Figure 11) is foreseen on the
development board. This clock signal is also supplied to the
microcontroller. See the NCN5120 datasheet
(www.onsemi.com

RESETB and SAVEB

) for more details on this signal.

The KNX transceiver NCN5120 controls the reset state of
the microcontroller by means of the RESETB signal. An
additional signal SAVEB can be monitored by the
microcontroller to detect possible issues. See NCN5120
datasheet for more details on these two signals.

Voltage Supervisors

NCN5120 has different voltage supervisors. Please check
the NCN5120 datasheet for more details.

Temperature Monitor

NCN5120 produces an over-temperature warning (TW)
and a thermal shutdown warning (TSD). Please check the
NCN5120 datasheet for more details.

Adjustable DC−DC Converter

NCN5120 provides the power for the complete reference
design. It has also a second power supply which can be used
to drive external loads. The voltage is programmable
between 3.3V and 21V by means of an external resistor
divider (R6 and R9, see Figure 11). The voltage divider can
be calculated as next:

R

R

9

R9) R

VDD2M

VDD2M

R

VDD2M

R6+

is between 60 kW and 140 kW (typical 100 kW).

The DC value of the KNX bus should be higher than V
Be aware that when changing the V

* 3.3

V

DD2

3.3

voltage, D9 … D12

DD2

(eq. 1)

DD2

(see Figure 11) need to be replaced. Check the SMFxxA
product family for possible replacements
(www.onsemi.com

Although V

).

is capable of delivering 100 mA, the

DD2

maximum current capability will not always be usable. One
needs to make sure that the KNX bus power consumption
stays within the KNX specification. The maximum allowed
current for V

V

I

BUS

I

is limited by NCN5120. If J5 is open, I

BUS

maximum be 12.5 mA. If J5 is shorted, I
be 25 mA. I
standard. Minimum V

can be calculated as next:

DD2

Ǔ

w 2 ƪ0.033 )ǒV

BUS

will however also be limited by the KNX

BUS

is 20 V (see KNX standard).

BUS

DD2

I

DD2

can maximum

BUS

ƫ

(eq. 2)

BUS

can

External IO

The development board has the possibility to monitor up
to 8 inputs (pin 1, 3, 5, 7, 9, 11, 13 and 15 of J3) and control
up to 4 outputs (pin 1, 3, 5 and 7 of J3). Notice that 4 of the
inputs are shared with 4 of the outputs (pin 1, 3, 5 and 7 of
J3). By default the board has 4 inputs (pin 9, 11, 13 and 15
of J3) and 4 outputs (pin 1, 3, 5 and 7 of J3). To use the
additional 4 inputs, Q1 … Q4 need to be removed and R12,
R17, R22 and R25 need to be mounted. The input pins are

3.3 V compliant and ESD protected (D5 … D8, Figure 11).
J3 is connected in such a way that an easy connection

.

between the input and ground is possible (pin 9, 11, 13 and
15 of J3). The microcontroller (U2, see Figure 11) should be
configured with an internal pull-up (see microcontroller
datasheet on how to do this).

The external outputs are driven by means of low-side
drivers (Q1 … Q4, see Figure 11). A gate resistor is foreseen
for slope control (R15, R18, R23 and R26 of Figure 11). J3
is routed in such a way that the load can easily be connected
between the output (low-side driver) and V
can be used over the complete V
diodes D9 … D12 need to be replaced if V

voltage range. ESD

DD2

DD2

(see also Adjustable DC-DC Converter).

Push Button and LED’s

One push button (SW1) and 3 LED’s (LED1 … LED3)
are foreseen on the reference design. These are freely usable.

. Q1 … Q4

DD2

is increased

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NCN51205GEVB

Jumpers

Several jumpers are located on the board (J5 ... J8). J5 can
be used to set the Fan-In. Mount the jumper for the highest
Fan-In setting.

J6 is required when one wants to force NCN5120 in
Analog Mode (make sure microcontroller is in reset to avoid
conflicts!).

J7 can be used to disconnect the microcontroller from the
fixed DC/DC converter of NCN5120. Be aware that if the
microcontroller is not powered, NCN5120 could start
powering the microcontroller over the IO-pins. It’s advised
to always short J7.

J8 can be used to disconnect the RESETB-signal from the
RST-pin of the microcontroller.

Microcontroller Debug Interface

J4 is the microcontroller debug interface. See the
microcontroller datasheet for more info on how to use this
interface.

Interface Mode

The device can communicate with the host controller by
means of a UART interface or an SPI interface. The
selection of the interface is done by the pins MODE1,
MODE2, TREQ, SCK/UC2 and CSB/UC1 which are
connected to the microcontroller (see Figure 11). More
details on the different interfaces can be found back in
Table 6 and the NCN5120 datasheet.

Digital Description

The implementation of the Data Link Layer as specified
in the KNX standard is divided in two parts. All functions
related to communication with the Physical Layer and most
of the Data Link Layer services are inside NCN5120, the rest
of the functions and the upper communication layers are
implemented into the microcontroller (see Figure 11 and
Figure 19).

The host controller is responsible for handling:

• Checksum

• Parity

• Addressing

• Length

The NCN5120 is responsible for handling:

• Checksum

• Parity

• Acknowledge

• Repetition

• Timing

Services

All services can be found back in the NCN5120 datasheet
(www.onsemi.com

Firmware

No special firmware is provided with the development
board. There will be some basic firmware flashed on the

).

microcontroller (U2, Figure 11) but this is only used to
verify the development board before shipment. The user has
the possibility to develop his own firmware but help on
programming the microcontroller will not be provided my
ON Semiconductor.

NCN5120 contains the physical layer and a part of the data
link layer (see Figure 19). ON Semiconductor can provide
a library for the microcontroller to complete the data link
layer. By no means will ON Semiconductor provide any of
the higher layer stacks (Network Layer, Transport Layer,
…). Sufficient 3
certified higher layer stacks.

FAQs

1. Is this development board KNX Certified?
No, only NCN5120 is KNX Certified. The
development board may only be used for
evaluation of NCN5120. It is not allowed to use
the development board in a final product or to sell
it as a KNX Certified product. Contact
ON Semiconductor if you want to use the
development board as a final product.

2. What 3rd party companies do you recommend for

the higher layer stacks?

ON Semiconductor does not recommend any 3
party company in particular. Several 3rd party
companies have KNX Certified stacks and it’s
always advised to use one of these stacks. Some
companies have experience with NCN5120.
Contact ON Semiconductor for more information.

3. Can we freely reuse the schematic and layout of

this development board?

It is allowed to reuse the schematic, components
and layout of the NCN5120 development board for
your own application. Because the operating
conditions of your design are not known by
ON Semiconductor, one must always fully verify
the design even if it’s based on this development
board. Contact ON Semiconductor if additional
information is required.

4. Can we request ON Semiconductor to supply the

higher layer stacks?

By no means will ON Semiconductor provide any
higher layer stacks. Certified higher layer stacks
can be provided by 3
Firmware).

5. How much load can the outputs drive?
The maximum allow load can be calculated with
the formula as given in Adjustable DC-DC
Converter (page x13). I
load the outputs can drive in total.

rd

party companies are available which have

rd

party companies (see also

defines the maximum

DD2

rd

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16

NCN51205GEVB

6. What is the usage of ARXD and ATXD

(Figure 11)?

These pins have no meaning and cannot be used.

7. I’ve tried all possible R6 and R9 combinations but

I’m not capable of setting V

above 6 V. How

DD2

does this come?

As can be seen in Figure 10, V

DD2

(5 V) is
connected to an ESD protection diode (D14). This
is a 5 V ESD protection diode. Whenever one tries
to set V
and limit the V

above 5 V, this ESD diode will trigger

DD2

voltage to about 6 V.

DD2

This issue can be solved by, or removing D14 (in
an ESD safe area this should not be an issue), or
by replacing this 5 V ESD diode with a higher
voltage version (see the SMFxxA datasheet for
other versions (www.onsemi.com)).

8. Is it possible to test all interfaces (UART, SPI,

Analog Mode) with KNX REV5?

Yes, the KNX REV5 board can be used with all
possible interfaces. One has to be careful however
when using the Analog Mode. In the Analog Mode
the digital of NCN5120 is bypassed. If the
microcontroller would force the RXD−pin (pin 29)
of NCN5120 low, NCN5120 would pull the KNX
bus low which could lead to issues.

9. Is it possible to bypass the microcontroller on the

KNX REV5 board and connect NCN5120 directly
with our microcontroller board?

Although the board is not designed for this, this is
possible. One could connect NCN5120 directly to
your microcontroller board by soldering some
wires on the KNX REV5 board. It is however
advised to remove the microcontroller from the
KNX REV5 board or to put the microcontroller in
reset (short pins 8 and 7 of J4 (see Figure 10)).
In case one wants to use the UART interface (9-bit
UART, 19 200 bps) or Analog Mode, one could
even use connector J2. The KNX_TXD and
KNX_RXD give a direct connection to the TXD­and RXD-pin of NCN5120. Because the MODE1-,
MODE2- and TREQ-pin have an internal pull
down, one does not even need to connect these
pins for UART mode. For Analog Mode one can
use J6 to make the TREQ-pin high.

10. I’m trying to sink more than 13 mA from the KNX

bus with KNX REV5 but I’m having issues with the
voltage regulators whenever I’m going above
16 mA. What could be the issue?

To be able to take more than 13 mA from the KNX
bus one needs to pull the FANIN/WAKE−pin of
NCN5120 low. This can be done by shorting J5
(add jumper).
See NCN5120 datasheet for more info on the
FANIN/WAKE−pin.

Table 6. INTERFACE SELECTION

TREQ MODE2 MODE1 SCK/UC2 SCB/UC1 SDI/RXD SDO/TXD Description

0 0 0 0 0

0 0 0 0 1 9-bit UART-Mode, 38,400 bps

0 0 0 1 0 8-bit UART-Mode, 19,200 bps

0 0 0 1 1 8-bit UART-Mode, 38,400 bps

1 0 0 X X Driver Receiver Analog Mode

TREQ 0 1

TREQ 1 0 SPI Master, 500 kbps

NOTE: X = Don’t Care

SCK (out) CSB (out) SDI SDO

RXD TXD

9-bit UART-Mode, 19,200 bps

SPI Master, 125 kbps

http://onsemi.com

17

NCN51205GEVB

Application Layer

7

Presentation Layer

6

5

4

3

2

1

Session Layer

Transport Layer

Network Layer

Logic Link Control

Data Link Layer

Media Access Control

Physical Layer

Figure 19. OSI Model Reference

NCN5120 Host Controller

http://onsemi.com

18

2.3

NCN51205GEVB

BOARD DIMENSIONS

64.5

61.7

56.0

12.5

39.0

35.2

31.0

2.8

2.7

19.7

−Above dimensions are in mm

−Height C8 = 11 mm

−Height J1 = 7 mm (pins only)

−Height J2, J3, J4 = 6 mm

−Height L1 and L2 (bottom side of PCB) = 4.8 mm

61.7

3.1

36.2

32.4

2.8

The product described herein may be covered by one or more US patents pending.

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19

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