ON Semiconductor NCN49597 User Manual

© Semiconductor Components Industries, LLC, 2011

December, 2011 − Rev. P0

1 Publication Order Number:

NCN49597/D

NCN49597

Product Preview

Power Line Carrier Modem

ON Semiconductor’s NCN49597 is an IEC 61334−5−1 compliant
power line carrier modem using spread−FSK (S−FSK) modulation for
robust low data rate communication over power lines. NCN49597 is
built around an ARM processor core, and includes the MAC layer.
With this robust modulation technique, signals on the power lines can
pass long distances. The half−duplex operation is automatically
synchronized to the mains, and can be up to 4800 bits/sec.

The product configuration is done via its serial interface, which
allows the user to concentrate on the development of the application.

The NCN49597 is implemented in ON Semiconductor mixed signal
technology, combining both analog circuitry and digital functionality
on the same IC.

Features

• Power Line Carrier Modem for 50 and 60 Hz Mains

• Fully compliant to IEC 61334−5−1 and CENELEC EN 50065−1

• Complete Handling of Protocol Layers Physical to MAC

• Programmable Carrier Frequencies in CENELEC A-Band from 9 to

95 kHz; B−Band from 95 to 125 kHz, in 10 Hz Steps

• Half Duplex

• Data Rate Selectable:

300 – 600 – 1200 − 2400 – 4800 baud (@ 50 Hz)
360 – 720 – 1440 − 2880 – 5760 baud (@ 60 Hz)

• Synchronization on Mains

• Repetition Algorithm Boost the Robustness of Communication

• SCI Port to Application Microcontroller

• SCI Baudrate Selectable: 9.6 – 19.2 – 38.4 − 115.2 kb

• Power Supply 3.3 V

• Ambient Temperature Range: −40°C to +80°C

• These Devices are Pb−Free and are RoHS Compliant*

Typical Applications

• ARM: Automated Remote Meter Reading

• Remote Security Control

• Streetlight Control

• Transmission of Alerts (Fire, Gas Leak, Water Leak)

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.

This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.

ON

e3

ARM

See detailed ordering and shipping information in the package
dimensions section on page 27 of this data sheet.

ORDERING INFORMATION

XXXX = Date Code
Y = Plant Identifier
ZZ = Traceability Code

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MARKING DIAGRAMS

152

QFN52 8x8, 0.5P

CASE 485M

XXXXYZZ
NCN 49597
C597−901

1

52

NCN49597

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APPLICATION

Application Example

PC20111120 .1

TX_OUT

NCN49597

TX_ENB

ZC_IN

REF_OUT

RX_IN

RX_OUT

XTAL _IN

XTAL_OUT

Appli

&

Metering

mC

TXD

RXD

BR0

BR1

RESB

VSSA

VSS

T_REQ

VDD

VDDA

3V3_A 3V3_D

1:2

C

1

R

1

C

2

R

2

C

DREF

C

16

C

17

3V3_A

D

5

D

1

D

2

D

3

D

4

R

12

C

11

C

12

R

14

C

15

C

14

Y

1

NCS5650

Enable

C

3

C

4

C

6

C

7

R

6

R

5R4

R

7

R

9

R

10

2

Vcom

+B

−B

+A

−A

OutA

OutB

8

9

13

12 5

4

3

1

6

7

VCC

10 11

VEE

Vuc

19

151420

GNDuC

Rlim

Vwarn

3V3_D12V

R

11

C

5

C

10

C

9

12V

R

3

MAINS

Tr

C

8

C

13

U

1

U

2

3V3_D

VDD1V8

R

8

SEN

EXT_CLK_E

Figure 1. Typical Application for the NCN49597S−FSK Modem

Figure 1 shows an S−FSK PLC modem build around
NCN49597. For synchronization the line frequency is
coupled in via a 1 MW resistor. The Schottky diode pair D

5

clamps the voltage within the input range of the zero cross
detector. In the receive path a 2

nd

order high pass filter

blocks the mains frequency. The corner point defined by C

1

,

C

2

, R1 and R2 is designed at 10 kHz. In the transmit path a

3

th

order low pass filter build around the NCS5650 power

operational amplifier suppresses the 2

nd

and 3rd harmonics

to be in line with the CENELEC EN 50065−1 specification.

The filter components are tuned for a space and mark
frequency of 63.3 and 74 kHz respectively. The output of the
amplifier is coupled via a DC blocking capacitor C

10

to a 2:1
pulse transformer Tr. The secondary of this transformer is
coupled to the mains via a high voltage capacitor C

11

. High
energetic transients from the mains are clamped by the
protection diode combination D

3

, D4 together with D1, D2.
Because the mains is not galvanic isolated care needs to be
taken when interfacing to a microcontroller or a PC!

Table 1. EXTERNAL COMPONENTS LIST AND DESCRIPTION

Component Function − Remark Typ Value Tolerance Unit

C1, C

2

High pass receive filter 1.5 ±10% nF

C5, C

DREF

V

REF_OUT

; V

REF_OUT

decoupling cap − ceramic 1 −20 +80%

mF

C7, C9, C16, C

17

Decoupling block capacitor 100 −20 +80% nF

C

3

TX_OUT coupling capacitor 470 ±20% nF

C

4

Low pass transmit filter 470 ±10% pF

C

6

Low pass transmit filter 68 ±10% pF

C

8

Low pass transmit filter 3 ±10% pF

C

10

TX coupling cap; 1 A rms ripple @ 70 kHz 10 ±20%

mF

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Table 1. EXTERNAL COMPONENTS LIST AND DESCRIPTION

Component UnitToleranceTyp ValueFunction − Remark

C

11

High Voltage coupling capacitor; 630 V 220 ±20% nF

C

12

Zero Cross noise suppression 100 ±20% pF

C13, C

14

X−tal load capacitor 22 ±20% pF

C

15

Decoupling block capacitor 1.8 V internal supply 1 −20 +80%

mF

R

1

High pass receive filter 22 ±1%

kW

R

2

High pass receive filter 11 ±1%

kW

R3, R9, R

12,

R

13

High pass receive filter; Alarm current ; Pull up 10 ±1%

kW

R

4

Low pass transmit filter 3,3 ±1%

kW

R

5

Low pass transmit filter 10 ±1%

kW

R

6

Low pass transmit filter 8,2 ±1%

kW

R

7

Low pass transmit filter 500 ±1%

W

R

8

Low pass transmit filter 3 ±1%

kW

R

10

TX Coupling resistor ; 0.5 W 0,47 ±1%

W

R

11

Zero Cross coupling HiV 1 ±5%

MW

D1, D

2

High current Schottky Clamp diodes MBRA430

D3, D

4

TVS diodes P6SMB6.8AT3G

D

5

Double low current Schottky clamp diode BAS70−04

Y1 X−tal 48 MHz

Tr 2:1 Pulse transformer

U1 PLC modem NCN49597

U2 Power Operational Amplifier NCS5650

Table 2. ABSOLUTE MAXIMUM RATINGS

Rating Symbol Min Max Unit

ABSOLUTE MAXIMUM RATINGS SUPPLY
Power Supply Pins VDD, VDDA, VSS, VSSA

Absolute max. digital power supply

V

DD_ABSM

V

SS

− 0.3 3.9 V

Absolute max. analog power supply V

DDA_ABSM

V

SSA

−

0.3

3.9 V

Absolute max. difference between digital and analog power supply V

DD

− V

DDA_ABSM

−0.3 0.3 V

Absolute max. difference between digital and analog ground V

SS

− V

SSA_ABSM

−0.3 0.3 V

ABSOLUTE MAXIMUM RATINGS NON 5V SAFE PINS
Non 5V Safe Pins: TX_OUT, ALC_IN, RX_IN, RX_OUT, REF_OUT, ZC_IN, XIN, XOUT, TDO, TDI, TCK, TMS, TRSTB, TEST

Absolute maximum input for normal digital inputs and analog inputs V

IN_ABSM

V

SS

− 0.3 V

DD

+ 0.3 V

Absolute maximum voltage at any output pin V

OUT_ABSM

V

SS

− 0.3 V

DD

+ 0.3 V

ABSOLUTE MAXIMUM RATINGS 5V SAFE PINS
5V Safe Pins: TX_ENB, TXD, RXD, BR0, BR1, IO3 .. IO11, RESB

Absolute maximum input for digital 5V safe inputs

V

5VS_ABSM

V

SS

− 0.3 6.0 V

Absolute maximum voltage at 5V safe output pin V

OUT5V_ABSM

V

SS

− 0.3 3.9 V

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.

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Normal Operating Conditions

Operating ranges define the limits for functional operation and parametric characteristics of the device as described in the
Normal Operating Conditions section and for the reliability specifications as listed in Detailed Hardware Description section.
Functionality outside these limits is not implied.

Total cumulative dwell time outside the normal power supply voltage range or the ambient temperature under bias, must be
less than 0.1% of the useful life as defined in Detailed Hardware Description section.

Table 3. OPERATING RANGES

Rating Symbol Min Max Unit

Power supply voltage range V

DD

3.0 3.6 V

Ambient Temperature T

A

−25 80 °C

Extended Ambient Temperature on special request T

A

−40 80 °C

PIN DESCRIPTION

QFN Packaging

AMIS49597

1

2

3

4

5

6

7

8

9

10

11

12

13

26

25

24

23

22

21

20

19

18

17

16

15

14

39

38

37

36

35

34

33

32

31

30

29

28

27

40

41

42

43

44

45

46

47

48

49

50

51

52

NC

REF_O UT

NC

RX_IN

RX_OUT

VSSA

VDDA

NC

NC

ALC_IN

TX_OUT

NC

NC

IO8

IO9

TXD /PRES

XIN

XOUT

VDD 1V8

VSS

VDD

TXD

IO10

RXD

SCK

SDI

IO7

IO6

TMS

TCK

TDI

TDO

IO0/RX_DATA

IO5

IO4

IO3

NC

M50Hz _IN

SDO

CSB

T_REQ

SEN

BR1

BR0

CRC

IO11

TEST

NC

NC

TRST

RES

TX_EN

Figure 2. QFN Pin−out of NCN49597 (Top view)

Table 4. NCN49597QFN PIN FUNCTION DESCRIPTION

Pin No. Pin Name I/O Type Description

1 ZC_IN In A 50/60 Hz input for mains zero cross detection

3..5, 12..15,
23, 34

IO3 .. IO11 In/Out D, 5V Safe General Purpose I/O

6 RX_DATA Out D, 5V Safe Data reception indication (open drain output)

7 TDO Out D, 5V Safe Test data output

8 TDI In D, 5V Safe Test data input (internal pull down)

9 TCK In D, 5V Safe Test clock (internal pull down)

10 TMS In D, 5V Safe Test mode select (internal pull down)

11 TRSTB In D, 5V Safe Test reset bar (internal pull down, active low)

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Table 4. NCN49597QFN PIN FUNCTION DESCRIPTION

Pin No. DescriptionTypeI/OPin Name

16 TXD/PRES Out D, 5V Safe Output of transmitted data (TXD) or PRE_SLOT signal

(PRES)

17 XIN In A Xtal input (can be driven by an internal clock)

18 XOUT Out A Xtal output (output floating when XIN driven by external

clock)

19 VDD1V8 P 1V8 regulator output. Foresee a decoupling capacitor

20 VSS P Digital ground

21 VDD P 3.3V digital supply

22 TXD Out D, 5V Safe SCI transmit output (open drain)

24 RXD In D, 5V Safe SCI receive input (Schmitt trigger output)

25 SCK Out D SPI interface external Flash

26 SDI In D SPI interface external Flash

27 SDO Out D SPI interface external Flash

28 CSB In D SPI interface external Flash

29 T_REQ In D, 5V Safe Transmit Request input

30 SEN In D Boot option

31 BR1 In D, 5V Safe SCI baud rate selection

32 BR0 In D, 5V Safe SCI baud rate selection

33 CRC Out D, 5V Safe Correct frame CRC indication (open drain output)

35 RESB In D, 5V Safe Master reset bar (Schmitt trigger input, active low)

36 TEST In D Hardware Test enable (internal pull down)

37 TX_ENB Out D, 5V Safe TX enable bar (open drain)

42 TX_OUT Out A Transmitter output

43 ALC_IN In A Automatic level control input

46 VDDA P 3.3V analog supply

47 VSSA P Analog ground

48 RX_OUT Out A Output of receiver low noise operational amplifier

49 RX_IN In A Positive input of receiver low noise operational amplifier

51 REF_OUT Out A Reference output for stabilization

2, 38..41, 44,

45,50, 52

NC Pins 2, 38..41, 44, 45, 50, 52 are not connected. These

pins need to be left open or connected to the GND plane.

P: Power pin 5V Safe: IO that support the presence of 5V on bus line

A: Analog pin Out: Output signal

D: Digital pin In: Input signal

Detailed Pin Description

VDDA

VDDA is the positive analog supply pin. Nominal voltage

is 3.3 V. A ceramic decoupling capacitor C

DA

= 100 nF must
be placed between this pin and the VSSA. Connection path
of this capacitance to the VSSA on the PCB should be kept
as short as possible in order to minimize the serial resistance.

REF_OUT

REF_OUT is the analog output pin which provides the

voltage reference used by the A/D converter. This pin must
be decoupled to the analog ground by a 1 mF ceramic
capacitance C

DREF

. The connection path of this capacitor to

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the VSSA on the PCB should be kept as short as possible in
order to minimize the serial resistance.

VSSA

VSSA is the analog ground supply pin.

VDD

VDD is the 3.3 V digital supply pin. A ceramic decoupling

capacitor C

DD

= 100 nF must be placed between this pin and
the VSS. Connection path of this capacitance to the VSS on
the PCB should be kept as short as possible in order to
minimize the serial resistance.

VSS

VSS is the digital ground supply pin.

Figure 3: Recommended Layout of the Placement of

Decoupling Capacitors

VDD1V8

This is an additional power supply pin to decouple an
internal LDO regulator. The decoupling capacitor should be
placed as close as possible to this output pin as illustrated in
Figure 4.

RX_OUT

RX_OUT is the output analog pin of the receiver low
noise input op−amp. This op−amp is in a negative feedback
configuration.

RX_IN

RX_IN is the positive analog input pin of the receiver low
noise input op−amp. Together with RX_OUT and
REF_OUT, an active high pass filter is realized. This filter
removes the main frequency (50 or 60 Hz) from the received
signal. The filter characteristics are determined by external
capacitors and resistors. A typical application schematic can
be found in paragraph 50/60 Hz Suppression Filter.

ZC_IN

ZC_IN is the mains frequency analog input pin. The signal
is used to detect the zero cross of the 50 or 60 Hz sine wave.

This information is used, after filtering with the internal
PLL, to synchronize frames with the mains frequency. In
case of direct connection to the mains it is advised to use a
series resistor of 1 MW in combination with two external
clamp diodes in order to limit the current flowing through
the internal protection diodes.

RX_DATA

RX_DATA is a 5 V compliant open drain output. An
external pull−up resistor defines the logic high level as
illustrated in Figure 4. A typical value for the pull−up
resistance “R” is 10 kW. The signal on this output depends
on the status of the data reception. If NCN49597waits for
configuration RX_DATA outputs a pulse train with a 10 Hz
frequency. After Synchronization Confirm Time out
RX_DATA = 0. If NCN49597is searching for
synchronization RX_DATA = 1.

PC20090722. 2

V

SSD

+5V

Output

R

Figure 4. Representation of 5V Safe Output

TDO, TDI, TCK, TMS, and TRSTB

All these pins are part of the JTAG bus interface. The
JTAG interface is used during production test of the IC and
will not be described here. Input pins (TDI, TCK, TMS, and
TRSTB) contain internal pull−down resistance. TDO is an
output. When not used, the JTAG interface pins may be left
floating.

TXD/PRES

TXD/PRES is the output for either the transmitting data
(TX_DATA) or a synchronization signal with the time−slots
(PRE_SLOT). TXD/PRES. More information can be found
in paragraph Local Port.

XIN

XIN is the analog input pin of the oscillator. It is connected
to the interval oscillator inverter gain stage. The clock signal
can be created either internally with the external crystal and
two capacitors or by connecting an external clock signal to
XIN. For the internal generation case, the two external
capacitors and crystal are placed as shown in Figure 5. For
the external clock connection, the signal is connected to XIN
and XOUT is left unused.

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XTAL_IN

PC20111118.1

XTAL_OUT

C

X

V

SSA

C

X

48 MHz

Figure 5. Placement of the Capacitors and Crystal

with Clock Signal Generated Internally

The crystal is a classical parallel resonance crystal of

48 MHz. The values of the capacitors C

X

are given by the
manufacturer of the crystal. A typical value is 36 pF. The
crystal has to fulfill impedance characteristics specified in
the NCN49597data sheet. As an oscillator is sensitive and
precise, it is advised to put the crystal as close as possible on
the board and to ground the case.

XOUT

XOUT is the analog output pin of the oscillator. When the
clock signal is provided from an external generator, this
output must be floating. When working with a crystal, this
pin cannot be used directly as clock output because no
additional loading is allowed on the pin (limited voltage
swing).

TXD

TXD is the digital output of the asynchronous serial
communication (SCI) unit. Only half−duplex transmission
is supported. It is used to realize the communication between
the NCN49597and the application microcontroller. The
TXD is an open drain IO (5 V safe). External pull−up
resistances (typically 10 kW) are necessary to generate the
5 V level. See Figure 4 for the circuit schematic.

RXD

This is the digital input of the asynchronous SCI unit.

Only half−duplex transmission is supported. This pin
supports a 5 V level. It is used to realize the communication
between the NCN49597and the application microcontroller.
RXD is a 5 V safe input.

T_REQ

T_REQ is the transmission request input of the Serial
Communication Interface. When pulled low its initiate a
local communication from the application micro controller
to NCN49597. T_REQ is a 5 V safe input. See also
paragraph Error! Reference source not found..

BR1, BR0

BR0 and BR1 are digital input pins. They are used to select
the baud rate (bits/second) of the Serial Communication
Interface unit. The rate is defined according to Error!
Reference source not found.. The values are taken into

account after a reset, hardware or software. Modification of
the baud rate during function is not possible. BR0 and BR1
are 5 V safe.

CRC

CRC is a 5 V compliant open drain output. An external
pull−up resistor defines the logic high level as illustrated in
Figure 4. A typical value for this pull−up resistance “R” is
10 kW. The signal on this output depends on the cyclic
redundancy code result of the received frame. If the cyclic
redundancy code is correct CRC = H during the pause
between two time slots.

RESB

RESB is a digital input pin. It is used to perform a
hardware reset of the NCN49597. This pin supports a 5 V
voltage level. The reset is active when the signal is low
(0 V).

TEST

TEST is a digital input pin with internal pull down resistor
used to enable the Hardware Test Mode of the chip. When
TEST is left open or forced to ground Normal Mode is
enabled. When TEST is forced to VDD the Hardware Test
Mode is enabled. This mode is used during production test
of the IC and will not be described here. TEST pin is not 5 V
safe.

TX_ENB

TX_ENB is a digital output pin. It is low when the
transmitter is activated. The signal is available to turn on the
line driver. TX_ENB is a 5 V safe with open drain output,
hence a pull−up resistance is necessary achieve the
requested voltage level associated with a logical one. See
also Figure 4 for reference.

TX_OUT

TX_OUT is the analog output pin of the transmitter. The
provided signal is the S−FSK modulated frames. A filtering
operation must be performed to reduce the second and third
order harmonic distortion. For this purpose an active filter
is suggested. See also paragraph Transmitter Output
TX_OUT.

ALC_IN

ALC_IN is the automatic level control analog input pin.
The signal is used to adjust the level of the transmitted
signal. The signal level adaptation is based on the AC
component. The DC level on the ALC_IN pin is fixed
internally to 1.65 V. Comparing the peak voltage of the AC
signal with two internal thresholds does the adaptation of the
gain. Low threshold is fixed to 0.4 V. A value under this
threshold will result in an increase of the gain. The high
threshold is fixed to 0.6 V. A value over this threshold will
result in a decrease of the gain. A serial capacitance is used
to block the DC components. The level adaptation is
performed during the transmission of the first two bits of a
new frame. Eight successive adaptations are performed. See

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also paragraph Amplifier with Automatic Level Control
(ALC).

SCK, SDI, SDO, CSB

These signals from the SPI interface to an optional
external Flash. See Reference 1.

ELECTRICAL CHARACTERISTICS

DC and AC Characteristics

Oscillator: Pin XIN, XOUT

In production the actual oscillation of the oscillator and duty cycle will not be tested. The production test will be based on

the static parameters and the inversion from XIN to XOUT in order to guarantee the functionality of the oscillator.

Table 5. OSCILLATOR

Parameter Test Conditions Symbol Min Typ Max Unit

Crystal frequency (Note 1) f

CLK

−100 ppm 48 +100 ppm MHz

Duty cycle with quartz connected (Note 1) 40 60 %

Start−up time (Note 1) T

startup

50 ms

Load capacitance external crystal (Note 1) C

L

18 pF

Series resistance external crystal (Note 1) R

S

20 40 80

W

Maximum Capacitive load on
XOUT

XIN used as clock input CL

XOUT

50 pF

Low input threshold voltage XIN used as clock input VIL

XOUT

0.3 V

DD

V

High input threshold voltage XIN used as clock input VIH

XOUT

0.7 V

DD

V

Low output voltage XIN used as clock input,

XOUT = 2 mA

VOL

XOUT

0.3 V

High input voltage XIN used as clock input VOH

XOUT

V

DD

− 0.3 V

1. Guaranteed by design. Maximum allowed series loss resistance is 80 W

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Zero Cross Detector and 50/60 Hz PLL: Pin ZC_IN

Table 6. ZERO CROSS DETECTOR AND 50/60 HZ PLL

Parameter Test Conditions Symbol Min Typ Max Unit

Maximum peak input current Imp

ZC_IN

−20 20 mA

Maximum average input current During 1 ms Imavg

ZC_IN

−2 2 mA

Mains voltage (ms) range With protection resistor at

ZC_IN

V

MAINS

90 550 V

Rising threshold level (Note 2) VIR

ZC_IN

1.9 V

Falling threshold level (Note 2) VIF

ZC_IN

0.9 V

Hysteresis (Note 2) VHY

ZC_IN

0.4 V

Lock range for 50 Hz (Note 3) MAINS_FREQ = 0 (50 Hz) Flock

50Hz

45 55 Hz

Lock range for 60 Hz (Note 3) MAINS_FREQ = 0 (60 Hz) Flock

60Hz

54 66 Hz

Lock time (Note 3) MAINS_FREQ = 0 (50 Hz) Tlock

50Hz

15 s

Lock time (Note 3) MAINS_FREQ = 0 (60 Hz) Tlock

60Hz

20 s

Frequency variation without going
out of lock (Note 3)

MAINS_FREQ = 0 (50 Hz) DF

60Hz

0.1 Hz/s

Frequency variation without going
out of lock (Note 3)

MAINS_FREQ = 0 (60 Hz) DF

50Hz

0.1 Hz/s

Jitter of CHIP_CLK (Note 3) Jitter

CHIP_CLK

−25 25

ms

2. Measured relative to VSS

3. These parameters will not be measured in production since the performance is totally dependent of a digital circuit which will be guaranteed
by the digital test patterns.