ON Semiconductor MC74HC14A Technical data

MC74HC14A

Hex Schmitt−Trigger
Inverter

High−Performance Silicon−Gate CMOS

The MC74HC14A is identical in pinout to the LS14, LS04 and the
HC04. The device inputs are compatible with Standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL
outputs.

The HC14A is useful to “square up” slow input rise and fall times.
Due to hysteresis voltage of the Schmitt trigger, the HC14A finds
applications in noisy environments.

Features

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 mA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance With the JEDEC Standard No. 7.0 A Requirements

• Chip Complexity: 60 FETs or 15 Equivalent Gates

• Pb−Free Packages are Available

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MARKING

DIAGRAMS

14

PDIP−14

4

1

14

1

N SUFFIX

CASE 646

SOIC−14

D SUFFIX

CASE 751A

MC74HC14AN

AWLYYWWG

1

14

HC14AG

AWLYWW

1

14

1

74HC14A

ALYWG

1

HC

14A

ALYWG

G

14

14

1

(Note: Microdot may be in either location)

See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.

TSSOP−14
DT SUFFIX

CASE 948G

1

14

SOEIAJ−14

F SUFFIX

CASE 965

A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G or G = Pb−Free Package

ORDERING INFORMATION

© Semiconductor Components Industries, LLC, 2006

October, 2006 − Rev. 11

1 Publication Order Number:

MC74HC14A/D

MC74HC14A

Pinout: 14−Lead Packages (Top View)

V

A6 Y6 A5 Y5 A4 Y4

CC

1314 12 11 10 9 8

21 34567

A1 Y1 A2 Y2 A3 Y3 GND

FUNCTION TABLE

Inputs Outputs

A

L

H

Y

H

L

LOGIC DIAGRAM

1

3

A2

5

A3

9

A4

11

A5

13

A6

2

Y1A1

4

Y2

6

Y3

Y = A

8

Y4

Pin 14 = V
Pin 7 = GND

10

Y5

12

Y6

CC

ORDERING INFORMATION

Device Package Shipping

MC74HC14AN PDIP−14

MC74HC14ANG PDIP−14

(Pb−Free)

MC74HC14AD SOIC−14

MC74HC14ADG SOIC−14

(Pb−Free)

MC74HC14ADR2 SOIC−14

MC74HC14ADR2G SOIC−14

(Pb−Free)

MC74HC14ADT TSSOP−14*

MC74HC14ADTG TSSOP−14*

MC74HC14ADTR2 TSSOP−14*

MC74HC14ADTR2G TSSOP−14*

MC74HC14AF SOEIAJ−14

MC74HC14AFG SOEIAJ−14

(Pb−Free)

MC74HC14AFEL SOEIAJ−14*

MC74HC14AFELG SOEIAJ−14*

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

25 Units / Rail

55 Units / Rail

2500 / Tape & Reel

96 Units / Rail

2500 / Tape & Reel

50 Units / Rail

2000 / Tape & Reel

†

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2

MC74HC14A

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

MAXIMUM RATINGS

Symbol

V

V

ÎÎ

ÎÎ

DC Supply Voltage (Referenced to GND)

CC

V

DC Input Voltage (Referenced to GND)

in

DC Output Voltage (Referenced to GND)

out

I

DC Input Current, per Pin

in

I

DC Output Current, per Pin

out

I

DC Supply Current, VCC and GND Pins

CC

P

Power Dissipation in Still Air, Plastic DIP†

D

ОООООООООООО

T

Storage Temperature Range

stg

T

Lead Temperature, 1 mm from Case for 10 Seconds

L

ОООООООООООО

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not im-

ООООООООООООООООООООО

plied. Extended exposure to stresses above the Recommended Operating Conditions may af­fect device reliability.

ООООООООООООООООООООО

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).

Parameter

SOIC Package†

TSSOP Package†

Plastic DIP, SOIC or TSSOP Package

Value

– 0.5 to + 7.0

– 0.5 to VCC + 0.5

– 0.5 to VCC + 0.5

±20

±25

±50

750
500

ÎÎÎ

450

– 65 to + 150

ÎÎÎ

260

Unit

mA

mA

mA

mW

Î

_C

_C

Î

This device contains protection

V

V

V

circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir­cuit. For proper operation, V

should be constrained to the

V

out

range GND v (V

in

or V

) v VCC.

out

in

and

Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V

CC

Unused outputs must be left open.

).

RECOMMENDED OPERATING CONDITIONS

Symbol

V

Vin, V

DC Supply Voltage (Referenced to GND)

CC

DC Input Voltage, Output Voltage (Referenced to

out

GND)

T

tr, t

ÎÎ

ÎÎ

Operating Temperature Range, All Package Types

A

Input Rise/Fall Time VCC = 2.0 V

f

ОООООООООООО

(Figure 1) V

ОООООООООООО

*When Vin = 50% VCC, ICC > 1mA

Parameter

V

= 4.5 V

CC

= 6.0 V

CC

Min

2.0

0

– 55

0

Î

0
0

Î

Max

6.0

V

CC

+ 125

No Limit*

ÎÎ

No Limit*
No Limit*

ÎÎ

Unit

V

V

_C

ns

Î

Î

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3