Datasheet MC74HC14A Datasheet (ON Semiconductor)

MC74HC14A

Hex Schmitt−Trigger Inverter

High−Performance Silicon−Gate CMOS

The MC74HC14A is identical in pinout to the LS14, LS04 and the HC04. The device inputs are compatible with Standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

The HC14A is useful to “square up” slow input rise and fall times. Due to hysteresis voltage of the Schmitt trigger, the HC14A finds applications in noisy environments.

Features

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 mA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance With the JEDEC Standard No. 7.0 A Requirements

• Chip Complexity: 60 FETs or 15 Equivalent Gates

• Pb−Free Packages are Available

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MARKING

DIAGRAMS

14

PDIP−14

4

1

14

1

N SUFFIX

CASE 646

SOIC−14

D SUFFIX

CASE 751A

MC74HC14AN

AWLYYWWG

1

14

HC14AG

AWLYWW

1

14

1

74HC14A

ALYWG

1

HC

14A

ALYWG

G

14

1

(Note: Microdot may be in either location)

See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.

TSSOP−14 DT SUFFIX

CASE 948G

1

14

SOEIAJ−14

F SUFFIX

CASE 965

A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G or G = Pb−Free Package

ORDERING INFORMATION

October, 2006 − Rev. 11

1 Publication Order Number:

MC74HC14A/D

MC74HC14A

Pinout: 14−Lead Packages (Top View)

V

A6 Y6 A5 Y5 A4 Y4

CC

1314 12 11 10 9 8

21 34567

A1 Y1 A2 Y2 A3 Y3 GND

FUNCTION TABLE

Inputs Outputs

A

L

H

Y

H

L

LOGIC DIAGRAM

1

3

A2

5

A3

9

A4

11

A5

13

A6

2

Y1A1

4

Y2

6

Y3

Y = A

8

Y4

Pin 14 = V Pin 7 = GND

10

Y5

12

Y6

CC

ORDERING INFORMATION

Device Package Shipping

MC74HC14AN PDIP−14

MC74HC14ANG PDIP−14

(Pb−Free)

MC74HC14AD SOIC−14

MC74HC14ADG SOIC−14

(Pb−Free)

MC74HC14ADR2 SOIC−14

MC74HC14ADR2G SOIC−14

(Pb−Free)

MC74HC14ADT TSSOP−14*

MC74HC14ADTG TSSOP−14*

MC74HC14ADTR2 TSSOP−14*

MC74HC14ADTR2G TSSOP−14*

MC74HC14AF SOEIAJ−14

MC74HC14AFG SOEIAJ−14

(Pb−Free)

MC74HC14AFEL SOEIAJ−14*

MC74HC14AFELG SOEIAJ−14*

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

25 Units / Rail

55 Units / Rail

2500 / Tape & Reel

96 Units / Rail

2500 / Tape & Reel

50 Units / Rail

2000 / Tape & Reel

†

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2

MC74HC14A

Î

MAXIMUM RATINGS

Symbol

V

ÎÎ

DC Supply Voltage (Referenced to GND)

CC

V

DC Input Voltage (Referenced to GND)

in

DC Output Voltage (Referenced to GND)

out

I

DC Input Current, per Pin

in

I

DC Output Current, per Pin

out

I

DC Supply Current, VCC and GND Pins

CC

P

Power Dissipation in Still Air, Plastic DIP†

D

ОООООООООООО

T

Storage Temperature Range

stg

T

Lead Temperature, 1 mm from Case for 10 Seconds

L

ОООООООООООО

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not im-

ООООООООООООООООООООО

plied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

ООООООООООООООООООООО

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP Package: − 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).

Parameter

SOIC Package†

TSSOP Package†

Plastic DIP, SOIC or TSSOP Package

Value

– 0.5 to + 7.0

– 0.5 to VCC + 0.5

±20

±25

±50

750 500

ÎÎÎ

450

– 65 to + 150

ÎÎÎ

260

Unit

mA

mW

Î

_C

Î

This device contains protection

V

circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, V

should be constrained to the

V

out

range GND v (V

in

or V

) v VCC.

out

in

and

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V

CC

Unused outputs must be left open.

).

RECOMMENDED OPERATING CONDITIONS

Symbol

V

Vin, V

DC Supply Voltage (Referenced to GND)

CC

DC Input Voltage, Output Voltage (Referenced to

out

GND)

T

tr, t

ÎÎ

Operating Temperature Range, All Package Types

A

Input Rise/Fall Time VCC = 2.0 V

f

ОООООООООООО

(Figure 1) V

ОООООООООООО

*When Vin = 50% VCC, ICC > 1mA

Parameter

V

= 4.5 V

CC

= 6.0 V

CC

Min

2.0

0

– 55

0

Î

0 0

Î

Max

6.0

V

CC

+ 125

No Limit*

ÎÎ

No Limit* No Limit*

ÎÎ

Unit

V

_C

ns

Î

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3

MC74HC14A

DC CHARACTERISTICS (Voltages Referenced to GND)

V

Symbol Parameter Condition −55 to 25°C ≤85°C ≤125°C Unit

VT+ max Maximum Positive−Going Input

Threshold Voltage

V

out

|I

out

= 0.1V

| ≤ 20mA

(Figure 3)

CC

V

2.0

3.0

4.5

6.0

VT+ min Minimum Positive−Going Input

Threshold Voltage (Figure 3)

V

out

|I

out

= 0.1V

| ≤ 20mA

2.0

3.0

4.5

6.0

VT− max Maximum Negative−Going Input

Threshold Voltage (Figure 3)

V

= VCC − 0.1V

out

|I

| ≤ 20mA

out

2.0

3.0

4.5

6.0

VT− min Minimum Negative−Going Input

Threshold Voltage (Figure 3)

V

= VCC − 0.1V

out

|I

| ≤ 20mA

out

2.0

3.0

4.5

6.0

VHmax Note 2

Maximum Hysteresis Voltage (Figure 3)

V

= 0.1V or VCC − 0.1V

out

|I

| ≤ 20mA

out

2.0

3.0

4.5

6.0

VHmin

Note 2

Minimum Hysteresis Voltage (Figure 3)

V

= 0.1V or VCC − 0.1V

out

|I

| ≤ 20mA

out

2.0

3.0

4.5

6.0

V

OH

Minimum High−Level Output Voltage

Vin ≤ VT− min |I

| ≤ 20mA

out

2.0

4.5

6.0

Vin ≤VT− min |I

V

OL

Maximum Low−Level Output Voltage

Vin ≥ VT+ max |I

| ≤ 20mA

out

|I

out

|I

out

| ≤ 2.4mA | ≤ 4.0mA | ≤ 5.2mA

3.0

4.5

6.0

2.0

4.5

6.0

Vin ≥VT+ max |I

I

in

Maximum Input Leakage

Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0

out

|I

out

|I

out

| ≤ 2.4mA | ≤ 4.0mA | ≤ 5.2mA

3.0

4.5

6.0

Current

I

CC

Maximum Quiescent Supply Current (per Package)

Vin = VCC or GND I

= 0mA

out

6.0 1.0 10 40

1. Information on typical parametric values along with frequency or heavy load considerations can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).

2. V

min > (V

H

min) − (VT− max); VHmax = (VT+ max) − (VT− min).

T+

Guaranteed Limit

1.50

2.15

3.15

4.20

1.0

1.5

2.3

3.0

0.9

1.4

2.0

2.6

0.3

0.5

0.9

1.2

1.20

1.65

2.25

3.00

0.20

0.25

0.40

0.50

1.9

4.4

5.9

2.48

3.98

5.48

0.1

0.26

1.50

2.15

3.15

4.20

0.95

1.45

2.25

2.95

0.95

1.45

2.05

2.65

0.3

0.5

0.9

1.2

1.20

1.65

2.25

3.00

0.20

0.25

0.40

0.50

1.9

4.4

5.9

2.34

3.84

5.34

0.1

0.33

1.50

2.15

3.15

4.20

0.95

1.45

2.25

2.95

0.95

1.45

2.05

2.65

0.3

0.5

0.9

1.2

1.20

1.65

2.25

3.00

0.20

0.25

0.40

0.50

1.9

4.4

5.9

2.20

3.70

5.20

0.1

0.40

V

mA

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4

MC74HC14A

AC CHARACTERISTICS (C

Symbol Parameter −55 to 25°C ≤85°C ≤125°C Unit

t

,

PLH

t

TLH

t

C

PHL

THL

in

Maximum Propagation Delay, Input A or B to Output Y (Figures 1 and 2)

,

Maximum Output Transition Time, Any Output (Figures 1 and 2)

Maximum Input Capacitance 10 10 10 pF

= 50pF, Input tr = tf = 6ns)

L

V

2.0

3.0

4.5

6.0

2.0

3.0

4.5

6.0

CC

V

Guaranteed Limit

75 30 15 13

75 27 15 13

95 40 19 16

95 32 19 16

110

55 22 19

110

36 22 19

ns

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON

Semiconductor High−Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

C

Power Dissipation Capacitance (Per Inverter)*

PD

* Used to determine the no−load dynamic power consumption: PD = CPD V

2

f + ICC VCC. For load considerations, see Chapter 2 of the

CC

22

pF

ON Semiconductor High−Speed CMOS Data Book (DL129/D).

t

f

r

V

CC

GND

INPUT A

90%

50%

10%

t

PLH

t

PHL

OUTPUT Y

90%

50%

10%

t

TLH

Figure 1. Switching Waveforms

TEST

POINT

OUTPUT

DEVICE

UNDER

TEST

CL*

*Includes all probe and jig capacitance

Figure 2. Test Circuit

t

THL

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5

MC74HC14A

S

4

3

(VT+)

VHtyp

2

(VT−)

1

, TYPICAL INPUT THRESHOLD VOLTAGE (VOLT

T

V

23456

VCC, POWER SUPPLY VOLTAGE (VOLTS)

VHtyp = (VT+ typ) − (VT− typ)

Figure 3. Typical Input Threshold, VT+, VT− versus Power Supply Voltage

YA

(a) A Schmitt−Trigger Squares Up Inputs With Slow Rise and Fall Times (b) A Schmitt−Trigger Offers Maximum Noise Immunity

V

H

V

in

CC

V

T+

V

T−

GND

V

H

V

in

V

CC

V

T+

V

T−

GND

V

OH

V

out

V

OL

V

out

V

OH

V

OL

Figure 4. Typical Schmitt−Trigger Applications

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6

−T−

SEATING PLANE

14 8

17

N

HG

MC74HC14A

PACKAGE DIMENSIONS

PDIP−14

CASE 646−06

ISSUE P

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

B

A

F

L

C

D

14 PL

0.13 (0.005)

K

J

M

3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

DIM MIN MAX MIN MAX

A 0.715 0.770 18.16 19.56 B 0.240 0.260 6.10 6.60 C 0.145 0.185 3.69 4.69 D 0.015 0.021 0.38 0.53 F 0.040 0.070 1.02 1.78 G 0.100 BSC 2.54 BSC H 0.052 0.095 1.32 2.41 J 0.008 0.015 0.20 0.38 K 0.115 0.135 2.92 3.43 L

0.290 0.310 7.37 7.87

M −−− 10 −−− 10

N 0.015 0.039 0.38 1.01

MILLIMETERSINCHES

__

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7

−T−

SEATING PLANE

MC74HC14A

PACKAGE DIMENSIONS

SOIC−14

CASE 751A−03

ISSUE H

NOTES:

1. DIMENSIONING AND TOLERANCING PER

−A−

14

1

8

−B−

7

P

7 PL

0.25 (0.010) B

M

G

F

J

D 14 PL

0.25 (0.010) A

M

T

R

X 45

C

K

S

B

S

_

M

SOLDERING FOOTPRINT*

7X

7.04

1

14X

0.58

14X

1.52

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

DIM MIN MAX MIN MAX

A 8.55 8.75 0.337 0.344 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 M 0 7 0 7

__ __

P 5.80 6.20 0.228 0.244 R 0.25 0.50 0.010 0.019

INCHESMILLIMETERS

1.27 PITCH

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

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8

MC74HC14A

PACKAGE DIMENSIONS

TSSOP−14

CASE 948G−01

ISSUE B

0.10 (0.004)

−T−

SEATING PLANE

14X REFK

S

U

T

S

N

0.25 (0.010)

U0.15 (0.006) T

S

2X L/2

0.10 (0.004) V

14

M

8

M

L

PIN 1 IDENT.

1

S

U0.15 (0.006) T

A

−V−

B

N

−U− F

7

DETAIL E

K

K1

J

J1

SECTION N−N

C

D

G

H

DETAIL E

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−.

DIM MIN MAX MIN MAX

A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C −−− 1.20 −−− 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.50 0.60 0.020 0.024 J 0.09 0.20 0.004 0.008

−W−

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC M 0 8 0 8

____

INCHESMILLIMETERS

SOLDERING FOOTPRINT*

7.06

1

14X

0.36

14X

1.26

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

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9

0.65

PITCH

14 8

1

Z

D

e

b

0.13 (0.005)

M

E

7

A

0.10 (0.004)

H

A

1

MC74HC14A

PACKAGE DIMENSIONS

SOEIAJ−14

CASE 965−01

ISSUE A

L

E

VIEW P

_

M

L

DETAIL P

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH OR PROTRUSIONS AND ARE

MEASURED AT THE PARTING LINE. MOLD FLASH

Q

1

c

OR PROTRUSIONS SHALL NOT EXCEED 0.15

(0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

MILLIMETERS

DIM MIN MAX MIN MAX

−−− 2.05 −−− 0.081

A

0.05 0.20 0.002 0.008

1

0.35 0.50 0.014 0.020

b

0.10 0.20 0.004 0.008

c

9.90 10.50 0.390 0.413

D

5.10 5.45 0.201 0.215

E

1.27 BSC 0.050 BSC

e

H

7.40 8.20 0.291 0.323

E

0.50 0.85 0.020 0.033

0.50 L

1.10 1.50 0.043 0.059

E

0

M

_

Q

0.70 0.90 0.028 0.035

1

−−− 1.42 −−− 0.056

Z

INCHES

10

_

10

0

_

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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MC74HC14A/D

10