The MC74HC139A is identical in pinout to the LS139. The device
inputs are compatible with standard CMOS outputs; with pull−up
resistors, they are compatible with LSTTL outputs.
This device consists of two independent 1−of−4 decoders, each of
which decodes a two−bit Address to one−of−four active−low outputs.
Active−low Selects are provided to facilitate the demultiplexing and
cascading functions. The demultiplexing function is accomplished by
using the Address inputs to select the desired device output, and
utilizing the Select as a data input.
Features
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 100 FETs or 25 Equivalent Gates
• Pb−Free Packages are Available*
16
16
16
16
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MARKING
DIAGRAMS
16
PDIP−16
N SUFFIX
1
1
1
1
CASE 648
SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
SOEIAJ−16
F SUFFIX
CASE 966
MC74HC139AN
AWLYYWWG
1
16
HC139AG
AWLYWW
1
16
HC
139A
ALYWG
G
1
16
74HC139A
ALYWG
1
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
A= Assembly Location
L, WL= Wafer Lot
Y, YY= Year
W, WW = Work Week
G= Pb−Free Package
G= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
MC74HC139A/D
MC74HC139A
SELECT
A0
A1
Y0
Y1
Y2
Y3
GND
1
a
2
a
3
a
4
a
a
6
a
7
a
8
16
15
14
13
125
11
10
9
V
CC
SELECT
A0
b
A1
b
Y0
b
Y1
b
Y2
b
Y3
b
b
Figure 1. Pin Assignment
FUNCTION TABLE
InputsOutputs
SelectA1A0Y0Y1 Y2Y3
HXXHHHH
LLLLHHH
LLHHLHH
LHLHHLH
LHHHHHL
X = don’t care
ADDRESS
INPUTS
ADDRESS
INPUTS
A0
A1
SELECT
A0
A1
SELECT
2
a
3
a
1
a
14
b
13
b
15
b
Figure 2. Logic Diagram
4
5
6
7
12
11
10
9
Y0
Y1
Y2
Y3
Y0
Y1
Y2
Y3
a
a
a
a
b
b
b
b
ACTIVE−LOW
OUTPUTS
PIN 16 = V
PIN 8 = GND
ACTIVE−LOW
OUTPUTS
CC
ORDERING INFORMATION
DevicePackageShipping
MC74HC139ANPDIP−162000 Units / Box
MC74HC139ANGPDIP−16
2000 Units / Box
(Pb−Free)
MC74HC139ADSOIC−1648 Units / Rail
MC74HC139ADGSOIC−16
48 Units / Rail
(Pb−Free)
MC74HC139ADR2SOIC−162500 Units / Reel
MC74HC139ADR2GSOIC−16
2500 Units / Reel
(Pb−Free)
MC74HC139ADTR2TSSOP−16*2500 Units / Reel
MC74HC139ADTR2GTSSOP−16*2500 Units / Reel
MC74HC139AFELSOEIAJ−162000 Units / Reel
MC74HC139AFELGSOEIAJ−16
2000 Units / Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
†
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2
MC74HC139A
Î
Î
Î
Î
Î
MAXIMUM RATINGS
SymbolParameterValueUnit
V
V
V
OUT
I
I
OUT
I
I
GND
T
STG
T
T
q
P
MSLMoisture SensitivityLevel 1
F
V
ESD
I
LATCHUP
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. IO absolute maximum rating must be observed.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
6. For high frequency or heavy load considerations, see Chapter 2the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
DC Supply Voltage(Referenced to GND)0.5 to 7.0V
CC
DC Input Voltage(Referenced to GND)1.5 to V
IN
1.5V
CC
DC Output Voltage(Referenced to GND) (Note 1)0.5 to VCC 0.5V
DC Input Current, per Pin20mA
IN
DC Output Current, per Pin25mA
DC Supply Current, VCC Pin50mA
CC
DC Ground Current per Ground Pin50mA
Storage Temperature Range65 to 150
Lead Temperature, 1 mm from Case for 10 Seconds260
Latchup PerformanceAbove VCC and Below GND at 85_C (Note 5)
78
112
148
750
500
450
2000
200
1000
300mA
_C
_C
_C
_C/W
mW
V
RECOMMENDED OPERATING CONDITIONS
SymbolParameterMinMaxUnit
V
VIN, V
T
tr, t
ÎÎ
DC Supply Voltage(Referenced to GND)
CC
DC Input Voltage, Output Voltage(Referenced to GND)
OUT
Operating Temperature, All Package Types
A
Input Rise and Fall TimeVCC = 2.0 V
f
(Figure 3)VCC = 4.5 V
ООООООООООООООООООО
VCC = 6.0 V
2.0
0
55
0
0
ÎÎÎ
0
6.0
V
CC
125
1000
500
ÎÎ
400
7. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level.
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3
V
V
_C
ns
Î
MC74HC139A
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
V
CC
SymbolParameterTest ConditionsV
V
ÎÎ
V
ÎÎ
V
ÎÎ
ÎÎ
V
ÎÎ
ÎÎÎОООООООÎОООООООО
I
ÎÎ
I
CC
Minimum High−Level Input
IH
Voltage
ООООООО
Maximum Low−Level Input
IL
Voltage
ООООООО
Minimum High−Level Output
OH
ООООООО
Voltage
ООООООО
Maximum Low−Level Output
OL
Voltage
ООООООО
Maximum Input Leakage
IN
Current
ООООООО
Maximum Quiescent Supply
Current (per Package)
V
= 0.1 V or VCC 0.1 V
OUT
|I
| 20 mA
OUT
ОООООООО
V
= 0.1 V or VCC 0.1 V
OUT
|I
| 20 mA
ОООООООО
OUT
VIN = VIH or V
ОООООООО
|I
| 20 mA
OUT
ОООООООО
VIN = VIH or V
VIN = VIH or V
|I
| 20 mA
ОООООООО
OUT
VIN = VIH or V
IL
IL|IOUT
|I
OUT
IL
IL|IOUT
|I
OUT
| 4.0 mA
| 5.2 mA
| 4.0 mA
| 5.2 mA
VIN = VCC or GND
ОООООООО
VIN = VCC or GND
I
= 0 mA
OUT
*55_C to 25_C 85_C125_C
2.0
4.5
Î
6.0
2.0
4.5
Î
6.0
2.0
Î
4.5
6.0
Î
4.5
6.0
2.0
4.5
Î
6.0
4.5
Î
6.0
6.0
Î
6.0
8. Information on typical parametric values can be found in the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
Guaranteed Limit
1.5
3.15
ÎÎÎ
4.2
0.5
1.35
ÎÎÎ
1.8
1.9
ÎÎÎ
4.4
5.9
ÎÎÎ
3.98
5.48
0.1
0.1
ÎÎÎ
0.1
0.26
ÎÎÎ
0.26
0.1
ÎÎÎ
4
1.5
3.15
Î
4.2
0.5
1.35
Î
1.8
1.9
Î
4.4
5.9
Î
3.84
5.34
0.1
0.1
Î
0.1
0.33
Î
0.33
1.0
Î
40
1.5
3.15
ÎÎ
4.2
0.5
1.35
ÎÎ
1.8
1.9
ÎÎ
4.4
5.9
ÎÎ
3.70
5.20
0.1
0.1
ÎÎ
0.1
0.40
ÎÎ
0.40
1.0
ÎÎ
160
Unit
V
V
V
V
mA
mA
AC ELECTRICAL CHARACTERISTICS (C
SymbolParameterV
t
,
PLH
t
PHL
ÎÎ
t
PLH
t
PHL
ÎÎ
t
TLH
ÎÎ
t
THL
ÎÎ
C
Maximum Propagation Delay, Select to Output Y
(Figures 1 and 3)
ОООООООООООООООО
,
Maximum Propagation Delay, Input A to Output Y
(Figures 2 and 3)
ОООООООООООООООО
,
Maximum Output Transition Time, Any Output
ОООООООООООООООО
(Figures 1 and 3)
ОООООООООООООООО
Maximum Input Capacitance
in
= 50 pF, Input tr = tf = 6.0 ns)
L
V
CC
Guaranteed Limit
*55_C to 25_C 85_C125_C
2.0
4.5
Î
6.0
2.0
4.5
Î
6.0
2.0
Î
4.5
6.0
Î
−
115
23
ÎÎÎ
20
115
23
ÎÎÎ
20
75
ÎÎÎ
15
13
ÎÎÎ
10
145
29
Î
25
145
29
Î
25
95
Î
19
16
Î
10
175
35
ÎÎ
30
175
35
ÎÎ
30
110
ÎÎ
22
19
ÎÎ
10
Unit
ns
ns
ns
pF
9. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High−Speed
CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
C
10. Used to determine the no−load dynamic power consumption: PD = CPD V
Semiconductor High−Speed CMOS Data Book (DL129/D).
Power Dissipation Capacitance (Per Decoder) (Note 10)55pF
PD
2
f ICC VCC. For load considerations, see the ON
CC
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4
MC74HC139A
t
t
SELECT
OUTPUT Y
f
90%
50%
10%
t
PHL
90%
50%
10%
t
THL
Figure 3. Switching Waveform
r
t
PLH
t
TLH
DEVICE
UNDER
V
GND
TEST
CC
OUTPUT Y
TEST POINT
OUTPUT
INPUT A
t
CL*
VALID
VALID
50%
PLH
50%
Figure 4. Switching Waveform
t
PHL
V
CC
GND
* Includes all probe and jig capacitance
Figure 5. Test Circuit
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5
MC74HC139A
PIN DESCRIPTIONS
ADDRESS INPUTS
A0
, A1a, A0b, A1b (Pins 2, 3, 14, 13)
a
Address inputs. These inputs, when the respective 1−of−4
decoder is enabled, determine which of its four active−low
outputs is selected.
CONTROL INPUTS
Select
, Selectb (Pins 1, 15)
a
Active−low select inputs. For a low level on this input, the
outputs for that particular decoder follow the Address
SELECT
A0
inputs. A high level on this input forces all outputs to a high
level.
OUTPUTS
Y0
a
− Y3a, Y0
− Y3b (Pins 4 − 7, 12, 11, 10, 9)
b
Active−low outputs. These outputs assume a low level
when addressed and the appropriate Select input is active.
These outputs remain high when not addressed or the
appropriate Select input is inactive.
Y0
Y1
Y2
A1
Y3
Figure 6. Expanded Logic Diagram
(1/2 of Device)
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6
MC74HC139A
PDIP−16
PACKAGE DIMENSIONS
N SUFFIX
CASE 648−08
ISSUE T
−A−
916
B
18
F
H
G
D
16 PL
0.25 (0.010)T
C
S
SEATING
−T−
PLANE
K
M
A
J
M
CASE 751B−05
L
SOIC−16
D SUFFIX
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
DIM MINMAXMINMAX
A 0.740 0.770 18.80 19.55
B 0.250 0.2706.356.85
C 0.145 0.1753.694.44
D 0.015 0.0210.390.53
F0.0400.701.021.77
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
S
_
F
J
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
MILLIMETERS
DIM MINMAXMINMAX
−−−2.05−−− 0.081
A
A
0.050.20 0.002 0.008
1
0.350.50 0.014 0.020
b
0.180.27 0.007 0.011
c
9.90 10.50 0.390 0.413
D
5.105.45 0.201 0.215
E
1.27 BSC0.050 BSC
e
H
7.408.20 0.291 0.323
E
0.500.85 0.020 0.033
L
L
1.101.50 0.043 0.059
E
0
M
_
Q
0.700.90 0.028 0.035
1
−−−0.78−−− 0.031
Z
INCHES
10
_
10
0
_
_
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9
MC74HC139A
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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For additional information, please contact your
local Sales Representative.
MC74HC139A/D
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