ON Semiconductor MC74HC139A Technical data

MC74HC139A

Dual 1−of−4 Decoder/
Demultiplexer

High−Performance Silicon−Gate CMOS

The MC74HC139A is identical in pinout to the LS139. The device
inputs are compatible with standard CMOS outputs; with pull−up
resistors, they are compatible with LSTTL outputs.

This device consists of two independent 1−of−4 decoders, each of
which decodes a two−bit Address to one−of−four active−low outputs.
Active−low Selects are provided to facilitate the demultiplexing and
cascading functions. The demultiplexing function is accomplished by
using the Address inputs to select the desired device output, and
utilizing the Select as a data input.

Features

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 mA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 100 FETs or 25 Equivalent Gates

• Pb−Free Packages are Available*

16

16

16

16

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MARKING

DIAGRAMS

16

PDIP−16

N SUFFIX

1

1

1

1

CASE 648

SOIC−16

D SUFFIX

CASE 751B

TSSOP−16
DT SUFFIX

CASE 948F

SOEIAJ−16

F SUFFIX
CASE 966

MC74HC139AN

AWLYYWWG

1

16

HC139AG
AWLYWW

1

16

HC

139A

ALYWG

G

1

16

74HC139A

ALYWG

1

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.

© Semiconductor Components Industries, LLC, 2005

June, 2005 − Rev. 9

1 Publication Order Number:

A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G = Pb−Free Package
G = Pb−Free Package
(Note: Microdot may be in either location)

ORDERING INFORMATION

See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.

MC74HC139A/D

MC74HC139A

SELECT

A0
A1

Y0
Y1
Y2

Y3

GND

1

a

2

a

3

a

4

a
a

6

a

7

a

8

16

15

14

13

125

11

10

9

V

CC

SELECT
A0

b

A1

b

Y0

b

Y1

b

Y2

b

Y3

b

b

Figure 1. Pin Assignment

FUNCTION TABLE

Inputs Outputs

Select A1 A0 Y0 Y1 Y2 Y3

HXXHHHH
LLLLHHH
LLHHLHH
LHLHHLH
LHHHHHL

X = don’t care

ADDRESS

INPUTS

ADDRESS

INPUTS

A0
A1

SELECT

A0
A1

SELECT

2

a

3

a

1

a

14

b

13

b

15

b

Figure 2. Logic Diagram

4
5
6
7

12
11
10
9

Y0
Y1

Y2
Y3

Y0
Y1
Y2
Y3

a
a

a
a

b
b
b
b

ACTIVE−LOW

OUTPUTS

PIN 16 = V
PIN 8 = GND

ACTIVE−LOW

OUTPUTS

CC

ORDERING INFORMATION

Device Package Shipping

MC74HC139AN PDIP−16 2000 Units / Box
MC74HC139ANG PDIP−16

2000 Units / Box

(Pb−Free)
MC74HC139AD SOIC−16 48 Units / Rail
MC74HC139ADG SOIC−16

48 Units / Rail

(Pb−Free)
MC74HC139ADR2 SOIC−16 2500 Units / Reel
MC74HC139ADR2G SOIC−16

2500 Units / Reel

(Pb−Free)
MC74HC139ADTR2 TSSOP−16* 2500 Units / Reel
MC74HC139ADTR2G TSSOP−16* 2500 Units / Reel
MC74HC139AFEL SOEIAJ−16 2000 Units / Reel
MC74HC139AFELG SOEIAJ−16

2000 Units / Reel

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

†

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2

MC74HC139A

Î

Î

Î

Î

Î

MAXIMUM RATINGS

Symbol Parameter Value Unit

V

V

V

OUT

I

I

OUT

I

I

GND

T

STG

T
T

q

P

MSL Moisture Sensitivity Level 1

F

V

ESD

I

LATCHUP

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.

1. IO absolute maximum rating must be observed.

2. Tested to EIA/JESD22−A114−A.

3. Tested to EIA/JESD22−A115−A.

4. Tested to JESD22−C101−A.

5. Tested to EIA/JESD78.

6. For high frequency or heavy load considerations, see Chapter 2the ON Semiconductor High−Speed CMOS Data Book (DL129/D).

DC Supply Voltage (Referenced to GND) 0.5 to 7.0 V

CC

DC Input Voltage (Referenced to GND) 1.5 to V

IN

1.5 V

CC

DC Output Voltage (Referenced to GND) (Note 1) 0.5 to VCC 0.5 V
DC Input Current, per Pin 20 mA

IN

DC Output Current, per Pin 25 mA
DC Supply Current, VCC Pin 50 mA

CC

DC Ground Current per Ground Pin 50 mA
Storage Temperature Range 65 to 150
Lead Temperature, 1 mm from Case for 10 Seconds 260

L

Junction Temperature Under Bias 150

J

Thermal Resistance PDIP

JA

SOIC

TSSOP

Power Dissipation in Still Air at 85_C PDIP

D

SOIC

TSSOP

Flammability Rating Oxygen Index: 30% − 35% UL 94 V−0 @ 0.125 in

R

ESD Withstand Voltage Human Body Model (Note 2)

Machine Model (Note 3)

Charged Device Model (Note 4)

Latchup Performance Above VCC and Below GND at 85_C (Note 5)

78
112
148

750
500
450

2000

200

1000

300 mA

_C
_C
_C

_C/W

mW

V

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

V

VIN, V

T

tr, t

ÎÎ

DC Supply Voltage (Referenced to GND)

CC

DC Input Voltage, Output Voltage (Referenced to GND)

OUT

Operating Temperature, All Package Types

A

Input Rise and Fall Time VCC = 2.0 V

f

(Figure 3) VCC = 4.5 V

ООООООООООООООООООО

VCC = 6.0 V

2.0
0

55

0
0

ÎÎÎ

0

6.0

V

CC

125

1000

500

ÎÎ

400

7. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level.

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3

V

V
_C
ns

Î