The MC74AC139/74ACT139 is a high–speed, dual 1–of–4
decoder/demultiplexer. The device has two independent decoders,
each accepting two inputs and providing four mutually–exclusive
active–LOW outputs. Each decoder has an active–LOW Enable input
which can be used as a data input for a 4–output demultiplexer. Each
half of the MC74AC139/74ACT139 can be used as a function
generator providing four minterms of two variables.
• Multifunctional Capability
• Two Completely Independent 1–of–4 Decoders
• Active LOW Mutually Exclusive Outputs
• Outputs Source/Sink 24 mA
• ′ACT139 Has TTL Compatible Inputs
V
E
CC
bA0bA1b
15161413121110
O
0bO1bO2bO3b
9
16
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1
16
1
16
1
DIP–16
N SUFFIX
CASE 648
SO–16
D SUFFIX
CASE 751B
TSSOP–16
DT SUFFIX
CASE 948F
2134567
E
A0aA1aO0aO1aO2aO
a
8
GND
3a
Figure 1. Pinout: 16–Lead Packages Conductors
(Top View)
PIN ASSIGNMENT
PINFUNCTION
A0, A
1
EEnable Inputs
O0–O
3
Address Inputs
Outputs
TRUTH TABLE
InputsOutputs
EA0A1O0O1O
HXXHHHH
LLLLHHH
LHLHLHH
LLHHHLH
LHHHHHL
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
See general marking information in the device marking
section on page 6 of this data sheet.
Semiconductor Components Industries, LLC, 2002
July, 2002 – Rev. 6
1Publication Order Number:
MC74AC139/D
MC74AC139, MC74ACT139
EA0A
1
DECODER a
O0O1O2O
E A
3
0A1
DECODER b
O0O1O2O
3
Figure 2. Logic Symbol
E
a
A0aA
1a
E
b
A0bA
1b
0
0a
0
0
1a
2a
0
3a
NOTE: This diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation
delays.
Figure 3. Logic Diagram
FUNCTIONAL DESCRIPTION
The MC74AC139/74ACT139 is a high–speed dual
1–of–4 decoder/demultiplexer. The device has two
independent decoders, each of which accepts two binary
weighted inputs (A
) and provides four mutually
0–A1
exclusive active–LOW outputs (O0–O3). Each decoder has
an active–LOW enable (E). When E is HIGH all outputs are
forced HIGH. The enable can be used as the data input for
a 4–output demultiplexer application. Each half of the
MC74AC139/74ACT139 generates all four minterms of
two variables. These four minterms are useful in some
applications, replacing multiple gate functions as shown in
Figure 4, and thereby reducing the number of packages
required in a logic network.
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0
0b
0
E
A
0
A
1
E
A
0
A
1
E
A
0
A
1
E
A
0
A
1
0
1b
2b
0
3b
E
A
O
0
0
A
1
E
A
0
O
1
A
1
E
A
O
0
2
A
1
E
O
A
3
0
A
1
O
0
O
1
O
2
O
3
Figure 4. Gate Functions (Each Half)
2
MC74AC139, MC74ACT139
r,f
′AC Devices except Schmitt Inputs
In ut Rise and Fall Time (Note 2)
MAXIMUM RATINGS*
SymbolParameterValueUnit
V
CC
V
IN
V
OUT
I
IN
I
OUT
I
CC
T
stg
*Maximum Ratings are those values beyond which damage to the device may occur . Functional operation should be restricted to the Recom-
mended Operating Conditions.
RECOMMENDED OPERATING CONDITIONS
SymbolParameterMinTypMaxUnit
V
CC
VIN, V
OUT
tr, t
f
tr, t
f
T
J
T
A
I
OH
I
OL
1. VIN from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.
from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2. V
IN
DC Supply Voltage (Referenced to GND)–0.5 to +7.0V
DC Input Voltage (Referenced to GND)–0.5 to VCC +0.5V
DC Output Voltage (Referenced to GND)–0.5 to VCC +0.5V
DC Input Current, per Pin±20mA
DC Output Sink/Source Current, per Pin±50mA
DC VCC or GND Current per Output Pin±50mA
Storage Temperature–65 to +150°C
Supply Voltage
DC Input Voltage, Output Voltage (Ref. to GND)0–V
′AC2.05.06.0
′ACT4.55.05.5
CC
V
V
VCC @ 3.0 V–150–
Input Rise and Fall Time (Note 1)
′
p
p
VCC @ 4.5 V–40–ns/V
VCC @ 5.5 V–25–
Input Rise and Fall Time (Note 2)
′ACT Devices except Schmitt Inputs
VCC @ 4.5 V–10–
VCC @ 5.5 V–8.0–
ns/V
Junction Temperature (PDIP)––140°C
Operating Ambient Temperature Range–402585°C
Output Current – High–––24mA
Output Current – Low––24mA
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3
MC74AC139, MC74ACT139
V
IH
ugee
g
o
CC
0
IL
auoee
g
o
CC
0
OH
ugee
OUT
50
g
V
OL
auoee
OUT
50
g
V
IINMaximum In ut
A
V
V
GND
ICCMaximum Quiescent
A
V
V
GND
VCC*
Fi
oagaoeay
oagaoeay
oagaoeay
oagaoeay
DC CHARACTERISTICS
74AC74AC
TA =
–40°C to
TA = +25°C
CC
SymbolParameter
V
IH
Minimum High Level
Input Voltage
(V)
3.01.52.12.1V
4.52.253.153.15Vor VCC – 0.1 V
TypGuaranteed Limits
5.52.753.853.85
V
IL
Maximum Low Level
Input Voltage
3.01.50.90.9V
4.52.251.351.35Vor VCC – 0.1 V
5.52.751.651.65
V
OH
Minimum High Level
Output Voltage
3.02.992.92.9
4.54.494.44.4V
5.55.495.45.4
3.0–2.562.46
4.5–3.863.76
5.5–4.864.76–24 mA
V
OL
Maximum Low Level
Output Voltage
3.00.0020.10.1
4.50.0010.10.1V
5.50.0010.10.1
3.0–0.360.44
4.5–0.360.44
5.5–0.360.4424 mA
I
IN
I
OLD
I
OHD
I
CC
Maximum Input
Leakage Current
†Minimum Dynamic
Output Current
Maximum Quiescent
Supply Current
5.5–±0.1±1.0
5.5––75mAV
5.5–––75mAV
5.5–8.080
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
NOTE: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC.
+85°C
UnitConditions
= 0.1 V
OUT
= 0.1 V
OUT
I
= –50 A
OUT
*VIN = VIL or V
–12 mA
I
OH
I
OUT
–24 mA
= 50 A
*VIN = VIL or V
12 mA
I
OL
I
OLD
OHD
IN
=
24 mA
,
CC
= 1.65 V Max
= 3.85 V Min
=
or
CC
IH
IH
AC CHARACTERISTICS (For Figures and Waveforms – See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
t
PLH
t
PHL
t
PLH
t
PHL
*Voltage Range 3.3 V is 3.3 V ±0.3 V.
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
SymbolParameter
Propagation Delay
An to O
n
Propagation Delay
An to O
n
Propagation Delay
En to O
n
Propagation Delay
En to O
n
*
(V)
3.34.08.011.53.513
5.03.06.58.52.59.5
3.33.07.0102.511
5.02.55.57.52.08.5
3.34.59.5123.513
5.03.57.08.53.010
3.34.08.0103.011
5.02.56.07.52.58.5
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4
74AC74AC
TA = –40°C
TA = +25°C
C
= 50 pF
L
to +85°C
= 50 pF
C
L
MinTypMaxMinMax
Unit
ns3–6
ns3–6
ns3–6
ns3–6
g.
No.
MC74AC139, MC74ACT139
V
IH
ugee
V
IL
auoee
V
OH
ugee
V
OUT
50
g
I
OL
auoee
V
OUT
50
g
I
IINMaximum In ut
A
V
V
GND
ICCMaximum Quiescent
A
V
V
GND
VCC*
Fi
Pro agation Delay
Pro agation Delay
Pro agation Delay
Pro agation Delay
DC CHARACTERISTICS
TA = +25°C
CC
Symbol Parameter
V
IH
Minimum High Level
Input Voltage
V
IL
Maximum Low Level
Input Voltage
V
OH
Minimum High Level
Output Voltage
(V)
4.51.52.02.0
5.51.52.02.0
4.51.50.80.8
5.51.50.80.8
4.54.494.44.4
5.55.495.45.4
4.5–3.863.76V
5.5–4.864.76
V
OL
Maximum Low Level
Output Voltage
4.50.0010.10.1
5.50.0010.10.1
4.5–0.360.44V
5.5–0.360.44
I
IN
I
I
OLD
I
OHD
I
CC
CCT
Maximum Input
Leakage Current
5.5–±0.1±1.0
Additional Max. ICC/Input5.50.6–1.5mAVI = VCC – 2.1 V
†Minimum Dynamic
Output Current
Maximum Quiescent
Supply Current
5.5––75mAV
5.5–––75mAV
5.5–8.080
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
TypGuaranteed Limits
74ACT74ACT
TA =
–40°C to
+85°C
UnitConditions
V
= 0.1 V
OUT
or VCC – 0.1 V
V
= 0.1 V
OUT
or VCC – 0.1 V
I
= –50 A
OUT
*VIN = VIL or V
OH
I
OUT
–24 mA
–24 mA
= 50 A
*VIN = VIL or V
OL
I
OLD
OHD
IN
=
24 mA
24 mA
,
CC
= 1.65 V Max
= 3.85 V Min
=
or
CC
IH
IH
AC CHARACTERISTICS(For Figures and Waveforms – See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74ACT74ACT
TA = –40°C
SymbolParameter
t
PLH
t
PHL
t
PLH
t
PHL
Propagation Delay
An to O
n
Propagation Delay
An to O
n
Propagation Delay
En to O
n
Propagation Delay
En to O
n
TA = +25°C
C
= 50 pF
*
(V)
L
MinTypMaxMinMax
5.01.56.08.51.59.5ns3–6
5.01.56.09.51.510.5ns3–6
5.02.57.010.02.011.0ns3–6
5.02.07.09.51.510.5ns3–6
to +85°C
= 50 pF
C
L
Unit
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
CAPACITANCE
Value
SymbolParameter
C
IN
C
PD
Input Capacitance4.5pFVCC = 5.0 V
Power Dissipation Capacitance40pFVCC = 5.0 V
Typ
UnitTest Conditions
g.
No.
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5
MC74AC139, MC74ACT139
MARKING DIAGRAMS
DIP–16SO–16TSSOP–16EIAJ–16
MC74AC139N
AWLYYWW
MC74ACT139N
AWLYYWW
AC139
AWLYWW
ACT139
AWLYWW
A= Assembly Location
WL, L= Wafer Lot
YY, Y= Year
WW, W = Work Week
AC
139
ALYW
ACT
139
ALYW
74AC139
ALYW
74ACT139
ALYW
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6
–A–
916
B
18
F
S
H
G
D
16 PL
0.25 (0.010)T
–A–
169
18
G
–T–
SEATING
PLANE
D
16 PL
0.25 (0.010)A
M
T
MC74AC139, MC74ACT139
PACKAGE DIMENSIONS
PDIP–16
N SUFFIX
16 PIN PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
C
SEATING
–T–
PLANE
K
M
A
J
M
16 PIN PLASTIC SOIC PACKAGE
CASE 751B–05
–B–
K
S
B
8 PLP
0.25 (0.010)B
C
S
L
SO–16
D SUFFIX
ISSUE J
M
R
M
S
X 45
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
DIM MINMAXMINMAX
A 0.740 0.770 18.80 19.55
B 0.250 0.2706.356.85
C 0.145 0.1753.694.44
D 0.015 0.0210.390.53
F 0.0400.701.021.77
G0.100 BSC2.54 BSC
M
J
H0.050 BSC1.27 BSC
J 0.008 0.0150.210.38
K 0.110 0.1302.803.30
L 0.295 0.3057.507.74
M0 10 0 10
S 0.020 0.0400.511.01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
1
c
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
MILLIMETERS
DIM MINMAXMIN MAX
---2.05--- 0.081
A
A
0.050.20 0.002 0.008
1
0.350.50 0.014 0.020
b
0.180.27 0.007 0.011
c
9.90 10.50 0.390 0.413
D
5.105.45 0.201 0.215
E
1.27 BSC0.050 BSC
e
H
7.408.20 0.291 0.323
E
0.500.85 0.020 0.033
L
L
1.101.50 0.043 0.059
E
0
M
Q
0.700.90 0.028 0.035
1
---0.78--- 0.031
Z
INCHES
10
10
0
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8
Notes
MC74AC139, MC74ACT139
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9
Notes
MC74AC139, MC74ACT139
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10
Notes
MC74AC139, MC74ACT139
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11
MC74AC139, MC74ACT139
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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MC74AC139/D
12
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