ON Semiconductor MC10EP52, MC100EP52 Technical data

MC10EP52, MC100EP52

3.3V / 5V ECL Differential Data and Clock D Flip-Flop

Description

The MC10EP/100EP52 is a differential data, differential clock D flip−flop. The device is pin and functionally equivalent to the EL52 device.

Data enters the master portion of the flip−flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EP52 allow the device to also be used as a negative edge triggered device.

The EP52 employs input clamping circuitry so that under open input conditions (pulled down to V stable.

The 100 Series contains temperature compensation.

Features

• 330 ps Typical Propagation Delay

• Maximum Frequency u 4 GHz Typical

• PECL Mode: V

• NECL Mode: V

= 3.0 V to 5.5 V with VEE = 0 V

= 0 V with VEE = −3.0 V to −5.5 V

• Open Input Default State

• Safety Clamp on Inputs

• Q Output Will Default LOW with Inputs Open or at V

• Pb−Free Packages are Available

) the outputs of the device will remain

SOIC−8

D SUFFIX

CASE 751

TSSOP−8

DT SUFFIX

CASE 948R

DFN8

MN SUFFIX

CASE 506AA

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MARKING

DIAGRAMS*

HEP52

ALYW

HP52

ALYWG

5T MG

KEP52

ALYW

KP52

ALYWG

3OMG

August, 2008 − Rev. 7

H = MC10 A = Assembly Location K = MC100 L = Wafer Lot 5T = MC10 Y = Year 3O = MC100 W = Work Week

= Date Code

(Note: Microdot may be in either location)

*For additional marking information, refer to

Application Note AND8002/D.

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet.

1 Publication Order Number:

G = Pb−Free Package

MC10EP52/D

MC10EP52, MC100EP52

CLK

Flip-Flop

78Q

QCLK

Figure 1. 8−Lead Pinout (Top View) and Logic Diagram

Table 3. ATTRIBUTES

Characteristics Value

Internal Input Pulldown Resistor

Internal Input Pullup Resistor N/A

ESD Protection Human Body Model

Charged Device Model

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb Pkg Pb−Free Pkg

Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in

Transistor Count 155 Devices

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

Table 1. PIN DESCRIPTION

CLK*, CLK

D*, D* ECL Data Input

Q, Q

EP (DFN8 only) Thermal exposed pad

* Pins will default LOW when left open.

FUNCTION

ECL Clock Inputs

ECL Data Outputs

Positive Supply

Negative Supply

must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open.

Table 2. TRUTH TABLE

L H

CLK

Z Z

Z = LOW to HIGH Transition

75 kW

Machine Model

SOIC−8

TSSOP−8

DFN8

Level 1 Level 1 Level 1

> 4 kV

> 200 V

> 2 kV

Level 1 Level 3 Level 1

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MC10EP52, MC100EP52

Table 4. MAXIMUM RATINGS

Symbol Parameter Condition 1 Condition 2 Rating Unit

out

stg

sol

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)

PECL Mode Power Supply VEE = 0 V 6 V

NECL Mode Power Supply VCC = 0 V −6 V

PECL Mode Input Voltage NECL Mode Input Voltage

Output Current Continuous

VEE = 0 V V

= 0 V

Surge

VI v V VI w V

−6

100

V V

mA mA

VBB Sink/Source ± 0.5 mA

Operating Temperature Range −40 to +85 °C

Storage Temperature Range −65 to +150 °C

Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

SOIC−8 SOIC−8

190 130

°C/W °C/W

Thermal Resistance (Junction−to−Case) Standard Board SOIC−8 41 to 44 °C/W

Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

TSSOP−8 TSSOP−8

185 140

°C/W °C/W

Thermal Resistance (Junction−to−Case) Standard Board TSSOP−8 41 to 44 °C/W

Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

Wave Solder Pb

Pb−Free

<2 to 3 sec @ 248°C <2 to 3 sec @ 260°C

DFN8 DFN8

129

265 265

°C/W °C/W

°C

Thermal Resistance (Junction−to−Case) (Note 2) DFN8 35 to 40 °C/W

Table 5. 10EP DC CHARACTERISTICS, PECL V

= 3.3 V, VEE = 0 V (Note 3)

−40°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit

IHCMR

Power Supply Current 20 34 44 20 35 45 20 37 47 mA

Output HIGH Voltage (Note 4) 2165 2290 2415 2230 2355 2480 2290 2415 2540 mV

Output LOW Voltage (Note 4) 1365 1490 1615 1430 1555 1680 1490 1615 1740 mV

Input HIGH Voltage (Single−Ended) 2090 2415 2155 2480 2215 2540 mV

Input LOW Voltage (Single−Ended) 1365 1690 1430 1755 1490 1815 mV

Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 5)

Input HIGH Current 150 150 150

Input LOW Current 0.5 0.5 0.5

2.0 3.3 2.0 3.3 2.0 3.3 V

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.

3. Input and output parameters vary 1:1 with V

4. All loading with 50 W to V

5. V

min varies 1:1 with VEE, V

IHCMR

input signal.

− 2.0 V.

IHCMR

. VEE can vary +0.3 V to −2.2 V.

max varies 1:1 with VCC. The V

range is referenced to the most positive side of the differential

IHCMR

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MC10EP52, MC100EP52

Table 6. 10EP DC CHARACTERISTICS, PECL V

= 5.0 V, VEE = 0 V (Note 6)

−40°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit

IHCMR

Power Supply Current 20 34 44 20 35 45 20 37 47 mA

Output HIGH Voltage (Note 7) 3865 3990 4115 3930 4055 4180 3990 4115 4240 mV

Output LOW Voltage (Note 7) 3065 3190 3315 3130 3255 3380 3190 3315 3440 mV

Input HIGH Voltage (Single−Ended) 3790 4115 3855 4180 3915 4240 mV

Input LOW Voltage (Single−Ended) 3065 3390 3130 3455 3190 3515 mV

Input HIGH Voltage Common Mode

2.0 5.0 2.0 5.0 2.0 5.0 V Range (Differential Configuration) (Note 8)

Input HIGH Current 150 150 150

Input LOW Current 0.5 0.5 0.5

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

6. Input and output parameters vary 1:1 with V

7. All loading with 50 W to V

8. V

min varies 1:1 with VEE, V

IHCMR

input signal.

− 2.0 V.

IHCMR

Table 7. 10EP DC CHARACTERISTICS, NECL V

. VEE can vary +2.0 V to −0.5 V.

max varies 1:1 with VCC. The V

= 0 V, V

range is referenced to the most positive side of the differential

IHCMR

= −5.5 V to −3.0 V (Note 9)

−40°C 25°C 85°C

Symbol Characteristic Min Ty p Max Min Typ Max Min Typ Max Unit

IHCMR

Power Supply Current 20 34 44 20 35 45 20 37 47 mA

Output HIGH Voltage (Note 10) −1135 −1010 −885 −1070 −945 −820 −1010 −885 −760 mV

Output LOW Voltage (Note 10) −1935 −1810 −1685 −1870 −1745 −1620 −1810 −1685 −1560 mV

Input HIGH Voltage (Single−Ended) −1210 −885 −1145 −820 −1085 −760 mV

Input LOW Voltage (Single−Ended) −1935 −1610 −1870 −1545 −1810 −1485 mV

Input HIGH Voltage Common Mode

VEE+2.0 0.0 VEE+2.0 0.0 VEE+2.0 0.0 V Range (Differential Configuration) (Note 11)

Input HIGH Current 150 150 150

Input LOW Current 0.5 0.5 0.5

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

9. Input and output parameters vary 1:1 with V

10.All loading with 50 W to V

11. V

min varies 1:1 with VEE, V

IHCMR

input signal.

− 2.0 V.

IHCMR

max varies 1:1 with VCC. The V

range is referenced to the most positive side of the differential

IHCMR

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ON Semiconductor MC10EP52, MC100EP52 Technical data

Specifications and Main Features

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