MC10EP52, MC100EP52
3.3V / 5V ECL Differential
Data and Clock D Flip-Flop
Description
The MC10EP/100EP52 is a differential data, differential clock D
flip−flop. The device is pin and functionally equivalent to the EL52
device.
Data enters the master portion of the flip−flop when the clock is
LOW and is transferred to the slave, and thus the outputs, upon a
positive transition of the clock. The differential clock inputs of the
EP52 allow the device to also be used as a negative edge triggered
device.
The EP52 employs input clamping circuitry so that under open input
conditions (pulled down to V
stable.
The 100 Series contains temperature compensation.
Features
• 330 ps Typical Propagation Delay
• Maximum Frequency u 4 GHz Typical
• PECL Mode: V
• NECL Mode: V
= 3.0 V to 5.5 V with VEE = 0 V
CC
= 0 V with VEE = −3.0 V to −5.5 V
CC
• Open Input Default State
• Safety Clamp on Inputs
• Q Output Will Default LOW with Inputs Open or at V
• Pb−Free Packages are Available
) the outputs of the device will remain
EE
EE
8
1
SOIC−8
D SUFFIX
CASE 751
8
1
TSSOP−8
DT SUFFIX
CASE 948R
DFN8
MN SUFFIX
CASE 506AA
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MARKING
DIAGRAMS*
8
HEP52
ALYW
G
1
8
HP52
ALYWG
G
1
G
5T MG
14
8
KEP52
ALYW
G
1
8
KP52
ALYWG
G
1
G
3OMG
14
© Semiconductor Components Industries, LLC, 2008
August, 2008 − Rev. 7
H = MC10 A = Assembly Location
K = MC100 L = Wafer Lot
5T = MC10 Y = Year
3O = MC100 W = Work Week
M
= Date Code
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
1 Publication Order Number:
G = Pb−Free Package
MC10EP52/D
MC10EP52, MC100EP52
1
D
2
D
3
45
CLK
D
Flip-Flop
78Q
6
V
CC
QCLK
V
EE
Figure 1. 8−Lead Pinout (Top View) and Logic Diagram
Table 3. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor
Internal Input Pullup Resistor N/A
ESD Protection Human Body Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb Pkg Pb−Free Pkg
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Transistor Count 155 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 1. PIN DESCRIPTION
PIN
CLK*, CLK
D*, D* ECL Data Input
Q, Q
V
CC
V
EE
EP (DFN8 only) Thermal exposed pad
* Pins will default LOW when left open.
FUNCTION
*
ECL Clock Inputs
ECL Data Outputs
Positive Supply
Negative Supply
must be connected to a sufficient
thermal conduit. Electrically connect to
the most negative supply (GND) or
leave unconnected, floating open.
Table 2. TRUTH TABLE
D
L
H
CLK
Z
Z
Z = LOW to HIGH Transition
75 kW
Machine Model
SOIC−8
TSSOP−8
DFN8
Level 1
Level 1
Level 1
> 4 kV
> 200 V
> 2 kV
Level 1
Level 3
Level 1
Q
L
H
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2
MC10EP52, MC100EP52
Table 4. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
CC
V
EE
V
I
I
out
I
BB
T
A
T
stg
q
JA
q
JC
q
JA
q
JC
q
JA
T
sol
q
JC
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)
PECL Mode Power Supply VEE = 0 V 6 V
NECL Mode Power Supply VCC = 0 V −6 V
PECL Mode Input Voltage
NECL Mode Input Voltage
Output Current Continuous
VEE = 0 V
V
= 0 V
CC
Surge
VI v V
VI w V
CC
EE
6
−6
50
100
V
V
mA
mA
VBB Sink/Source ± 0.5 mA
Operating Temperature Range −40 to +85 °C
Storage Temperature Range −65 to +150 °C
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
SOIC−8
SOIC−8
190
130
°C/W
°C/W
Thermal Resistance (Junction−to−Case) Standard Board SOIC−8 41 to 44 °C/W
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
TSSOP−8
TSSOP−8
185
140
°C/W
°C/W
Thermal Resistance (Junction−to−Case) Standard Board TSSOP−8 41 to 44 °C/W
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
Wave Solder Pb
Pb−Free
<2 to 3 sec @ 248°C
<2 to 3 sec @ 260°C
DFN8
DFN8
129
84
265
265
°C/W
°C/W
°C
Thermal Resistance (Junction−to−Case) (Note 2) DFN8 35 to 40 °C/W
Table 5. 10EP DC CHARACTERISTICS, PECL V
= 3.3 V, VEE = 0 V (Note 3)
CC
−40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
I
EE
V
OH
V
OL
V
IH
V
IL
V
IHCMR
I
IH
I
IL
Power Supply Current 20 34 44 20 35 45 20 37 47 mA
Output HIGH Voltage (Note 4) 2165 2290 2415 2230 2355 2480 2290 2415 2540 mV
Output LOW Voltage (Note 4) 1365 1490 1615 1430 1555 1680 1490 1615 1740 mV
Input HIGH Voltage (Single−Ended) 2090 2415 2155 2480 2215 2540 mV
Input LOW Voltage (Single−Ended) 1365 1690 1430 1755 1490 1815 mV
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 5)
Input HIGH Current 150 150 150
Input LOW Current 0.5 0.5 0.5
2.0 3.3 2.0 3.3 2.0 3.3 V
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Input and output parameters vary 1:1 with V
4. All loading with 50 W to V
5. V
min varies 1:1 with VEE, V
IHCMR
input signal.
CC
− 2.0 V.
IHCMR
. VEE can vary +0.3 V to −2.2 V.
CC
max varies 1:1 with VCC. The V
range is referenced to the most positive side of the differential
IHCMR
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3
MC10EP52, MC100EP52
Table 6. 10EP DC CHARACTERISTICS, PECL V
= 5.0 V, VEE = 0 V (Note 6)
CC
−40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
I
EE
V
OH
V
OL
V
IH
V
IL
V
IHCMR
Power Supply Current 20 34 44 20 35 45 20 37 47 mA
Output HIGH Voltage (Note 7) 3865 3990 4115 3930 4055 4180 3990 4115 4240 mV
Output LOW Voltage (Note 7) 3065 3190 3315 3130 3255 3380 3190 3315 3440 mV
Input HIGH Voltage (Single−Ended) 3790 4115 3855 4180 3915 4240 mV
Input LOW Voltage (Single−Ended) 3065 3390 3130 3455 3190 3515 mV
Input HIGH Voltage Common Mode
2.0 5.0 2.0 5.0 2.0 5.0 V
Range (Differential Configuration)
(Note 8)
I
IH
I
IL
Input HIGH Current 150 150 150
Input LOW Current 0.5 0.5 0.5
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. Input and output parameters vary 1:1 with V
7. All loading with 50 W to V
8. V
min varies 1:1 with VEE, V
IHCMR
input signal.
CC
− 2.0 V.
IHCMR
Table 7. 10EP DC CHARACTERISTICS, NECL V
. VEE can vary +2.0 V to −0.5 V.
CC
max varies 1:1 with VCC. The V
= 0 V, V
CC
EE
range is referenced to the most positive side of the differential
IHCMR
= −5.5 V to −3.0 V (Note 9)
−40°C 25°C 85°C
Symbol Characteristic Min Ty p Max Min Typ Max Min Typ Max Unit
I
EE
V
OH
V
OL
V
IH
V
IL
V
IHCMR
Power Supply Current 20 34 44 20 35 45 20 37 47 mA
Output HIGH Voltage (Note 10) −1135 −1010 −885 −1070 −945 −820 −1010 −885 −760 mV
Output LOW Voltage (Note 10) −1935 −1810 −1685 −1870 −1745 −1620 −1810 −1685 −1560 mV
Input HIGH Voltage (Single−Ended) −1210 −885 −1145 −820 −1085 −760 mV
Input LOW Voltage (Single−Ended) −1935 −1610 −1870 −1545 −1810 −1485 mV
Input HIGH Voltage Common Mode
VEE+2.0 0.0 VEE+2.0 0.0 VEE+2.0 0.0 V
Range (Differential Configuration)
(Note 11)
I
IH
I
IL
Input HIGH Current 150 150 150
Input LOW Current 0.5 0.5 0.5
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
9. Input and output parameters vary 1:1 with V
10.All loading with 50 W to V
11. V
min varies 1:1 with VEE, V
IHCMR
input signal.
CC
− 2.0 V.
IHCMR
.
CC
max varies 1:1 with VCC. The V
range is referenced to the most positive side of the differential
IHCMR
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4
MC10EP52, MC100EP52
Table 8. 100EP DC CHARACTERISTICS, PECL V
= 3.3 V, VEE = 0 V (Note 12)
CC
−40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
I
EE
V
OH
V
OL
V
IH
V
IL
V
IHCMR
I
IH
I
IL
Power Supply Current 20 34 44 20 35 45 20 37 47 mA
Output HIGH Voltage (Note 13) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV
Output LOW Voltage (Note 13) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mV
Input HIGH Voltage (Single−Ended) 2075 2420 2075 2420 2075 2420 mV
Input LOW Voltage (Single−Ended) 1355 1675 1355 1675 1355 1675 mV
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 14)
Input HIGH Current 150 150 150
Input LOW Current 0.5 0.5 0.5
2.0 3.3 2.0 3.3 2.0 3.3 V
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
12.Input and output parameters vary 1:1 with V
13.All loading with 50 W to V
14.V
min varies 1:1 with VEE, V
IHCMR
input signal.
CC
− 2.0 V.
IHCMR
Table 9. 100EP DC CHARACTERISTICS, PECL V
. VEE can vary +0.3 V to −2.2 V.
CC
max varies 1:1 with VCC. The V
= 5.0 V, VEE = 0 V (Note 15)
CC
range is referenced to the most positive side of the differential
IHCMR
−40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
I
EE
V
OH
V
OL
V
IH
V
IL
V
IHCMR
I
IH
I
IL
Power Supply Current 20 34 44 20 35 45 20 37 47 mA
Output HIGH Voltage (Note 16) 3855 3980 4105 3855 3980 4105 3855 3980 4105 mV
Output LOW Voltage (Note 16) 3055 3180 3305 3055 3180 3305 3055 3180 3305 mV
Input HIGH Voltage (Single−Ended) 3775 4120 3775 4120 3775 4120 mV
Input LOW Voltage (Single−Ended) 3055 3375 3055 3375 3055 3375 mV
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 17)
Input HIGH Current 150 150 150
Input LOW Current 0.5 0.5 0.5
2.0 5.0 2.0 5.0 2.0 5.0 V
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
15.Input and output parameters vary 1:1 with V
16.All loading with 50 W to V
17.V
min varies 1:1 with VEE, V
IHCMR
input signal.
CC
− 2.0 V.
IHCMR
. VEE can vary +2.0 V to −0.5 V.
CC
max varies 1:1 with VCC. The V
range is referenced to the most positive side of the differential
IHCMR
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5
MC10EP52, MC100EP52
Table 10. 100EP DC CHARACTERISTICS, NECL V
= 0 V, V
CC
= −5.5 V to −3.0 V (Note 18)
EE
−40°C 25°C 85°C
Symbol Characteristic Min Ty p Max Min Typ Max Min Typ Max Unit
I
EE
V
OH
V
OL
V
IH
V
IL
V
IHCMR
I
IH
I
IL
Power Supply Current 20 34 44 20 35 45 20 37 47 mA
Output HIGH Voltage (Note 19) −1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895 mV
Output LOW Voltage (Note 19) −1945 −1820 −1695 −1945 −1820 −1695 −1945 −1820 −1695 mV
Input HIGH Voltage (Single−Ended) −1225 −880 −1225 −880 −1225 −880 mV
Input LOW Voltage (Single−Ended) −1945 −1625 −1945 −1625 −1945 −1625 mV
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 20)
Input HIGH Current 150 150 150
Input LOW Current 0.5 0.5 0.5
VEE+2.0 0.0 VEE+2.0 0.0 VEE+2.0 0.0 V
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
18.Input and output parameters vary 1:1 with V
19.All loading with 50 W to V
20.V
min varies 1:1 with VEE, V
IHCMR
input signal.
CC
− 2.0 V.
IHCMR
Table 11. AC CHARACTERISTICS V
.
CC
max varies 1:1 with VCC. The V
= 0 V; VEE = −3.0 V to −5.5 V or VCC = 3.0 V to 5.5 V; V
CC
range is referenced to the most positive side of the differential
IHCMR
= 0 V (Note 21)
EE
−40°C 25°C 85°C
Symbol Characteristic Min Ty p Max Min Typ Max Min Typ Max Unit
V
OUTpp
Output Voltage Amplitude @ 3.0 GHz
630 750 610 730 520 640 GHz
(Figure 2)
t
,
PLH
t
PHL
t
S
t
H
t
JITTER
Propagation Delay to
Output Differential
CLK, CLK
Setup Time
Hold Time
CLOCK Random Jitter (RMS)
−>Q, Q 250 300 350 280 330 380 310 360 410
50
0
50
0
0
50
0.2 1 0.2 1 0.2 1 ps
(Figure 2)
V
PP
Input Voltage Swing
150 800 1200 150 800 1200 150 800 1200 mV
(Differential Configuration)
t
r
t
f
Output Rise/Fall Times
(20% − 80%) Q, Q
70 11 0 170 80 120 180 90 130 200
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
21.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to V
CC
− 2.0 V.
ps
ps
ps
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6
MC10EP52, MC100EP52
0.9
0.8
0.7
(mV)
0.6
0.5
OUTpp
V
0.4
0.3
0.2
0.1
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
Driver
Device
5 V
3.3 V
FREQUENCY (MHz)
Figure 2. F
QD
Q D
Zo = 50 W
Zo = 50 W
max
Typical
Receiver
Device
50 W 50 W
V
VTT = VCC − 2.0 V
TT
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
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7
MC10EP52, MC100EP52
ORDERING INFORMATION
Device Package Shipping
MC10EP52D SO−8 98 Units / Rail
MC10EP52DG SO−8
(Pb−Free)
MC10EP52DR2 SO−8 2500 Tape & Reel
MC10EP52DR2G SO−8
(Pb−Free)
MC10EP52DT TSSOP−8 100 Units / Rail
MC10EP52DTG TSSOP−8
(Pb−Free)
MC10EP52DTR2 TSSOP−8 2500 Tape & Reel
MC10EP52DTR2G TSSOP−8
(Pb−Free)
MC10EP52MNR4 DFN8 1000 / Tape & Reel
MC10EP52MNR4G DFN8
(Pb−Free)
MC100EP52D SO−8 98 Units / Rail
MC100EP52DG SO−8
(Pb−Free)
MC100EP52DR2 SO−8 2500 Tape & Reel
MC100EP52DR2G SO−8
(Pb−Free)
MC100EP52DT TSSOP−8 100 Units / Rail
MC100EP52DTG TSSOP−8
(Pb−Free)
MC100EP52DTR2 TSSOP−8 2500 Tape & Reel
MC100EP52DTR2G TSSOP−8
(Pb−Free)
MC100EP52MNR4 DFN8 1000 / Tape & Reel
MC100EP52MNR4G DFN8
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
98 Units / Rail
2500 Tape & Reel
100 Units / Rail
2500 Tape & Reel
1000 / Tape & Reel
98 Units / Rail
2500 Tape & Reel
100 Units / Rail
2500 Tape & Reel
1000 / Tape & Reel
†
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8
MC10EP52, MC100EP52
Resource Reference of Application Notes
AN1405/D − ECL Clock Distribution Techniques
AN1406/D − Designing with PECL (ECL at +5.0 V)
AN1503/D −
AN1504/D − Metastability and the ECLinPS Family
AN1568/D − Interfacing Between LVDS and ECL
AN1672/D − The ECL Translator Guide
AND8001/D − Odd Number Counters Design
AND8002/D − Marking and Date Codes
AND8020/D − Termination of ECL Logic Devices
AND8066/D − Interfacing with ECLinPS
AND8090/D − AC Characteristics of ECL Devices
ECLinPSt I/O SPiCE Modeling Kit
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9
−Y−
−Z−
MC10EP52, MC100EP52
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AH
−X−
B
H
A
58
1
4
G
D
0.25 (0.010) Z
M
S
Y
0.25 (0.010)
C
SEATING
PLANE
SXS
M
0.10 (0.004)
M
Y
K
N
X 45
_
M
J
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
MILLIMETERS
DIMAMIN MAX MIN MAX
4.80 5.00 0.189 0.197
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0 8 0 8
____
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
INCHES
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
0.6
0.024
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
4.0
0.155
1.270
0.050
SCALE 6:1
mm
ǒ
inches
Ǔ
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10
0.10 (0.004)
−T−
SEATING
PLANE
MC10EP52, MC100EP52
PACKAGE DIMENSIONS
TSSOP−8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R−02
ISSUE A
8x REFK
S
U0.15 (0.006) T
2X L/2
85
L
PIN 1
IDENT
S
U0.15 (0.006) T
0.10 (0.004) V
1
4
A
M
B
−U−
−V−
S
U
T
S
0.25 (0.010)
M
F
DETAIL E
C
D
G
DETAIL E
−W−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
DIM MIN MAX MIN MAX
A 2.90 3.10 0.114 0.122
B 2.90 3.10 0.114 0.122
C 0.80 1.10 0.031 0.043
D 0.05 0.15 0.002 0.006
F 0.40 0.70 0.016 0.028
G 0.65 BSC 0.026 BSC
K 0.25 0.40 0.010 0.016
L 4.90 BSC 0.193 BSC
M 0 6 0 6
____
INCHESMILLIMETERS
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11
MC10EP52, MC100EP52
PACKAGE DIMENSIONS
DFN8
CASE 506AA−01
ISSUE D
8 X
REFERENCE
2 X
SEATING
PLANE
PIN ONE
2 X
C0.10
C0.08
C0.10
A1
8 X
D
A
B
E
C0.10
TOP VIEW
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
MILLIMETERS
DIM MIN MAX
A 0.80 1.00
A1 0.00 0.05
A3 0.20 REF
b 0.20 0.30
D 2.00 BSC
D2 1.10 1.30
E 2.00 BSC
E2 0.70 0.90
e 0.50 BSC
K 0.20 −−−
L 0.25 0.35
A
SIDE VIEW
(A3)
C
D2
e/2
1
4
e
L
E2
K
8
5
8 X
0.10 C
b
0.05 C
A
BB
NOTE 3
BOTTOM VIEW
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MC10EP52/D
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