ON Semiconductor MC10EP32, MC100EP32 Technical data

MC10EP32, MC100EP32

3.3V / 5VECL 2 Divider

The MC10/100EP32 is an integrated 2 divider with differential

CLK inputs.

The V this device only. For single−ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple V and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, V

The reset pin is asynchronous and is asserted on the rising edge. Upon power−up, the internal flip−flops will attain a random state; the reset allows for the synchronization of multiple EP32’s in a system.

The 100 Series contains temperature compensation.

• 350 ps Typical Propagation Delay

• Maximum Frequency > 4 GHz Typical (Figure 3)

• PECL Mode Operating Range:

VCC = 3.0 V to 5.5 V with VEE = 0 V

• NECL Mode Operating Range:

VCC = 0 V with VEE = −3.0 V to −5.5 V

• Open Input Default State

• Safety Clamp on Inputs

• Q Output Will Default LOW with Inputs Open or at V

• Pb−Free Package is Available

pin, an internally generated voltage supply, is available to

should be left open.

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SOIC−8

D SUFFIX

CASE 751

TSSOP−8

DT SUFFIX

CASE 948R

H = MC10 K = MC100 A = Assembly Location

MARKING DIAGRAMS*

HEP32

ALYW

HP32

ALYW

L = Wafer Lot Y = Year W = Work Week

KEP32

ALYW

KP32

ALYW

*For additional marking information, refer to

Application Note AND8002/D.

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet.

 Semiconductor Components Industries, LLC, 2004

June, 2004 − Rev. 7

1 Publication Order Number:

MC10EP32/D

MC10EP32, MC100EP32

RESET

CLK

2

CLK

Figure 1. 8−Lead Pinout (Top View) and Logic

Diagram

78Q

Table 1. PIN DESCRIPTION

Pin Function

CLK, CLK* ECL Clock Inputs Reset* ECL Asynchronous Reset V

Q, Q ECL Data Outputs V

*Pins will default LOW when left open.

Reference Voltage Output

Positive Supply Negative Supply

Table 2. TRUTH TABLE

CLK CLK RESET Q Q

X Z

Z = LOW to HIGH Transition Z = HIGH to LOW Transition F = Divide by 2 Function

X Z

Z L

L F

H F

CLK

RESET

Figure 2. Timing Diagram

Table 3. ATTRIBUTES

Characteristics Value

Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor N/A ESD Protection Human Body Model

Machine Model

Charged Device Model Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 78 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

> 4 kV

> 200 V

> 2 kV

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MC10EP32, MC100EP32

Table 4. MAXIMUM RATINGS

Symbol Parameter Condition 1 Condition 2 Rating Unit

out

stg



sol

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously . If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.

PECL Mode Power Supply VEE = 0 V 6 V NECL Mode Power Supply VCC = 0 V −6 V PECL Mode Input Voltage

NECL Mode Input Voltage Output Current Continuous

VEE = 0 V V

= 0 V

Surge

VI  V VI  V

CC EE

−6 50

100

V V

mA VBB Sink/Source ± 0.5 mA Operating Temperature Range −40 to +85 °C Storage Temperature Range −65 to +150 °C Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

SOIC−8 SOIC−8

190 130

°C/W °C/W

Thermal Resistance (Junction−to−Case) Standard Board SOIC−8 41 to 44 °C/W Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

TSSOP−8 TSSOP−8

185 140

°C/W °C/W

Thermal Resistance (Junction−to−Case) Standard Board TSSOP−8 41 to 44 °C/W Wave Solder <2 to 3 sec @ 248°C 265 °C

Table 5. 10EP DC CHARACTERISTICS, PECL V

= 3.3 V, VEE = 0 V (Note 2)

−40°C 25°C 85°C

Symbol Characteristic

IHCMR

Power Supply Current 23 30 37 23 30 37 23 30 37 mA Output HIGH Voltage (Note 3) 2165 2290 2415 2230 2355 2480 2290 2415 2540 mV Output LOW Voltage (Note 3) 1365 1490 1615 1430 1555 1680 1490 1615 1740 mV Input HIGH Voltage (Single−Ended) 2090 2415 2155 2480 2215 2540 mV Input LOW Voltage (Single−Ended) 1365 1690 1430 1755 1490 1815 mV Output Voltage Reference 1790 1890 1990 1855 1955 2055 1915 2015 2115 mV Input HIGH Voltage Common Mode

Range (Differential Configuration) (Note 4) Input HIGH Current 150 150 150 A Input LOW Current 0.5 0.5 0.5 A

Min Typ Max Min Typ Max Min Typ Max

2.0 3.3 2.0 3.3 2.0 3.3 V

Unit

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.

2. Input and output parameters vary 1:1 with V

3. All loading with 50  to V

4. V

min varies 1:1 with VEE, V

IHCMR

input signal.

− 2.0 V.

IHCMR

. VEE can vary +0.3 V to −2.2 V.

max varies 1:1 with VCC. The V

range is referenced to the most positive side of the differential

IHCMR

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MC10EP32, MC100EP32

Table 6. 10EP DC CHARACTERISTICS, PECL V

= 5.0 V, VEE = 0 V (Note 5)

−40°C 25°C 85°C

Symbol Characteristic

IHCMR

Power Supply Current 23 30 37 23 30 37 23 30 37 mA Output HIGH Voltage (Note 6) 3865 3990 4115 3930 4055 4180 3990 4115 4240 mV Output LOW Voltage (Note 6) 3065 3190 3315 3130 3255 3380 3190 3315 3440 mV Input HIGH Voltage (Single−Ended) 3790 4115 3855 4180 3915 4240 mV Input LOW Voltage (Single−Ended) 3065 3390 3130 3455 3190 3515 mV Output Voltage Reference 3490 3590 3690 3555 3655 3755 3615 3715 3815 mV Input HIGH Voltage Common Mode Range

(Differential Configuration) (Note 7) Input HIGH Current 150 150 150 A Input LOW Current 0.5 0.5 0.5 A

Min Typ Max Min Typ Max Min Typ Max

2.0 5.0 2.0 5.0 2.0 5.0 V

Unit

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

5. Input and output parameters vary 1:1 with V

6. All loading with 50  to V

7. V

min varies 1:1 with VEE, V

IHCMR

input signal.

− 2.0 V.

IHCMR

. VEE can vary +2.0 V to −0.5 V.

max varies 1:1 with VCC. The V

range is referenced to the most positive side of the differential

IHCMR

Table 7. 10EP DC CHARACTERISTICS, NECL V

= 0 V; VEE = −5.5 V to −3.0 V (Note 8)

−40°C 25°C 85°C

Symbol Characteristic

Power Supply Current 23 30 37 23 30 37 23 30 37 mA

Min Typ Max Min Typ Max Min Typ Max

Unit

VOH Output HIGH Voltage (Note 9) −1135 −1010 −885 −1070 −945 −820 −1010 −885 −760 mV V

IHCMR

Output LOW Voltage (Note 9) −1935 −1810 −1685 −1870 −1745 −1620 −1810 −1685 −1560 mV Input HIGH Voltage (Single−Ended) −1210 −885 −1145 −820 −1085 −760 mV Input LOW Voltage (Single−Ended) −1935 −1610 −1870 −1545 −1810 −1485 mV Output Voltage Reference −1510 −1410 −1310 −1445 −1345 −1245 −1385 −1285 −1185 mV Input HIGH Voltage Common Mode

VEE+2.0 0.0 VEE+2.0 0.0 VEE+2.0 0.0 V Range (Differential Configuration) (Note 10)

Input HIGH Current 150 150 150 A Input LOW Current 0.5 0.5 0.5 A

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

8. Input and output parameters vary 1:1 with V

9. All loading with 50  to V

10.V

min varies 1:1 with VEE, V

IHCMR

input signal.

− 2.0 V.

IHCMR

max varies 1:1 with VCC. The V

range is referenced to the most positive side of the differential

IHCMR

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