ON Semiconductor MC10E137, MC100E137 Technical data

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MC10E137, MC100E137

5 VECL 8-Bit Ripple Counter

Description

The MC10E/100E137 is a very high speed binary ripple counter. The

two least significant bits were designed with very fast edge rates while the more significant bits maintain standard ECLinPS™ output edge rates. This allows the counter to operate at very high frequencies while maintaining a moderate power dissipation level.

The device is ideally suited for multiple frequency clock generation as well as a counter in a high performance ATE time measurement board.

Both asynchronous and synchronous enables are available to maximize the device’s flexibility for various applications. The asynchronous enable input, A_Start, when asserted enables the counter while overriding any synchronous enable signals. The E137 features XORed enable inputs, EN1 and EN2, which are synchronous to the CLK input. When only one synchronous enable is asserted the counter becomes disabled on the next CLK transition; all outputs remain in the previous state poised for the other synchronous enable or A_Start to be asserted to re-enable the counter. Asserting both synchronous enables causes the counter to become enabled on the next transition of the CLK. If EN1 (or EN2) and CLK edges are coincident, sufficient delay has been inserted in the CLK path (to compensate for the XOR gate delay and the internal D-flip flop setup time) to insure that the synchronous enable signal is clocked correctly, hence, the counter is disabled.

All input pins left open will be pulled LOW via an input pulldown resistor. Therefore, do not leave the differential CLK inputs open. Doing so causes the current source transistor of the input clock gate to become saturated, thus upsetting the internal bias regulators and jeopardizing the stability of the device.

The asynchronous Master Reset resets the counter to an all zero state upon assertion.

The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to

0.5 mA. When not used, VBB should be left open.

The 100 Series contains temperature compensation.

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PLCC−28

FN SUFFIX

CASE 776

MARKING DIAGRAM*

MCxxxE137FNG

AWLYYWW

xxx = 10 or 100 A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package

*For additional marking information, refer to

Application Note AND8002/D.

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet.

Features

• Differential Clock Input and Data Output Pins

• V

Output for Single-Ended Use

• Synchronous and Asynchronous Enable Pins

• Asynchronous Master Reset

• PECL Mode Operating Range: V

with VEE = 0 V

• NECL Mode Operating Range: V

with VEE = −4.2 V to −5.7 V

= 4.2 V to 5.7 V

= 0 V

• Internal Input 50 kW Pull−down Resistors

• Transistor Count = 330 devices

*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting

Techniques Reference Manual, SOLDERRM/D.

November, 2006 − Rev. 8

• ESD Protection: Human Body Model: > 2 kV,

Machine Model: > 200 V

• Meets or Exceeds JEDEC Spec EIA/JESD78 IC

Latchup Test

• Moisture Sensitivity Level: Pb = 1; Pb−Free = 3

For Additional Information, see Application Note AND8003/D

• Flammability Rating: UL 94 V−0 @ 0.125 in,

Oxygen Index: 28 to 34

• Pb−Free Packages are Available*

1 Publication Order Number:

MC10E137/D

MC10E137, MC100E137

CCO

A_Start

EN1

EN2

CLK

Q7 Q6

* All VCC and V

Warning: All VCC, V

Pinout: 28-Lead PLCC

(Top View)

CCO

pins are tied together on the die.

CCO

, and VEE pins must be externally

CCO

connected to Power Supply to guarantee proper operation.

Figure 1. 28−Lead Pinout

Q1Q1Q0

Table 1. PIN DESCRIPTION

PIN FUNCTION

CLK, CLK

Q0-Q7, Q0-Q7

A_Start

EN1, EN2

VCC, V

CCO

ECL Differential Clock Inputs

ECL Differential Q Outputs

ECL Asynchronous Enable Input

ECL Synchronous Enable Inputs

Asynchronous Master Reset

Reference Voltage Output

Positive Supply

Negative Supply

11109

CCO

A_Start

EN1 EN2

CLK CLK

Q0 Q0 Q1 Q1

Q7 Q7

CLK CLK

Q Q

CLK CLK

Q Q

CLK CLK

Q Q

Figure 2. Logic Diagram

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MC10E137, MC100E137

Table 2. SEQUENTIAL TRUTH TABLE

Function EN1 EN2 A_Start MR CLK Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0

Reset X X X H X L L L L L L L L

Count L

L L

Stop H

Asynch Start H

H L

Count L

L L

Stop L

Synch Start H

H H

Stop H

Count L

L L

Reset X X X H X L L L L L L L L

Z = Low to High Transition

L L L

L L

L L L

H H

H H H

L L

L L L

L L

H H H

L L L

L L

L L L

L L

L L L

L L

L L L

L L

L L L

L L

L L L

Z Z Z

Z Z

Z Z Z

Z Z

Z Z Z

Z Z

Z Z Z

L L L

L L

L L L

L L

L L L

L L

L L L

L L

L L L

L L

L L L

L L

L L L

L L

L L L

L L

L L L

L L

L L L

L L

L L L

L L

L L L

L L

L L L

L L

L L L

L H H

H H

H H H

H H

H H H

L L L

L L

H H H

L L

H H

H H H

L H H

H H

L H

H H

L H H

H H

L L

Table 3. MAXIMUM RATINGS

Symbol Parameter Condition 1 Condition 2 Rating Unit

out

stg

sol

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

PECL Mode Power Supply VEE = 0 V 8 V

NECL Mode Power Supply VCC = 0 V −8 V

PECL Mode Input Voltage NECL Mode Input Voltage

Output Current Continuous

VEE = 0 V VCC = 0 V

Surge

VI v V VI w V

−6

100

V V

mA mA

Operating Temperature Range 0 to +85 °C

Storage Temperature Range −65 to +150 °C

Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

PLCC−28 PLCC−28

63.5

43.5

°C/W °C/W

Thermal Resistance (Junction−to−Case) Standard Board PLCC−28 22 to 26 °C/W

PECL Operating Range NECL Operating Range

Wave Solder Pb

Pb−Free

4.2 to 5.7

−5.7 to −4.2

265 265

V V

°C

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