EVBUM2516/D
150 W High Power Density
Adapter Using SJ Si
MOSFETs Evolution Board
User Manual
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Contents
This evaluation board user manual describes the 150 W
High Power Density Adapter and its main parameters like
efficiency, no−load input power consumption, EMI
signature, transient responses, etc. The evaluation board is
dedicated to present ON Semiconductor’s high performance
controllers. High Power Density design is enabled when
using these controllers and higher switching frequency.
Higher efficiency can be achieved by using GaN HEMT
devices instead of Silicon Super−junction MOSFETs.
The evaluation board comprising of the PFC boost
converter operated in the critical conduction mode (CrCM)
and LLC power stage. The PFC front stage is driven by
NCP1615, assures unity power factor and low input current
THD. The LLC stage operates @ 260 to 300 kHz @ nominal
load and it’s managed by the NCP1399 high performance
current mode LLC controller. Super−junction Si MOSFETs
(like FCMT199N60) can be assembled as primary side
power switches. The CV/CC controller NCP4353A ensures
output voltage regulation.
Above mentioned controllers are placed on the Control
Module. Secondary side utilizes synchronous rectifier (SR)
from NCP4305 or NCP4306 family composed with
NVMFS5C645NL 4mW 60V Power MOSFET. Whole SR
stage is implemented on the daughter card for easier main
power board PCB design. The discrete or integrated LLC
resonant thanks implementations can be used in one board
with few changes thanks to universal design.
EVAL BOARD USER’S MANUAL
This evaluation board manual focuses mainly on short
description of adapter operation principles and connections.
For more detailed information please refer to datasheets of
individual part.
Key Features
• Wide Input Voltage Range
• High Power Density, High Efficiency
• Low No−load Power Consumption
• X2 Capacitor Discharge Function
• Near Unity Power Factor
• Overload Protection, Thermal Protection
• Low Mains Operation Protection
• Secondary Short Circuit Protected
• Regulated Output Under any Conditions
• Capability to Implement Off−mode for
Table 1. GENERAL PARAMETERS
Device Applications Input Voltage
NCP1615
NCP1399
NCP4305
NCP4353
Efficiency Standby Power
Up to 94.15%
© Semiconductor Components Industries, LLC, 2016
October, 2017 − Rev. 6
Notebook
Adaptors,
Ac – dc converters
for consumer
electronics
150 mW @ 230
Vac
Normal Output
Voltage / Current
90 – 265 Vac
Operating
Temperature
0 – 50 °C Passive cooling
19 Vdc / 8 A
9 A max limit
Cooling Topology Board size
1 Publication Order Number:
Output Power V
150 W < 250 mV @ Full load
PFC CrCM
LLC + SR
Ripple
OUT
116 x 55 x 18 mm
EVBUM2516/D
EVBUM2516/D
Figure 1. 150 W High Power Density Adapter − Schematic Of The Power−Board (1/2)
Figure 2. 150 W High Power Density Adapter − Schematic Of The Power−Board (2/2)
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Figure 3. High Power Density Adapter − Schematic Of The Control Module 1/2
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Figure 4. High Power Density Adapter − Schematic Of The Control Module 2/2
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Figure 5. 150 W High Power Density Adapter − Schematic Of The Switch Module With Si MOSFETs
Figure 6. 150 W High Power Density Adapter − Schematic of Synchronous Rectifier Module
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Figure 7. 150 W High Power Density Adapter − Arrangement Of Modules
DETAILED DESCRIPTIONS OF THE EVALUATION
BOARD
Adapter modular conceptions − The demo−board is
constructed using a main power board plus daughtercards or
modules, which are showed in Figure 7. This assists
evaluation and allows the user to exchange daughtercards
for experimentation. This comprehensive type of
construction helps to reduce PCB area, thus increases power
density and also allows reducing number of PCB layers. All
modules PCBs are designed as 2−layers with 35um or 70um
thin copper plating. PCBs with 70um copper plating are used
for SR and Power Switch Modules. The lowest PCB
manufacturing and assembly cost has been achieved thanks
to this construction.
The input of the converter is protected by the varistor
R7. A differential mode lighting surge protection has not
been optimized. The fuse F1 is 4A time−lag type fuse to
withstand the inrush current. The inrush current limiting
NTC thermistor is not used in this demo−board (Figure
NO TAG.)
The EMI filter consists from the common−mode power
line chokes L1 and L2, X2−capacitor C1, and three
Y−capacitors CY1 − CY3. CY1 is complemented with
ferrite beads L6 at one terminal. The center of CY2 and CY3
capacitors is connected to the PE terminal through ferrite
bead L7. The PE−A terminal should be connected to the
PE−B terminal by a wire to reduce EMI signature. Pre−filter
arranged by polypropylene capacitors C5, C6 and
differential mode inductor L3 (Figure NO TAG.) is used for
further reduction of EMI signature.
The HV Start−up and X2 discharge capability – both
primary controllers are equipped with High Voltage
Start−up current sources (NCP1615, NCP1399). PFC
High−voltage Start−up (HVSU) is assured via serial circuit
R3, R5, D5, and two diodes D1 and D2. Diodes are shared
for PFC and LLC HVSU. LLC HVSU is joined through
same serial circuit R4, R6 and D6. To avoid influence
between controllers, HV pin of both controllers are
separated via mentioned serial circuitries.
Additionally for NCP1615 – the PFC controller has X2
discharge function. The X2−capacitor is discharged after
disconnecting power cord from the line.
The PFC front stage implements critical conduction
mode PFC boost converter and consists mainly the bulk
capacitor C8, which is decoupled at high frequencies (HF)
with multi−layer ceramic capacitors (MLCC) C9−11, PFC
inductor L4, rectifying diode D10 and power switch (Figure
NO TAG.), which is located on Power Switch Module
(Figure 5.). The PFC controller NCP1615 senses inductor
current directly as a voltage drop on resistors R13, R14.
These resistors are connected directly to Control Module,
where the PFC controller is located. These resistors define
maximum PFC front stage peak current. The PFC controller
U1 (NCP1615) uses CS/ZCD for inductor peak current
sensing and zero current condition or valley detection. Zero
current detection is guaranteed by PFC coil auxiliary
winding voltage, which is rectified with D9 and this signal
is connected to Control Module via parallel RC circuit R10
and C7. Input voltage is observed at HV pin, which also
serves for input voltage sensing and BROWN−OUT
protection. The bulk capacitor voltage is fed into PFC
controller through set of four resistors R15, R16, R17 and
R18. Necessary PFC compensation circuitries and
components are located on the Control Module board. The
PFC OK status is transferred via network of C9, R13, C13
and R18 to LLC controller, which is subsequently enabled
after PFC provides PFC OK status. For more details, please
refer to NCP1615 datasheet.
Power Switch Module with Si SJ MOSFETs is showed
in Figures 5, 15, 16. Power Switch Module consists of power
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FET devices and additional components which are
necessary for correct operation.
Power Switch Module is designed for Silicon Power
MOFETs in small SMD package so−called the Power88. In
Figure 6 is Power Switch module schematic, where M2 is
the low side switch of PFC front stage, M4 and M5 create
LLC half−bridge stage. C3, C4, C5, C6 and C7 are HF
decoupling MLCC capacitors with same function as afore
mentioned. Q1, Q2, Q6 forms emitter followers with Vcc
decoupling capacitors C1, C2 and C41. Emitter followers
provide buffering of driving signal in case of need – they can
be assembled on purpose. Paralleled resistor−diode pairs
(D14–R29, D1–R1, D2–R6) set switching slopes of
MOSFETs and this way improving EMI signature.
Exchange of Power Switch Modules Important notes
– Power Switch Modules can be exchanged, but specific
conditions must be satisfied due to operation differences:
Silicon MOSFETs requirements:
• Higher magnetizing current (compare to GaN) to
achieve ZVS ³ Lower magnetizing inductance
because of higher output capacitance
• Maximum needed Dead−time up to 500ns
• Maximum switching Frequency is limited from to 420
– 450kHz @Light−load − it is given by used MOSFET
parameters
• Dedicated NCP1399 setting is needed for Si MOSFETs
board option
GaN FETs requirements:
• Lower magnetizing current (compare to Si MOSFETs)
to achieve ZVS ³ Higher magnetizing inductance, less
conduction losses
• Maximum needed Dead−time ~200ns
• Frequency is limited by IC controller
• Dedicated NCP1399 setting is needed for GaN
MOSFETs board option
To summarize: the LLC controller has to be replaced and
air gap in the LLC transformer increased when Switching
Module is changed from GaN to ³ Si type.
Control Module – (Figures NO TAG, NO TAG, 13, 14)
integrates the PFC controller NCP1615, the LLC controller
NCP1399 and secondary side CV/CC controller NCP4353
in one PCB. Control module is designed in such a way, that
each component is placed to its dedicated controller as close
as possible. Another design strategy was to move all signal
processing components to the Control Module, except the
high voltage circuitries for example bulk voltage feedback
divider. Module also contains two optocouplers, first one
output is used for voltage feedback loop. IC1 – NCP4353
(Figure NO TAG) senses output voltage using resistor
divider R43, R44 and R45 and transfers this information via
optocoupler U3 to primary side, to the U2 – NCP1399,
which regulates switching frequency according to feedback
and current sense signals. Second optocoupler is dedicated
to output overvoltage protection (OVP). As soon as output
voltage reaches ~21V, optocoupler U4 pulls up OVP/OTP
pin of U2 and activates OVP. Output OVP level and response
is defined by zener diode D5, resistors R30, R31 and
capacitor C21.
The LLC primary stage is formed by half−bridge, which
is located on the Power switch Module, split resonant tank
capacitors C15−C16, clamping diode D13, resonant
inductor L5 (in case of discrete resonant transformer
implementation) and transformer TR1. The resonant
capacitor voltage divided down by R20, R21, C12, C13,
C14, C19, C20, C21, C22, D11 and D12 and provides
information about transformer current for NCP1399.
Divider serves as current feedback loop and also sets adapter
output current limit.
The Synchronous Rectifier Module (Figures 6, 17, 18)
consists of two Single N−Channel SO−8FL Logic Level
60V MOSFETs Q1 and Q2, two synchronous rectifier (SR)
controllers IC1−2 NCP43080 (or similar part from
NCP430x family) and HF decoupling MLCC capacitors
C3−8. RC snubber circuits, composed as R1−C1 and R2−C2,
are connected across the drain and the source of each
MOSFET, to protect them against voltage spikes. C9−11 and
R6−7 are components use to filtering and HF decoupling
supply voltage for both SR controllers. R4 (R9) and R5 (R8)
serve to set minimum ON and minimum OFF switching
times of SR controller. Automatic Light Load and Disable
mode (LLD pin) is input modulates the driver clamp level
and/or turns the driver off during light load conditions. This
feature helps to reduce No−load consumption and improves
Light−load efficiency. In Figure 6, the Light−Load
Detection Circuitry is formed by resistors R11–14, ceramic
capacitors C12, C13 and diodes D1−2. If there is a certain
reason to not use LLD feature, use R3 (R10) zero ohms to
disable it. Then in this situation Light−Load Detection
Circuitry doesn’t have to be assembled. When using
NCP4306, R3 (R10) resistors can set specific timing of
Automatic LLD or disable it fully and external Light−Load
Detection Circuitry is not needed anymore. For more detail
please see each device specific datasheet.
The regulation of output voltage is ensured by the
regulator IC1–NCP4353 (see Figure NO TAG), which
provides integrated voltage feedback regulation, replacing
traditional shunt regulator. The device is capable of
detecting “no−load” conditions and inserts the power supply
into a low consumption OFF−
current regulation loop in addition to voltage regulation.
These possibilities are included in design of PCBs, but
demo−board is not utilized them. The optocoupler U3 is
driven via resistor R29, which determines the feedback loop
gain. Resistor R46 biases the NCP4353 in case that there is
no current flowing through the optocoupler U3. The voltage
feedback loop compensation network is created by resistors
R39, R42 capacitors C24, C25. The value of output voltage
is set up by voltage divider comprised of resistors R43, R44,
R45.
mode. IC1 also includes a
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Coupling between primary and secondary is ensured
by the Y−capacitor CY1, which is connected between
secondary ground and primary bulk voltage. Similar
functionality have CY2 and CY3, which are placed between
input terminals (L, N) and their center point is connected to
PE earth terminal. PE−A and PE−B allow making the
PBC Layout
The PCB is made as a double layer FR4 board with 35mm
copper cladding.
connection between secondary ground GND and input earth
terminal (PE). The connection should be made by awg 18 or
0.75 mm
2
wire with optionally threaded ferrite bead.
This configuration of CY1−3 helps to improve the EMI
signature of the converter and pass legislation EMI emission
limits.
Figure 8. Evaluation Board − Top Side Components
Figure 9. Evaluation Board − Bottom Side Components
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