ON Semiconductor ESD7421, SZESD7421 User Manual

ESD7421, SZESD7421

ESD Protection Diode

Micro−Packaged Diodes for ESD Protection

The ESD7421 is designed to protect voltage sensitive components
from ESD. Excellent clamping capability, low leakage, and fast
response time provide best in class protection on designs that are
exposed to ESD. Because of its small size, it is suited for use in cellular
phones, automotive sensors, infotainment, MP3 players, digital
cameras and many other applications where board space comes at a
premium.

Specification Features

• Low Capacitance 0.3 pF

• Low Clamping Voltage

• Low Leakage 100 nA

• Response Time is < 1 ns

• IEC61000−4−2 Level 4 ESD Protection

• SZ Prefix for Automotive and Other Applications Requiring Unique

Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

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Pin 1

XDFN2

(SOD−882)

CASE 711AM

5 = Specific Device Code
M = Date Code
G = Pb−Free Package

Pin 2

MARKING
DIAGRAM

5 M

G

MAXIMUM RATINGS

Rating Symbol Value Unit

IEC 61000−4−2 (ESD) Contact

Total Power Dissipation on FR−5 Board
(Note 1) @ TA = 25°C
Thermal Resistance, Junction−to−Ambient

Junction and Storage Temperature Range TJ, T

Lead Solder Temperature − Maximum
(10 Second Duration)

Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.

1. FR−5 = 1.0 x 0.75 x 0.62 in.

Air

°PD°

R

q

T

JA

stg

L

±12
±15

300

400

−55 to +150 °C

260 °C

kV

mW

°C/W

ORDERING INFORMATION

Device Package Shipping

ESD7421N2T5G XDFN2

(Pb−Free)

SZESD7421N2T5G XDFN2

(Pb−Free)

†For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.

8000 /

Tape & Reel

8000 /

Tape & Reel

†

See Application Note AND8308/D for further description of survivability specs.

© Semiconductor Components Industries, LLC, 2016

October, 2017 − Rev. 3

1 Publication Order Number:

ESD7421/D

ESD7421, SZESD7421

ELECTRICAL CHARACTERISTICS

(TA = 25°C unless otherwise noted)

Symbol

I

PP

V

C

V

RWM

I

R

V

BR1

V

BR2

I

T

Maximum Reverse Peak Pulse Current

Clamping Voltage @ I

Working Peak Reverse Voltage

Maximum Reverse Leakage Current @ V

Breakdown Voltage @ I

Breakdown Voltage @ I

Test Current

Parameter

PP

T

T

RWM

VCV

V

RWM

BR2

Bi−Directional

I

I

PP

I

T

I

R

I

V

RWM

V

R

I

T

I

PP

BR1

V

V

C

*See Application Note AND8308/D for detailed explanations of

datasheet parameters.

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise specified)

A

Parameter Symbol Conditions Min Typ Max Unit

Reverse Working
Voltage

Breakdown Voltage V

Breakdown Voltage V

Reverse Leakage
Current

Clamping Voltage
(Note 2)

Clamping Voltage TLP
(Note 3)

Junction Capacitance C

V

RWM

BR1

BR2

I

R

V

C

V

C

J

Pin 1 to GND
Pin 2 to GND

I

= 1 mA, Pin 1 to GND 16.5 V

T

I

= 1 mA, Pin 2 to GND 10.5 14 V

T

V

= 5 V, I/O Pin to GND

RWM

V

= 16 V, Pin 1 to GND

RWM

5
5

16
10

100 500

1.0

nA
mA

IEC61000−4−2, ±8 kV Contact See Figures 2 and 3

IPP = 8 A
IPP = 16 A
IPP = −8 A

IPP = −16 A

35

38.1

−21

−29.5

VR = 0 V, f = 1 MHz between I/O Pins and GND 0.3 0.6 pF

V

V

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.

2. For test procedure see Figure 5 and application note AND8307/D.

3. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z

= 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.

0

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2

ESD7421, SZESD7421

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

CAPACITANCE (pF)

0.2

0.1
0

−5 −4 −20123 5

VBias (V)

Figure 1. Typical CV Characteristic Curve

Pin1 to GND (GND connected to Pin2)

4−1−3

120

100

80

60

40

VOLTAGE (V)

20

−20

0

−25

0

25 50 75 150100 125

TIME (ns)

Figure 2. IEC61000−4−2 +8 kV Contact ESD

Clamping Voltage

Pin1 to GND (GND connected to Pin2)

20

0

−20

−40

−60

VOLTAGE (V)

−80

−100

−120

−25

0 25 50 150100 125

75

TIME (ns)

Figure 3. IEC61000−4−2 −8 kV Contact ESD

Clamping Voltage

Pin1 to GND (GND connected to Pin2)

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3

ESD7421, SZESD7421

IEC 61000−4−2 Spec.

Test Volt-

Level

age (kV)

1 2 7.5 4 2

2 4 15 8 4

3 6 22.5 12 6

4 8 30 16 8

ESD Gun

First Peak

Current

(A)

Current at

30 ns (A)

Device

Under

Test

50 W

Cable

IEC61000−4−2 Waveform

I

peak

Current at

60 ns (A)

100%

90%

I @ 30 ns

I @ 60 ns

10%

Figure 4. IEC61000−4−2 Spec

Oscilloscope

50 W

tP = 0.7 ns to 1 ns

Figure 5. Diagram of ESD Clamping Voltage Test Setup

The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.

ESD Voltage Clamping

For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger

systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.

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4

ESD7421, SZESD7421

20

18

16

14

12

10

8

CURRENT (A)

6

4

2

0

045353051015 2520

VOLTAGE (V)

40

Figure 6. Positive TLP IV Curve

NOTE: TLP parameter: Z

= 50 W, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns.

0

Transmission Line Pulse (TLP) Measurement

Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 8. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 9 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels.

−20

−18

−16

−14

−12

−10

−8

CURRENT (A)

−6

−4

−2

0

0 −35−5 −10 −15 −20 −30−25

VOLTAGE (V)

Figure 7. Negative TLP IV Curve

L

50 W Coax

Cable

Figure 8. Simplified Schematic of a Typical TLP

10 MW

V

C

System

Attenuator

S

÷

I

M

Oscilloscope

50 W Coax

Cable

V

M

DUT

Figure 9. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms

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5

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

XDFN2 1.0x0.6, 0.65P (SOD−882)

SCALE 8:1

CASE 711AM

ISSUE O

DATE 29 AUG 2012

0.10 C

PIN 1
INDICATOR

D

TOP VIEW

0.10 C

NOTE 3

0.10 C

A1

SIDE VIEW

e

e/2

1

BOTTOM VIEW

RECOMMENDED

SOLDER FOOTPRINT*

1.20

2X

0.47

A B

E

b

2X

L

0.05

A

SEATING

C

PLANE

M

0.05 BC

M

0.05 BC

2X

0.60

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. EXPOSED COPPER ALLOWED AS SHOWN.

MILLIMETERS

DIM MIN MAX

C

A 0.34 0.44

A1 −−− 0.05

b 0.43 0.53
D 1.00 BSC
E 0.60 BSC
e 0.65 BSC
L 0.20 0.30

GENERIC

MARKING DIAGRAM*

XX M

G

A

A

XX = Specific Device Code
M = Date Code
G = Pb−Free Package

*This information is generic. Please refer

to device data sheet for actual part
marking. Pb−Free indicator, “G”, may
or not be present.

PIN 1

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

DOCUMENT NUMBER:

DESCRIPTION:

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.

98AON82886E

XDFN2 1.0X0.6, 0.65P (SOD−882)

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

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