ON Semiconductor ESD7008, SZESD7008 Users guide

ESD7008, SZESD7008

ESD Protection Diode

Low Capacitance ESD Protection Diode for High Speed Data Line

The ESD7008 ESD protection diode is designed specifically to protect four high speed differential pairs. Ultra−low capacitance and low ESD clamping voltage make this device an ideal solution for protecting voltage sensitive high speed data lines. The flow−through style package allows for easy PCB layout and matched trace lengths necessary to maintain consistent impedance for the high speed lines.

Features

• Integrated 4 Pairs (8 Lines) High Speed Data

• Single Connect, Flow through Routing

• Low Capacitance (0.12 pF Typical, I/O to GND)

• Protection for the Following IEC Standards:

IEC 61000−4−2 Level 4

• UL Flammability Rating of 94 V−0

• SZ Prefix for Automotive and Other Applications Requiring Unique

Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable

• This is a Pb−Free Device

Typical Applications

• V−by−One HS

• Thunderbolt (Light Peak)

• USB 3.0

• HDMI

• Display Port

• LVDS

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MARKING

UDFN18

CASE 517BV

7008 = Specific Device Code M = Date Code G = Pb−Free Package

(Note: Microdot may be in either location)

ORDERING INFORMATION

Device Package Shipping

ESD7008MUTAG UDFN18

(Pb−Free)

SZESD7008MUTAG UDFN18

(Pb−Free)

†For information on tape and reel specifications,

including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.

DIAGRAM

7008MG

3000 / Tape &

Reel

3000 / Tape &

Reel

MAXIMUM RATINGS (T

Rating

Operating Junction Temperature Range T

Storage Temperature Range T

Lead Solder Temperature − Maximum (10 Seconds)

IEC 61000−4−2 Contact (ESD) IEC 61000−4−2 Air (ESD)

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

= 25°C unless otherwise noted)

Symbol Value Unit

stg

ESD ESD

−55 to +125 °C

−55 to +150 °C

260 °C

±15 ±15

kV kV

See Application Note AND8308/D for further description of survivability specs.

October, 2017 − Rev. 7

1 Publication Order Number:

ESD7008/D

ESD7008, SZESD7008

I/O

Pin 1

GND Pin 3

I/O

Pin 2

I/O

Pin 4

GND Pin 6

GND Pin 9

I/O

Pin 5

I/O

Pin 7

GND

Pin 13

Note: Only Minimum of 1 GND connection required

I/O

Pin 8

GND

Pin 15

I/O

Pin 10

Pin 17

I/O

Pin 11

GND

Figure 1. Pin Schematic

I/O

GND

I/O

GND

I/O

GND

I/O

N/C

GND

N/C

GND

N/C

GND

N/C

Figure 2. Pin Configuration

Note: Only minimum of one pin needs to be connected to ground for functional-

ity of all pins. All pins labeled “N/C” should have no electrical connection.

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ESD7008, SZESD7008

RWM

= 25°C unless otherwise specified)

I/O Pin to GND (Note 1) 5.0 V

IT = 1 mA, I/O Pin to GND 5.5 6.7 V

= 5 V, I/O Pin to GND 1.0

RWM

IPP = 1 A, I/O Pin to GND (8 x 20 ms pulse)

IEC61000−4−2, ±8 kV Contact See Figures 3 and 4 V

IPP = ±8 A I

= ±16 A

13.2

18.2

VR = 0 V, f = 1 MHz between I/O Pins and GND 0.12 0.15 pF

VR = 0 V, f = 1 MHz between I/O Pins and GND 0.02 pF

ELECTRICAL CHARACTERISTICS (T

Parameter

Reverse Working Voltage V

Breakdown Voltage V

Reverse Leakage Current I

Clamping Voltage (Note 1) V

Clamping Voltage (Note 2) V

Clamping Voltage TLP (Note 3) See Figures 8 through 11

Junction Capacitance C

Junction Capacitance Difference

Symbol Conditions Min Typ Max Unit

1. Surge current waveform per Figure 7.

2. For test procedure see Figures 5 and 6 and application note AND8307/D.

3. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z

= 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.

−10

VOLTAGE (V)

−20

−30

VOLTAGE (V)

−40

−10

−20 0 20 40 60 80 100 120 140

−50

−20 0 20 40 60 80 100 120 140

TIME (ns) TIME (ns)

Figure 3. IEC61000−4−2 +8 KV Contact

Clamping Voltage

Figure 4. IEC61000−4−2 −8 KV Contact

Clamping Voltage

10 V

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ESD7008, SZESD7008

IEC 61000−4−2 Spec.

Test Volt-

Level

age (kV)

1 2 7.5 4 2

2 4 15 8 4

3 6 22.5 12 6

4 8 30 16 8

ESD Gun

First Peak

Current

(A)

Current at

30 ns (A)

Device

Under

Test

50 W

Cable

IEC61000−4−2 Waveform

peak

Current at

60 ns (A)

100%

90%

I @ 30 ns

I @ 60 ns

10%

Figure 5. IEC61000−4−2 Spec

Oscilloscope

50 W

tP = 0.7 ns to 1 ns

Figure 6. Diagram of ESD Clamping Voltage Test Setup

The following is taken from Application Note AND8308/D − Interpretation of Datasheet Parameters for ESD Devices.

ESD Voltage Clamping

For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger

100

% OF PEAK PULSE CURRENT

020406080

PEAK VALUE I

Figure 7. 8 x 20 ms Pulse Waveform

systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D.

@ 8 ms

RSM

PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 ms

HALF VALUE I

t, TIME (ms)

/2 @ 20 ms

RSM

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