ON Semiconductor ESD7008, SZESD7008 Users guide

ESD7008, SZESD7008

ESD Protection Diode

Low Capacitance ESD Protection Diode for High Speed Data Line

The ESD7008 ESD protection diode is designed specifically to protect four high speed differential pairs. Ultra−low capacitance and low ESD clamping voltage make this device an ideal solution for protecting voltage sensitive high speed data lines. The flow−through style package allows for easy PCB layout and matched trace lengths necessary to maintain consistent impedance for the high speed lines.

Features

•Integrated 4 Pairs (8 Lines) High Speed Data

•Single Connect, Flow through Routing

•Low Capacitance (0.12 pF Typical, I/O to GND)

•Protection for the Following IEC Standards: IEC 61000−4−2 Level 4

•UL Flammability Rating of 94 V−0

•SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable

•This is a Pb−Free Device

Typical Applications

•V−by−One HS

•Thunderbolt (Light Peak)

•USB 3.0

•HDMI

•Display Port

•LVDS

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)

Rating	Symbol	Value	Unit
Operating Junction Temperature Range	TJ	−55 to +125	°C
Storage Temperature Range	Tstg	−55 to +150	°C
Lead Solder Temperature −	TL	260	°C
Maximum (10 Seconds)
IEC 61000−4−2 Contact (ESD)	ESD	±15	kV
IEC 61000−4−2 Air (ESD)	ESD	±15	kV

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

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MARKING 18 DIAGRAM

	1	7008MG
	UDFN18
		G

CASE 517BV

7008 = Specific Device Code

M = Date Code

G= Pb−Free Package

(Note: Microdot may be in either location)

ORDERING INFORMATION

Device	Package		Shipping
ESD7008MUTAG	UDFN18		3000 / Tape &
	(Pb−Free)		Reel
SZESD7008MUTAG	UDFN18		3000 / Tape &
	(Pb−Free)		Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

See Application Note AND8308/D for further description of survivability specs.

♥ Semiconductor Components Industries, LLC, 2016	1	Publication Order Number:
October, 2017 − Rev. 7		ESD7008/D

ESD7008, SZESD7008

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

Pin 1

Pin 2

Pin 4

Pin 5

Pin 7

Pin 8

Pin 10

Pin 11

GND	GND	GND	GND	GND	GND
Pin 3	Pin 6	Pin 9	Pin 13	Pin 15	Pin 17

Note: Only Minimum of 1 GND connection required

=

Figure 1. Pin Schematic

I/O

1

18 N/C

I/O 2

GND				N/C			GND
		3				17
I/O
		4
						16	N/C
I/O		5
GND
		6		N/C		15	GND
I/O
		7
						14	N/C
I/O		8
				N/C
GND		9				13	GND
I/O		10
						12	N/C
I/O
		11

Figure 2. Pin Configuration

Note: Only minimum of one pin needs to be connected to ground for functionality of all pins. All pins labeled “N/C” should have no electrical connection.

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ESD7008, SZESD7008

ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified)

Parameter	Symbol	Conditions	Min	Typ	Max	Unit
Reverse Working Voltage	VRWM	I/O Pin to GND (Note 1)			5.0	V
Breakdown Voltage	VBR	IT = 1 mA, I/O Pin to GND	5.5	6.7		V
Reverse Leakage Current	IR	VRWM = 5 V, I/O Pin to GND			1.0	mA
Clamping Voltage (Note 1)	VC	IPP = 1 A, I/O Pin to GND (8 x 20 ms pulse)			10	V
Clamping Voltage (Note 2)	VC	IEC61000−4−2, ±8 kV Contact	See Figures 3 and 4			V
Clamping Voltage	VC	IPP = ±8 A		13.2
TLP (Note 3)		IPP = ±16 A		18.2
See Figures 8 through 11
Junction Capacitance	CJ	VR = 0 V, f = 1 MHz between I/O Pins and GND		0.12	0.15	pF
Junction Capacitance	DCJ	VR = 0 V, f = 1 MHz between I/O Pins and GND		0.02		pF
Difference

1.Surge current waveform per Figure 7.

2.For test procedure see Figures 5 and 6 and application note AND8307/D.

3.ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.

	90
	80
	70
<![if ! IE]> <![endif]>(V)	60
	50
<![if ! IE]> <![endif]>VOLTAGE
	40
	30
	20
	10
	0
	−10
	−20	0	20	40	60	80	100	120	140

TIME (ns)

Figure 3. IEC61000−4−2 +8 KV Contact

Clamping Voltage

	0
	−10
<![if ! IE]> <![endif]>(V)
<![if ! IE]> <![endif]>VOLTAGE	−20
	−30
	−40
	−50
	−20	0	20	40	60	80	100	120	140

TIME (ns)

Figure 4. IEC61000−4−2 −8 KV Contact

Clamping Voltage

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				ESD7008, SZESD7008
IEC 61000−4−2 Spec.					IEC61000−4−2 Waveform
					Ipeak
		First Peak
					100%
	Test Volt-	Current	Current at	Current at
Level	age (kV)	(A)	30 ns (A)	60 ns (A)	90%
1	2	7.5	4	2
2	4	15	8	4	I @ 30 ns
3	6	22.5	12	6
4	8	30	16	8	I @ 60 ns
					10%
					tP = 0.7 ns to 1 ns
				Figure 5. IEC61000−4−2 Spec
			Device
	ESD Gun		Under	Oscilloscope
			Test
			50 W
			Cable		50 W

Figure 6. Diagram of ESD Clamping Voltage Test Setup

The following is taken from Application Note AND8308/D − Interpretation of Datasheet Parameters for ESD Devices.

ESD Voltage Clamping

For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger

systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D.

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<![endif]>% OF PEAK PULSE CURRENT

100	tr	PEAK VALUE IRSM @ 8 ms
90
80			PULSE WIDTH (tP) IS DEFINED
70			AS THAT POINT WHERE THE
			PEAK CURRENT DECAY = 8 ms
60			HALF VALUE IRSM/2 @ 20 ms
50
40
30		tP
20
10
0	0	20	40	60	80
			t, TIME (ms)

Figure 7. 8 x 20 ms Pulse Waveform

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