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CS5159
CPU 5−Bit Synchronous
Buck Controller
The CS5159 is a 5−bit synchronous dual N−Channel buck
controller. It is designed to provide unprecedented transient response
for today’s demanding high−density, high−speed logic. The regulator
operates using a proprietary control method, which allows a 100 ns
response time to load transients. The CS5159 is designed to operate
over a 4.25−16 V range (VCC) using 12 V to power the IC and 5.0 V or
12V as the main supply for conversion.
The CS5159 is specifically designed to power Pentium® II
processors and other high performance core logic. It includes the
following features: on board, 5−bit DAC, short circuit protection,
1.0% output tolerance, VCC monitor, and programmable Soft Start
capability. The CS5159 is available in 16 pin surface mount.
Features
• Dual N−Channel Design
• Excess of 1.0 MHz Operation
• 100 ns Transient Response
• 5−Bit DAC
• Backward Compatible with Adjustable CS5157
• 30 ns Gate Rise/Fall Times
• 1.0% DAC Accuracy
• 5.0 V & 12 V Operation
• Remote Sense
• Programmable Soft Start
• Lossless Short Circuit Protection
• V
Monitor
CC
• 25 ns FET Nonoverlap Time
2
• V
™ Control Topology
• Current Sharing
• Overvoltage Protection
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MARKING
DIAGRAM
16
1
SOIC−16
D SUFFIX
CASE 751B
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
PIN CONNECTIONS
1
V
ID0
ID1
ID2
V
ID3
SS
ID4
C
OFF
V
FFB
ORDERING INFORMATION
16
CS5159
AWLYWW
1
16
V
COMPV
LGNDV
V
V
PGNDV
V
V
FB
CC1
GATE(L)
GATE(H)
CC2
© Semiconductor Components Industries, LLC, 2006
July, 2006 − Rev. 5
Device Package Shipping
CS5159GD16 SO−16
CS5159GDR16
1 Publication Order Number:
SO−16
48 Units/Rail
2500 Tape & Reel
CS5159/D
CS5159
12 V
5.0 V
0.1 μF
CC1
V
CC2
CS5159
V
GATE(H)
V
GATE(L)
PGND
IRL3103
2.0 μH
IRL3103
V
V
V
V
V
330 pF
ID0
ID1
ID2
ID3
ID4
V
V
ID0
V
ID1
V
ID2
V
ID3
V
ID4
C
OFF
SS
0.1 μF
0.33 μF
COMP
LGND
V
FB
3.3 k
V
FFB
1200 μF/10 V × 5
100 pF
Figure 1. Application Diagram, Switching Power Supply for Core Logic − Pentium) II Processor
1200 μF/10 V × 3
AIEI
1.3 V to 3.5 V @ 13 A
AIEI
ABSOLUTE MAXIMUM RATINGS*
Rating Value Unit
Operating Junction Temperature, T
J
0 to 150 °C
Lead Temperature Soldering: Reflow: (SMD styles only) (Note 1) 230 peak °C
Storage Temperature Range, T
S
−65 to +150 °C
ESD Susceptibility (Human Body Model) 2.0 kV
1. 60 second maximum above 183°C.
*The maximum package power dissipation must be observed.
ABSOLUTE MAXIMUM RATINGS
Pin Name Max Operating Voltage Max Current
V
CC1
V
CC2
SS 6.0 V/−0.3 V −100 μA
COMP 6.0 V/−0.3 V 200 μA
V
FB
C
OFF
V
FFB
V
− V
ID0
ID4
V
GATE(H)
V
GATE(L)
LGND 0 V 25 mA
PGND 0 V 100 mA DC/1.5 A peak
16 V/−0.3 V 25 mA DC/1.5 A peak
18 V/−0.3 V 20 mA DC/1.5 A peak
6.0 V/−0.3 V −0.2 μA
6.0 V/−0.3 V −0.2 μA
6.0 V/−0.3 V −0.2 μA
6.0 V/−0.3 V −50 μA
18 V/−0.3 V 100 mA DC/1.5 A peak
16 V/−0.3 V 100 mA DC/1.5 A peak
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CS5159
ELECTRICAL CHARACTERISTICS (0°C < T
Code: V
ID4
= V
ID2
= V
ID1
= V
ID0
= 1; V
ID3
= 0
;
CV
GATE(L)
< +70°C; 0°C < TJ < +85°C; 8.0 V < V
A
GATE(H)
= 1.0 nF; C
OFF
and CV
< 14 V; 5.0 V < V
CC1
= 330 pF; CSS = 0.1 μF, unless otherwise specified.)
< 18 V; DAC
CC2
Characteristic Test Conditions Min Typ Max Unit
Error Amplifier
VFB Bias Current VFB = 0 V − 0.3 1.0 μA
Open Loop Gain 1.25 V < V
< 4.0 V; Note 2 50 60 − dB
COMP
Unity Gain Bandwidth Note 2 500 3000 − kHz
COMP SINK Current V
COMP SOURCE Current V
COMP CLAMP Current V
= 1.5 V; VFB = 3.0 V; VSS > 2.0 V 0.4 2.5 8.0 mA
COMP
= 1.2 V; VFB = 2.7 V; VSS = 5.0 V 30 50 80 μA
COMP
= 0 V; VFB = 2.7 V 0.4 1.0 1.6 mA
COMP
COMP High Voltage VFB = 2.7 V; VSS = 5.0 V 4.0 4.3 5.0 V
COMP Low Voltage VFB = 3.0 V − 160 600 mV
PSRR 8.0 V < V
V
Monitor
CC1
< 14 V @ 1.0 kHz; Note 2 60 85 − dB
CC1
Start Threshold Output switching 3.75 3.90 4.05 V
Stop Threshold Output not switching 3.70 3.85 4.00 V
Hysteresis Start−Stop − 50 − mV
V
and V
GATE(H)
GATE(L)
Out SOURCE Sat at 100 mA Measure V
Out SINK Sat at 100 mA Measure V
Out Rise Time 1.0 V < V
V
= V
CC1
Out Fall Time 9.0 V > V
V
= V
CC1
Delay V
Delay V
V
GATE(H)
V
GATE(H)
GATE(H)
GATE(L)
, V
GATE(L)
, V
GATE(L)
to V
GATE(L)
to V
GATE(H)
Resistance Resistor to LGND, Note 2 20 50 100 kΩ
Schottky LGND to V
V
GATE(H)
V
V
GATE(L)
V
GATE(L)
falling to 2.0 V; V
GATE(H)
LGND to V
− V
CC1
GATE(L)
− V
GATE(H)
GATE(H)
CC2
GATE(H)
CC2
PGND
< 9.0 V; 1.0 V < V
= 12 V
> 1.0 V; 9.0 V > V
= 12 V
falling to 2.0 V; V
rising to 2.0 V
rising to 2.0 V
@ 10 mA
GATE(H)
GATE(L)
@ 10 mA
; V
CC1
; V
CC1
CC2
GATE(L)
= V
= V
− V
GATE(L)
GATE(L)
CC2
CC2
GATE(H)
− V
< 9.0 V;
> 1.0 V;
= 8.0 V;
= 8.0 V;
PGND
− 1.2 2.0 V
− 1.0 1.5 V
− 30 50 ns
− 30 50 ns
− 25 50 ns
− 25 50 ns
− 600 800 mV
Soft Start (SS)
Charge Time − 1.6 3.3 5.0 ms
Pulse Period − 25 100 200 ms
Duty Cycle (Charge Time /Pulse Period) × 100 1.0 3.3 6.0 %
COMP Clamp Voltage VFB = 0 V; VSS = 0 0.50 0.95 1.10 V
V
SS Fault Disable V
FFB
GATE(H)
= Low; V
= Low 0.9 1.0 1.1 V
GATE(L)
High Threshold − − 2.5 3.0 V
PWM Comparator
Transient Response V
V
Bias Current V
FFB
= 0 to 5.0 V to V
FFB
V
= V
CC2
= 12 V
CC1
= 0 V − 0.3 − μA
FFB
= 9.0 V to 1.0 V;
GATE(H)
− 100 125 ns
2. Guaranteed by design, not 100% tested in production.
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CS5159
ELECTRICAL CHARACTERISTICS (continued) (0 °C < T
Code: V
ID4
= V
ID2
= V
ID1
= V
ID0
= 1; V
ID3
= 0
;
CV
GATE(L)
and CV
< +70°C; 0°C < TJ < +85°C; 8.0 V < V
A
GATE(H)
= 1.0 nF; C
= 330 pF; CSS = 0.1 μF, unless otherwise specified.)
OFF
< 14 V; 5.0 V < V
CC1
< 18 V; DAC
CC2
Characteristic UnitMaxTypMinTest Conditions
DAC
Input Threshold
Input Pull Up Resistance V
ID0,
ID0,
, V
ID3
ID3
, V
, V
ID4
ID4
ID1
ID2
V
, V
ID1
ID2
1.00 1.25 2.40 V
25 50 100 kΩ
V
V
, V
, V
Pull Up Voltage − 4.85 5.00 5.15 V
Accuracy (all codes except 11111 ,
Measure VFB = V
, 25°C ≤TJ ≤85°C − − 1.0 %
COMP
10110, 10101, 10100, 10011,
10010, 10001, 10000)
V
ID4VID3VID2VID1VID0
0 1 1 1 1 − 1.2870 1.3000 1.3130 V
0 1 1 1 0 − 1.3365 1.3500 1.3635 V
0 1 1 0 1 − 1.3860 1.4000 1.4140 V
0 1 1 0 0 − 1.4355 1.4500 1.4645 V
0 1 0 1 1 − 1.4850 1.5000 1.5150 V
0 1 0 1 0 − 1.5345 1.5500 1.5655 V
0 1 0 0 1 − 1.5840 1.6000 1.6160 V
0 1 0 0 0 − 1.6335 1.6500 1.6665 V
0 0 1 1 1 − 1.6830 1.7000 1.7170 V
0 0 1 1 0 − 1.7325 1.7500 1.7675 V
0 0 1 0 1 − 1.7820 1.8000 1.8180 V
0 0 1 0 0 − 1.8315 1.8500 1.8685 V
0 0 0 1 1 − 1.8810 1.9000 1.9190 V
0 0 0 1 0 − 1.9305 1.9500 1.9695 V
0 0 0 0 1 − 1.9800 2.0000 2.0200 V
0 0 0 0 0 − 2.0295 2.0500 2.0705 V
1 1 1 1 1 − 1.2191 1.2440 1.2689 V
1 1 1 1 0 − 2.0790 2.1000 2.1210 V
1 1 1 0 1 − 2.1780 2.2000 2.2220 V
1 1 1 0 0 − 2.2770 2.3000 2.3230 V
1 1 0 1 1 − 2.3760 2.4000 2.4240 V
1 1 0 1 0 − 2.4750 2.5000 2.5250 V
1 1 0 0 1 − 2.5740 2.6000 2.6260 V
1 1 0 0 0 − 2.6730 2.7000 2.7270 V
1 0 1 1 1 − 2.7720 2.8000 2.8280 V
1 0 1 1 0 − 2.8420 2.9000 2.9580 V
1 0 1 0 1 − 2.9400 3.0000 3.0600 V
1 0 1 0 0 − 3.0380 3.1000 3.1620 V
1 0 0 1 1 − 3.1360 3.2000 3.2640 V
1 0 0 1 0 − 3.2340 3.3000 3.3660 V
1 0 0 0 1 − 3.3320 3.4000 3.4680 V
1 0 0 0 0 − 3.4300 3.5000 3.5700 V
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4
CS5159
ELECTRICAL CHARACTERISTICS (continued) (0 °C < T
Code: V
ID4
= V
ID2
= V
ID1
= V
ID0
= 1; V
ID3
= 0
;
CV
GATE(L)
and CV
Characteristic UnitMaxTypMinTest Conditions
Supply Current
I
CC1
I
CC2
Operating I
Operating I
C
OFF
CC1
CC2
Normal Charge Time V
Extension Charge Time VSS = V
Discharge Current C
No Switching − 8.5 13.5 mA
No Switching − 1.6 3.0 mA
VFB = COMP = V
VFB = COMP = V
= 1.5 V; VSS = 5.0 V 1.0 1.6 2.2 μs
FFB
FFB
to 5.0 V; VFB > 1.0 V 5.0 − − mA
OFF
FFB
FFB
= 0 5.0 8.0 11.0 μs
Time Out Timer
Time Out Time VFB = V
Record V
Fault Mode Duty Cycle V
= 0V 35 50 70 %
FFB
COMP
; V
FFB
Pulse High Duration
GATE(H)
PACKAGE PIN DESCRIPTION
PACKAGE PIN #
SO−16
1, 2, 3, 4, 6 V
5 SS Soft Start Pin. A capacitor from this pin to LGND in conjunction with internal 60 μA cur-
7 C
8 V
9 V
10 V
11 PGND High current ground for the IC. The MOSFET driver is referenced to this pin. Input capac-
12 V
13 V
14 LGND Signal ground for the IC. All control circuits are referenced to this pin.
15 COMP Error amplifier compensation pin. A capacitor to ground should be provided externally to
16 V
PIN SYMBOL FUNCTION
ID0−VID4
Voltage ID DAC input pins. These pins are internally pulled up to 5.0 V providing logic
ones if left open. V
range is 2.10 V to 3.50 V with 100 mV increments. When V
DAC range is 1.30 V to 2.05 V with 50 mV increments. V
DAC output voltage. Leaving all 5 DAC input pins open results in a DAC output voltage
of 1.2440 V, allowing for adjustable output voltage, using a traditional resistor divider.
rent source provides Soft Start function for the controller. This pin disables fault detect
function during Soft Start. When a fault is detected, the Soft Start capacitor is slowly discharged by internal 2.0 μA current source setting the time out before trying to restart the
IC. Charge/discharge current ratio of 30 sets the duty cycle for the IC when the regulator
output is shorted.
OFF
FFB
CC2
GATE(H)
A capacitor from this pin to ground sets the time duration for the on board one shot,
which is used for the constant off time architecture.
Fast feedback connection to the PWM comparator. This pin is connected to the regulator
output. The inner feedback loop terminates on time.
Boosted power for the high side gate driver.
High FET driver pin capable of 1.5 A peak switching current. Internal circuit prevents
V
GATE(H)
and V
itor ground and the source of lower FET should be tied to this pin.
GATE(L)
CC1
Low FET driver pin capable of 1.5 A peak switching current.
Input power for the IC and low side gate driver.
compensate the amplifier.
FB
Error amplifier DC feedback input. This is the master voltage feedback which sets the
output voltage. This pin can be connected directly to the output or a remote sense trace.
< +70°C; 0°C < TJ < +85°C; 8.0 V < V
A
GATE(H)
= 1.0 nF; C
= 330 pF; CSS = 0.1 μF, unless otherwise specified.)
OFF
= 2.0 V;
selects the DAC range. When V
ID4
from being in high state simultaneously.
GATE(L)
< 14 V; 5.0 V < V
CC1
< 18 V; DAC
CC2
− 8.0 13 mA
− 2.0 5.0 mA
10 30 65 μs
is High (logic one), the DAC
ID4
is Low (logic zero), the
ID4
ID0
− V
select the desired
ID4
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