ON Semiconductor CS5157H Technical data

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查询CS5157HGD16G供应商

CS5157H

CPU 5−Bit Synchronous
Buck Controller

The CS5157H is a 5−bit synchronous dual N−Channel buck
controller. It is designed to provide unprecedented transient response
for today’s demanding high−density, high−speed logic. The regulator
operates using a proprietary control method, which allows a 100 ns
response time to load transients. The CS5157H is designed to operate
over a 4.25−20 V range (VCC) using 12 V to power the IC and 5.0 V or
12 V as the main supply for conversion.

The CS5157H is specifically designed to power Pentium® II
processors and other high performance core logic. It includes the
following features: on board, 5−bit DAC, short circuit protection,

1.0% output tolerance, VCC monitor, and programmable Soft−Start
capability. The CS5157H is available in 16 pin surface mount.

Features

• Dual N−Channel Design

• Excess of 1.0 MHz Operation

• 100 ns Transient Response

• 5−Bit DAC

• 30 ns Gate Rise/Fall Times

• 1.0% DAC Accuracy

• 5.0 V and 12 V Operation

• Remote Sense

• Programmable Soft−Start

• Lossless Short Circuit Protection

• V

Monitor

CC

• 25 ns FET Nonoverlap Time

2

• V

t Control Topology

• Current Sharing

• Overvoltage Protection

• Pb−Free Packages are Available*

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SOIC−16

16

1

D SUFFIX

CASE 751B

MARKING DIAGRAM

16

CS5157HG

AWLYWW

1

CS5157H = Device Code
A = Assembly Location
WL = Wafer Lot
Y = Year
WW = Work Week
G = Pb−Free Package

PIN CONNECTIONS

1

V

ID0
ID1
ID2

V

ID3

SS

ID4

C

OFF

V

FFB

16

V
COMPV
LGNDV
V
V
PGNDV
V
V

FB

CC1
GATE(L)

GATE(H)
CC2

ORDERING INFORMATION

Device Package Shipping

CS5157HGD16 SO−16 48 Units/Rail
CS5157HGD16G SO−16

CS5157HGDR16
CS5157HGDR16G SO−16

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.

© Semiconductor Components Industries, LLC, 2005

October, 2005 − Rev. 7

1 Publication Order Number:

For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.

(Pb−Free)

SO−16 2500/Tape & Ree

(Pb−Free)

48 Units/Rail

2500/Tape & Ree

†

CS5157H/D

CS5157H

12 V

5.0 V

0.1 mF

CC1

V

CC2

CS5157H

V

GATE(H)

V

GATE(L)

PGND

IRL3103

2.0 mH

IRL3103

V
V
V
V

V

330 pF

ID0

ID1

ID2

ID3
ID4

V

V

ID0

V

ID1

V

ID2

V

ID3

V

ID4

C

OFF

SS

0.1 mF

0.33 mF

COMP

LGND

V

FB

3.3 k

V

FFB

1200 mF/10 V × 5

100 pF

Figure 1. Application Diagram, Switching Power Supply for Core Logic − Pentium) II Processor

1200 mF/10 V × 3

AIEI

1.3 V to 3.5 V @ 13 A

AIEI

MAXIMUM RATINGS

Rating Value Unit

Operating Junction Temperature, T

J

0 to 150 °C
Lead Temperature Soldering: Reflow: (SMD styles only) (Note 1) 230 peak °C
Storage Temperature Range, T

S

−65 to +150 °C

ESD Susceptibility (Human Body Model) 2.0 kV

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.

1. 60 second maximum above 183°C.

MAXIMUM RATINGS

Pin Name Max Operating Voltage Max Current

V

CC1

V

CC2

SS 6.0 V/−0.3 V

COMP 6.0 V/−0.3 V

V

FB

C

OFF

V

FFB

V

− V

ID0

ID4

V

GATE(H)

V

GATE(L)

LGND 0 V 25 mA

PGND 0 V 100 mA DC/1.5 A peak

16 V/−0.3 V 25 mA DC/1.5 A peak
20 V/−0.3 V 20 mA DC/1.5 A peak

−100 mA
200 mA

6.0 V/−0.3 V

6.0 V/−0.3 V

6.0 V/−0.3 V

6.0 V/−0.3 V

−0.2 mA

−0.2 mA

−0.2 mA

−50 mA

20 V/−0.3 V 100 mA DC/1.5 A peak
16 V/−0.3 V 100 mA DC/1.5 A peak

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2

CS5157H

ELECTRICAL CHARACTERISTICS (0°C < T

V

= V

ID4

ID2

= V

ID1

= V

ID0

= 1; V

ID3

= 0

;

CV

GATE(L)

< +70°C; 0°C < TJ < +125 °C; 8. 0 V < V

A

and CV

GATE(H)

= 1.0 nF; C

= 330 pF; CSS = 0.1 mF, unless otherwise spec if ied.)

OFF

< 14 V; 5.0 V < V

CC1

< 20 V;DAC Code:

CC2

Characteristic Test Conditions Min Typ Max Unit

Error Amplifier

VFB Bias Current VFB = 0 V − 0.3 1.0
Open Loop Gain 1.25 V < V

< 4.0 V; (Note 2) 50 60 − dB

COMP

Unity Gain Bandwidth (Note 2) 500 3000 − kHz
COMP SINK Current V
COMP SOURCE Current V
COMP CLAMP Current V

= 1.5 V; VFB = 3.0 V; VSS > 2.0 V 0.4 2.5 8.0 mA

COMP

= 1.2 V; VFB = 2.7 V; VSS = 5.0 V 30 50 80

COMP

= 0 V; VFB = 2.7 V 0.4 1.0 1.6 mA

COMP

COMP High Voltage VFB = 2.7 V; VSS = 5.0 V 4.0 4.3 5.0 V
COMP Low Voltage VFB = 3.0 V − 160 600 mV
PSRR 8.0 V < V

V

Monitor

CC1

< 14 V @ 1.0 kHz; (Note 2) 60 85 − dB

CC1

Start Threshold Output switching 3.75 3.90 4.05 V
Stop Threshold Output not switching 3.70 3.85 4.00 V
Hysteresis Start−Stop − 50 − mV

V

Out SOURCE Sat at 100 mA Measure V
Out SINK Sat at 100 mA Measure V
Out Rise Time 1.0 V < V

Out Fall Time 9.0 V > V

Delay V

Delay V

V
V

GATE(H)

GATE(H)

GATE(H)

and V

GATE(H)

GATE(L)

, V

GATE(L)

, V

GATE(L)

GATE(L)

− V

CC1

GATE(H)

< 9.0 V; 1.0 V < V

V

V

to V

GATE(L)

to V

GATE(H)

Resistance Resistor to LGND (Note 2) 20 50 100
Schottky LGND to V

V
V

V
V

LGND to V

GATE(H)

= V

CC1

CC2

GATE(H)

= V

CC1

CC2

falling to 2.0 V; V

GATE(H)

rising to 2.0 V

GATE(L)

falling to 2.0 V; V

GATE(L)

rising to 2.0 V

GATE(H)

= 12 V

> 1.0 V; 9.0 V > V

= 12 V

GATE(H)
GATE(L)

; V

GATE(L)

− V

PGND

@ 10 mA

@ 10 mA

; V

CC1

CC1

CC2

GATE(L)

= V

= V

− V

GATE(L)

GATE(L)

CC2

GATE(H)

− V

CC2

PGND

< 9.0 V;

> 1.0 V;

= 8.0 V;

= 8.0 V;

− 1.2 2.0 V

− 1.0 1.5 V

− 30 50 ns

− 30 50 ns

− 25 50 ns

− 25 50 ns

− 600 800 mV

Soft−Start (SS)

Charge Time − 1.6 3.3 5.0 ms
Pulse Period − 25 100 200 ms
Duty Cycle (Charge Time /Pulse Period) × 100 1.0 3.3 6.0 %
COMP Clamp Voltage VFB = 0 V; VSS = 0 0.50 0.95 1.10 V
V

SS Fault Disable V

FFB

GATE(H)

= Low; V

= Low 0.9 1.0 1.1 V

GATE(L)

High Threshold − − 2.5 3.0 V

PWM Comparator

Transient Response V

V

Bias Current V

FFB

= 0 to 5.0 V to V

FFB

V

= V

CC1

FFB

= 12 V

CC2

= 0 V − 0.3 −

= 9.0 V to 1.0 V;

GATE(H)

− 100 125 ns

2. Guaranteed by design, not 100% tested in production.

mA

mA

kW

mA

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3

CS5157H

ELECTRICAL CHARACTERISTICS (0°C < T

V

= V

ID4

ID2

= V

ID1

= V

ID0

= 1; V

ID3

= 0

;

CV

GATE(L)

< +70°C; 0°C < TJ < +125 °C; 8. 0 V < V

A

and CV

GATE(H)

= 1.0 nF; C

= 330 pF; CSS = 0.1 mF, unless otherwise spec if ied.)

OFF

< 14 V; 5.0 V < V

CC1

< 20 V;DAC Code:

CC2

Characteristic Test Conditions Min Typ Max Unit

DAC

Input Threshold V
Input Pullup Resistance V

ID0,

ID0,

V

, V

, V
, V

ID3

ID3

, V
, V

ID4

ID4

ID1

ID2

V

, V

ID1

ID2

1.00 1.25 2.40 V
25 50 100

Pullup Voltage − 4.85 5.00 5.15 V
Accuracy (all codes exc ept 11111) Measure VFB = V

V

ID4VID3VID2VID1VID0

, 25°C ≤ TJ ≤ 125°C − − 1.0 %

COMP

0 1 1 1 1 − 1.2870 1.3000 1.3130 V
0 1 1 1 0 − 1.3365 1.3500 1.3635 V
0 1 1 0 1 − 1.3860 1.4000 1.4140 V
0 1 1 0 0 − 1.4355 1.4500 1.4645 V
0 1 0 1 1 − 1.4850 1.5000 1.5150 V
0 1 0 1 0 − 1.5345 1.5500 1.5655 V
0 1 0 0 1 − 1.5840 1.6000 1.6160 V
0 1 0 0 0 − 1.6335 1.6500 1.6665 V
0 0 1 1 1 − 1.6830 1.7000 1.7170 V
0 0 1 1 0 − 1.7325 1.7500 1.7675 V
0 0 1 0 1 − 1.7820 1.8000 1.8180 V
0 0 1 0 0 − 1.8315 1.8500 1.8685 V
0 0 0 1 1 − 1.8810 1.9000 1.9190 V
0 0 0 1 0 − 1.9305 1.9500 1.9695 V
0 0 0 0 1 − 1.9800 2.0000 2.0200 V
0 0 0 0 0 − 2.0295 2.0500 2.0705 V
1 1 1 1 1 − 1.2191 1.2440 1.2689 V
1 1 1 1 0 − 2.0790 2.1000 2.1210 V
1 1 1 0 1 − 2.1780 2.2000 2.2220 V
1 1 1 0 0 − 2.2770 2.3000 2.3230 V
1 1 0 1 1 − 2.3760 2.4000 2.4240 V
1 1 0 1 0 − 2.4750 2.5000 2.5250 V
1 1 0 0 1 − 2.5740 2.6000 2.6260 V
1 1 0 0 0 − 2.6730 2.7000 2.7270 V
1 0 1 1 1 − 2.7720 2.8000 2.8280 V
1 0 1 1 0 − 2.8710 2.9000 2.9290 V
1 0 1 0 1 − 2.9700 3.0000 3.0300 V
1 0 1 0 0 − 3.0690 3.1000 3.1310 V
1 0 0 1 1 − 3.1680 3.2000 3.2320 V
1 0 0 1 0 − 3.2670 3.3000 3.3330 V
1 0 0 0 1 − 3.3660 3.4000 3.4340 V
1 0 0 0 0 − 3.4650 3.5000 3.5350 V

kW

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4

CS5157H

PIN SYMBOL

FUNCTION

ELECTRICAL CHARACTERISTICS (0°C < T

V

= V

ID4

ID2

= V

ID1

= V

ID0

= 1; V

ID3

= 0

;

CV

GATE(L)

Characteristic UnitMaxTypMinTest Conditions

Supply Current

I

CC1

I

CC2

Operating I
Operating I

C

OFF

CC1

CC2

Normal Charge Time V

No Switching − 8.5 13.5 mA
No Switching − 1.6 3.0 mA
VFB = COMP = V
VFB = COMP = V

FFB

Extension Charge Time VSS = V
Discharge Current C

OFF

Time Out Timer

Time Out Time VFB = V

Record V

Fault Mode Duty Cycle V

FFB

PACKAGE PIN DESCRIPTION

PACKAGE PIN #

SOIC−16

1, 2, 3, 4, 6 V

ID0−VID4

Voltage ID DAC input pins. These pins are internally pulled up to 5.0 V providing logic ones if left
open. V

3.50 V with 100 mV increments. When V

2.05 V with 50 mV increments. V
5 DAC input pins open results in a DAC output voltage of 1.2440 V, allowing for adjustable output
voltage, using a traditional resistor divider.

< +70°C; 0°C < TJ < +125 °C; 8. 0 V < V

A

and CV

GATE(H)

FFB

FFB

= 1.0 nF; C

= 330 pF; CSS = 0.1 mF, unless otherwise spec if ied.)

OFF

< 14 V; 5.0 V < V

CC1

− 8.0 13 mA

− 2.0 5.0 mA

= 1.5 V; VSS = 5.0 V 1.0 1.6 2.2

= 0 5.0 8.0 11.0

FFB

< 20 V;DAC Code:

CC2

ms
ms

to 5.0 V; VFB > 1.0 V 5.0 − − mA

; V

COMP

GATE(H)

= 2.0 V;

FFB

Pulse High Duration

10 30 65

ms

= 0V 35 50 70 %

selects the DAC range. When V

ID4

− V

ID0

is High (logic one), the DAC range is 2.10 V to

ID4

is Low (logic zero), the DAC range is 1.30 V to

ID4

select the desired DAC output voltage. Leaving all

ID4

5 SS

Soft−Start Pin. A capacitor from this pin to LGND in conjunction with internal 60 mA current
source provides Soft−Start function for the controller. This pin disables fault detect function
during Soft−Start. When a fault is detected, the Soft−Start capacitor is slowly discharged by
internal 2.0 mA current source setting the time out before trying to restart the IC.
Charge/discharge current ratio of 30 sets the duty cycle for the IC when the regulator output is
shorted.

7 C

8 V

9 V

10 V

OFF

FFB

CC2

GATE(H)

A capacitor from this pin to ground sets the time duration for the on board one shot, which is
used for the constant off time architecture.

Fast feedback connection to the PWM comparator. This pin is connected to the regulator output.
The inner feedback loop terminates on time.

Boosted power for the high side gate driver.
High FET driver pin capable of 1.5 A peak switching current. Internal circuit prevents V

and V

from being in high state simultaneously.

GATE(L)

GATE(H)

11 PGND High current ground for the IC. The MOSFET driver is referenced to this pin. Input capacitor

ground and the source of lower FET should be tied to this pin.
12 V
13 V

GATE(L)

CC1

Low FET driver pin capable of 1.5 A peak switching current.

Input power for the IC and low side gate driver.
14 LGND Signal ground for the IC. All control circuits are referenced to this pin.
15 COMP Error amplifier compensation pin. A capacitor to ground should be provided externally to

compensate the amplifier.
16 V

FB

Error amplifier DC feedback input. This is the master voltage feedback which sets the output

voltage. This pin can be connected directly to the output or a remote sense trace.

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5

V

)

L)

C

CC1

SS

V

ID0

V

ID1

V

ID2

V

ID3

V

ID4

V

OMP

V

FFB

LGnd

FB

V

CC1

Comparator

−

+

3.90 V

3.85V

5 BIT
DAC

Slow Feedback

Fast Feedback

Monitor

Error
Amplifier

+

−

1.0 V

60 mA

2.0 mA

PWM
Comparator

−
+

−
+

V

FFB

Comparator

5.0 V

Low

2.5 V

CS5157H

SS Low

−

Comparator

+

0.7 V
SS High

Comparator

+

−

Maximum

On−Time

Timeout

Normal

Off−Time

Timeout

Extended

Off−Time

Timeout

Q

R

Q

S

FAULT

Latch

Off−Time

Timeout

FAULT

FAULT

R
S

PMW
Latch

GATE(H) = ON

Q

GATE(H) = OFF

Q

One Shot

V

CC2

V

GATE(H

PGnd

V

CC1

V

GATE(

PGnd

C

OFF

R

Q

S

C

OFF

PWM COMP

Figure 2. Block Diagram

APPLICATIONS INFORMATION

THEORY OF OPERATION

V2 Control Method

The V2 method of control uses a ramp signal that is
generated by the ESR of the output capacitors. This ramp is
proportional to the AC current through the main inductor
and is offset by the value of the DC output voltage. This
control scheme inherently compensates for variation in
either line or load conditions, since the ramp signal is
generated from the output voltage itself. This control
scheme inherently compensates for variation in either line or
load conditions, since the ramp signal is generated from the
output voltage itself. This control scheme differs from
traditional techniques such as voltage mode, which
generates an artificial ramp, and current mode, which
generates a ramp from inductor current.

COMP

Time−Out

Timer

(30 ms)

Edge Triggered

PWM
Comparator

+

C

−

Ramp
Signal

Error

Amplifier

Error

Signal

Figure 3. V2 Control Diagram

V

GATE(H)

V

GATE(L)

V

FFB

Output
Voltage
Feedback

V

FB

−

E

+

Reference

Voltage

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6

CS5157H

The V2 control m et hod i s i ll ust rated in Figure 3. The output
voltage is used to generate both the error signal and the ramp
signal. Since the ramp signal is simply the output voltage, it is
affected by any c hange i n t he output r egardless o f the origin of
that change. The ramp signal also contains the DC portion of
the output voltage, which allows the control circuit t o drive t he
main switch to 0% or 100% duty cycle as required.

A change in line voltage changes the current ramp in the
inductor, a ffecting t he ramp signal, w hich causes the V2 cont rol
scheme to compensate the duty cycle. Since the change in
inductor current modifies the ramp signal, as in current mode
control, the V2 control s cheme h as t he s ame a dvantages i n l ine
transient response.

A change in load current will have an affect on the output
voltage, altering the ramp signal. A load step immediately
changes the state of t he comparator output, which controls the
main switch. L oad t ransient r esponse i s d etermined o nly b y the
comparator response time and the transition speed of the main
switch. The reaction time t o a n o utput l oad s tep h as n o r elation
to the crossover frequency of the error signal loop, as in
traditional control methods.

The error signal loop can have a low crossover frequency,
since transient response is handled by the ramp signal loop.
The main purpose of this ‘slow’ feedback loop is to provide
DC accuracy. Noise immunity i s significantly improved, s ince
the error amplifier bandwidth can be rolled off at a low
frequency. E nhanced n oise immuni ty improves remote s ensing
of the output voltage, since the noise associated with long
feedback traces can be effectively filtered.

Line and load regulation are drastically improved because
there are two independent voltage loops. A voltage mode
controller relies o n a c hange in t he e rror si gnal t o compensate f or
a deviation i n e i ther l ine o r l oad v ol tage. T his change in the e rror
signal causes the output voltage to change corresponding to the
gain of the error amplifier, which is normally specified as line
and load regulation. A current mode controller maintains fixed
error signal under deviation in the line voltage, since the slope
of the ramp signal changes, but still relies on a change in the
error signal for a deviation in load. The V2 method of control
maintains a fixed error signal for both line and load variation,
since the ramp signal is affected by both line and load.

Constant Off Time

To maximize transient response, the CS5157H uses a
constant off time method to control the rate of output pulses.
During normal operation, the off time of the high side switch
is terminated after a f ixed period, s et by t he C

capacitor . To

OFF

maintain regulation, the V2 control loop varies switch on time.
The PWM comparator monitors the output voltage ramp, and
terminates the switch on time.

Constant off time provides a number of advantages. Switch
duty cycle can b e a djusted f rom 0 t o 1 00% o n a p uls e by p uls e
basis when responding to transient conditions. Both 0% and
100% duty cycle operation can be maintained for extended
periods of time in response to load or line transients. PWM
slope compensation to avoid s ub− harmonic o scillations a t h igh
duty cycles is avoided.

Switch on time is limited by an internal 25 ms timer,

minimizing stress to the power components.

Programmable Output

The CS5157H is designed to provide two methods for
programming the output voltage o f t he p ower supply. A five
bit on board digital to analog converter (DAC) is used to
program the output voltage withi n two di f ferent ranges . T he
first range is 2 .10 V t o 3.50 V i n 100 m V s teps, t he second is

1.30 V to 2.05 V in 50 mV steps, depending on the digital
input code. If all five bits are left open, the CS5157H enters
adjust mode. In adjust mode, the designer can choose any
output voltage by using resistor divi der feedback to the V
and V

Startup

pins, as in traditional controllers.

FFB

Until the voltage o n t he V

supply pin exceeds the 3.9 V

CC1

FB

monitor threshold, the Soft −Start and g at e p i ns are held low.
The FAULT latch i s r es et ( no Fault condition). The o utput of
the error amplifier (COMP) is pulled up to 1.0 V by the
comparator clamp. When the V

pin exceeds the monitor

CC1

threshold, the GATE(H) output is activated, and the
Soft−Start capacitor begins charging. The GATE(H) output
will remain on , enabling the NFET switch, until terminated
by either the PWM comparator, or the maximum on time
timer.

If the maximum on time is exceeded before the regulator
output voltage achieves the 1.0 V level, the pulse is
terminated. The GATE(H) pin drives low, and the GATE(L)
pin drives high f or t he d uration o f t he e xtended of f t ime. T his
time is set by the time out timer and is approximately equal
to the maximum on time, resulting in a 50% duty cycle. The
GATE(L) pin w ill t hen d rive l ow, the G ATE(H) pin will d rive
high, and the cycle repeats.

When regulator output voltage achieves the 1.0 V level
present at the COMP pin, regulation has been achieved and
normal off t ime w ill e nsue. T he P WM c omparator t erminates
the switch on time, with off time set by the C

capacitor.

OFF

The V2 control loop will adjust switch duty cycle as required
to ensure t he regulator output v oltage t racks t he output of the
error amplifier.

The Soft−Start and COMP capacitors will charge to their
final levels, providing a controlled turn on of the regulator
output. Regulator turn on time is determined by the COMP
capacitor charging to its final val ue. Its voltage is limited by
the Soft−Start C OMP c lamp a nd t he v oltage o n t he Soft−Start
pin (see Figures 4 and 5 ).

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7

.

O

o

M 250 ms

Trace 1− Regulator Output Voltage (1.0 V/div.)
Trace 2− Inductor Switching Node (2.0 V/div.)
Trace 3− 12 V Input (V
Trace 4− 5.0 V Input (1.0 V/div.)

CC1

and V

) (5.0 V/div.)

CC2

Figure 4. CS5157H Demonstration Board Startup in

Response to Increasing 12 V and 5.0 V Input Voltages

Extended Off Time is Followed by Normal Off Time

peration when Output Voltage Achieves Regulation t

the Error Amplifier Output.

CS5157H

Trace 1− Regulator Output Voltage (5.0 V/div.)
Trace 2− Inductor Switching Node (5.0 V/div.)

Normal Operation

During normal operation, switch off time is constant and
set by the C
V2 control loop to maintain regulation. This results in
changes in regulator switching frequency, duty cycle, and
output ripple in response to changes in load and line. Output
voltage ripple will be determined by inductor ripple current
working into the ESR of the output capacitors (see Figures
7 and 8).

M 10.0 ms

Figure 6. CS5157H Demonstration Board Enable

Startup Waveforms

capacitor. Switch on time is adjusted by the

OFF

M 2.50 ms

Trace 1− Regulator Output Voltage (1.0 V/div.)
Trace 3− COMP PIn (error amplifier output) (1.0 V/div.)
Trace 4− Soft−Start Pin (2.0 V/div.)

Figure 5. CS5157H Demonstration Board Startup

Waveforms

If the input voltage rises quickly, or the regulator output
is enabled externally, output voltage will increase to the
level set by the error amplifier output more rapidly, usually
within a couple of cycles (see Figure 6).

M 1.00 ms

Trace 1− Regulator Output Voltage (10 mV/div.)

Trace 2− Inductor Switching Node (5.0 V/div.)

Figure 7. Peak−to−Peak Ripple on V

I

= 0.5 A (Light Load)

OUT

OUT

= 2.8 V,

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8

CS5157H

F

o
o

M 1.00 ms

Trace 1− Regulator Output Voltage (10 mV/div.)
Trace 2− Inductor Switching Node (5.0 V/div.)

Figure 8. Peak−to−Peak Ripple on V

I

= 13 A (Heavy Load)

OUT

Transient Response

The CS5157H V2 control loop’s 100 ns reaction time
provides unprecedented transient response to changes in
input voltage or output current. Pulse by pulse adjustment of
duty cycle is provided to quickly ramp the inductor current
to the required level. Since the inductor current cannot be
changed instantaneously, regulation is maintained by the
output capacitor(s) during the time required to slew the
inductor current.

For best transient response, a combination of a number of
high frequency and bulk output capacitors are usually used.

If the maximum on time is exceeded while responding to
a sudden increase in load current, a normal off time occurs
to prevent saturation of the output inductor.

OUT

= 2.8 V,

Trace 1− Regulator Output Voltage (100 mV/div.)
Trace 2− Inductor Switching Node (5.0 V/div.)
Trace 3− Output Current (0.5 to 13 Amps) (10 A/div.)

igure 10. CS5157H Demonstration Board Response t

13 A Load Turn On (Output Set for 2.8 V). Upon

2

Completing a Normal Off Time, The V

Control Loop

Immediately Connects the Inductor to the Input

Voltage, Providing 100% Duty Cycle. Regulation is

Achieved in Less Than 20 ms

Trace 1− Regulator Output Voltage (100 mV/div.)
Trace 2− Inductor Switching Node (5.0 V/div.)
Trace 3− Output Current (13 to 0,5 Amps) (10 A/div.)

Figure 11. CS5157H Demonstration Board Response t

13 A Load Turn Off (Output Set for 2.8 V). V2 Control
Topology Immediately Connects Inductor to Ground,

Providing 0% Duty Cycle. Regulation is Achieved in

Less Than 10 ms

PROTECTION AND MONITORING FEATURES

V

Monitor

CC1

To maintain predictable startup and shutdown

characteristics an internal V

Trace 1− Regulator Output Voltage (100 mV/div.)

Trace 2− Regulator Output Voltage (10 A/div.)

Figure 9. CS5157H Demonstration Board Response

to a 0.5 to 13 A Load Pulse (Output Set for 2.8 V)

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prevent the part from operating below 3.75 V minimum
startup. The V

monitor comparator provides hysteresis

CC1

and guarantees a 3.70 V minimum shutdown threshold.

9

monitor circuit is used to

CC1

CS5157H

d

Short Circuit Protection

A lossless hiccup mode short circuit protection feature is
provided, requiring only the Soft−Start capacitor to
implement. If a s hort c ircuit c ondition o ccurs ( V
the V

low comparator sets the FAULT latch. This causes

FFB

the M OSFET t o s hut o ff, d isc onnecting t he r egul ator f rom i t’s
input voltage. The Soft−Start capacitor is then slowly
discharged by a 2.0 mA current source until it reaches it’s
lower 0.7 V threshold. The regulator will then attempt to
restart normally, operating i n i t ’ s e xtended o ff t ime m ode with
a 50% duty cycle, while the Soft−Start capacitor is charged
with a 60 mA charge current.

If the short circuit cond ition persists, the regulato r ou tput
will not achieve the 1.0 V low V

comparator threshold

FFB

before the Soft− S tart c apacitor is charged to it’s upper 2.5 V
threshold. If this happens the cycle will repeat itself until the
short is removed. The Soft−Start charge/discharge current
ratio sets t he d uty c ycle f or t he p ulses ( 2.0 mA/60 mA = 3.3%),
while actual d uty c ycle i s h alf t hat d ue t o the e xtended o ff t ime
mode (1.65%).

This protection feature results in less stress to the
regulator components, input power supply, and PC board
traces than occurs with constant current limit protection (see
Figures 12 and 13).

If the short circuit condition is removed, output voltage
will rise above the 1.0 V level, preventing the F AULT latch
from being set, allowing normal operation to resume.

FFB

< 1.0 V),

Trace 4− 5.0 V from PC Power Supply (2.0 V/div.)
Trace 2− Inductor Switching Node (2.0 V/div.)

Figure 13. Startup with Regulator Output Shorted

Overvoltage Protection

M 50.0 ms

Overvoltage protection (OVP) is provided as result of the
normal operation of the V2 control topology and requires no
additional external components. The control loop responds
to an overvoltage condition within 100 ns, causing the top
MOSFET to shut off, disconnecting the regulator from it’s
input voltage. The bottom MOSFET is then activated,
resulting in a “crowbar” action to clamp the output voltage
and prevent damage to the load (see Figures 14 and 15 ). The
regulator will remain in this state until the overvoltage
condition ceases or the input voltage is pulled low. The
bottom FET and board trace must be properly designed to
implement the OVP function.

M 25.0 ms

Trace 4− 5.0 V Supply Voltage (2.0 V/div.)
Trace 3− Soft−Start Timing Capacitor (1.0 V/div.)
Trace 2− Inductor Switching Node (2.0 V/div.)

Figure 12. CS5157H Demonstration Board Hiccup

Mode Short Circuit Protection. Gate Pulses are

Delivered While the Soft−Start Capacitor Charges, an

Cease During Discharge

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Trace 4− 5.0 V from PC Power Supply (5.0 V/div.)

M 10.0 ms

Trace 1− Regulator Output Voltage (1.0 V/div.)

Trace 2− Inductor Switching Node (5.0 V/div.)

Figure 14. OVP Response to an Input−to−Output

Short Circuit by Immediately Providing 0% Duty

Cycle, Crow−Barring the Input Voltage to Ground

10

CS5157H

t

H

5.0 V

Trace 4− 5.0 V from PC Power Supply (2.0 V/div.)
Trace 1− Regulator Output Voltage (1.0 V/div.)

M 5.00 ms

Figure 15. OVP Response to an Input−to−Output Shor

Circuit by Pulling the Input Voltage to Ground

External Output Enable Circuit

On/off control of the regulator can be implemented
through the addition of two additional discrete components
(see Figure 16). This circuit operates by pulling the
Soft−Start pin high, and the V

pin low, emulating a short

FFB

circuit condition.

5.0 V

MMUN2111T1 (SOT−23)

5

SS

Power Good

PN3904

V

OUT

CS5157H

R1

10 k

R2

6.2 k

R3

10 k

PN3904

Figure 17. Implementing Power Good with the CS5157

M 2.50 ms

Trace 3 − 12 V Input (V
Trace 4− 5.0 V Input (2.0 V/div.)
Trace 1− Regulator Output Voltage (1.0 V/div.)
Trace 2− Power Good Signal (2.0 V/div.)

CC1

) and (V

) (10 V/div.)

CC2

Figure 18. CS5157H Demonstration Board During

Power Up. Power Good Signal is Activated when

Output Voltage Reaches 1.70 V.

CS5157H

8

V

FFB

IN4148

Shutdown

Input

Figure 16. Implementing Shutdown with the CS5157H

External Power Good Circuit

An optional Power Good signal can be generated through
the use of four additional external components (see
Figure 17). The threshold voltage of the Power Good signal
can be adjusted per the following equation:

V

Power Good

(R1 ) R2) 0.65 V

+

R2

This circuit provides an open collector output that drives
the Power Good output to ground for regulator voltages less
than V

Power Good

.

Selecting External Components

The CS5157H can be used with a wide range of external
power components to optimize the cost and performance of
a particular design. The following information can be used
as general guidelines to assist in their selection.

NFET Power Transistors

Both logic level and standard MOSFETs can be used. The
reference designs derive gate drive from the 12 V supply
which is generally available in most computer systems and

utilize logic level MOSFETs. Multiple MOSFETs may be
paralleled to reduce losses and improve efficiency and
thermal management.

Voltage applied to the MOSFET gates depends on the
application circuit used. Both upper and lower gate driver
outputs are specified to drive to within 1.5 V of ground when
in the low state and to within 2.0 V of their respective bias
supplies when in the high state. In practice, the MOSFET
gates will be driven rail to rail due to overshoot caused by the

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11

CS5157H

V

BD

I

LOAD

conduction time switching frequency

capacitive load they present to the controller IC. For the
typical application where V

CC1

= V

= 12 V and 5.0 V is

CC2

used as the source for the regulator output current, the
following gate drive is provided;

V

GATE(H)

+ 12 V * 5.0 V + 7.0 V, V

GATE(L)

+ 12 V

(see Figure 19.)

M 1.00 ms

Trace 3 = V
Math 1 = V
Trace 4 = V
Trace 2− Inductor Switching Nodes (5.0 V/div.)

Figure 19. CS5157H Gate Drive Waveforms Depicting

GATE(H)

GATE(H)

GATE(L)

(10 V/div.)

− 5.0 V

IN

(10 V/div.)

Rail to Rail Swing

The most important aspect of MOSFET performance is
RDSON, which effects regulator efficiency and MOSFET
thermal management requirements.

The power dissipated by the MOSFETs may be estimated
as follows;

Switching MOSFET:

Power + I

LOAD

2

RDSON duty cycle

Synchronous MOSFET:

Power + I

LOAD

2

RDS

ON

(

1 * duty cycle

)

Duty Cycle =

V

) (I

OUT

VIN)(I

ƪ

Off Time Capacitor (C

The C

When the V
the C

OFF

LOAD

* (I

LOAD

timing capacitor sets the regulator off time:

OFF

FFB

capacitor is reduced. The extended off time can be

LOAD

RDS

T

OFF

RDS

RDS

OFF

+ C

ON OF SYNCH FET

ON OF SYNCH FET

ON OF SWITCH FET

)

4848.5

OFF

)

)

ƫ

)

pin is less than 1.0 V, the current charging

calculated as follows:

T

+ C

OFF

Off time will be determined by either the T

OFF

24, 242.5

time, or the

OFF

time out timer, whichever is longer.

The preceding equations for duty cycle can also be used
to calculate the regulator switching frequency and select the
C

timing capacitor:

OFF

C

OFF

Perioid (1 * duty cycle

+

4848.5

)

where:

Period +

Schottky Diode for Synchronous MOSFET

switching frequency

1

A Schottky diode may be placed in parallel with the
synchronous MOSFET to conduct the inductor current upon
turn off of the switching MOSFET to improve efficiency.
The CS5157H reference circuit does not use this device due
to it’s excellent design. Instead, the body diode of the
synchronous MOSFET is utilized to reduce cost and
conducts the inductor current. For a design operating at
200 kHz or so, the low non−overlap time combined with
Schottky forward recovery time may make the benefits of
this device not worth the additional expense (see Figure 8,
channel 2). The power dissipation in the synchronous
MOSFET due to body diode conduction can be estimated by
the following equation:

+

Where VBD = the forward drop of the MOSFET body
diode. For the CS5157H demonstration board as shown in
Figure 8;

Power + 1.6 V 13 A 100 ns 233 kHz + 0.48 W

This is only 1.3% of the 36.4 W being delivered to the
load.

Input and Output Capacitors

These components must be selected and placed carefully
to yield optimal results. Capacitors should be chosen to
provide acceptable ripple on the input supply lines and
regulator output voltage. Key specifications for input
capacitors are their ripple rating, while ESR is important for
output capacitors. For best transient response, a combination
of low value/high frequency and bulk capacitors placed
close to the load will be required.

Output Inductor

The inductor should be selected based on its inductance,
current capability, and DC resistance. Increasing the
inductor value will decrease output voltage ripple, but
degrade transient response.

THERMAL MANAGEMENT

Thermal Considerations for Power
MOSFETs and Diodes

In order to maintain good reliability, the junction
temperature of the semiconductor components should be
kept to a maximum of 150°C or lower. The thermal
impedance (junction to ambient) required to meet this
requirement can be calculated as follows:

Thermal Impedance +

T

JUNCTION(MAX)

Power

* T

AMBIENT

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12

CS5157H

F

V

To the negative terminal

A heatsink may be added to TO−220 components to
reduce their thermal impedance. A number of PC board
layout techniques such as thermal vias and additional copper
foil area can be used to improve the power handling
capability of surface mount components.

EMI Management

As a consequence of large currents being turned on and off
at high frequency, switching regulators generate noise as a
consequence of their normal operation. When designing for
compliance with EMI/EMC regulations, additional
components may be added to reduce noise emissions. These
components are not required for regulator operation and
experimental results may allow them to be eliminated. The
input filter i nductor m ay n ot b e r equired becaus e b ulk f ilter a nd
bypass capacitors, as well as other loads located on the board
will tend to redu ce regulator di/dt effects on the circuit board
and input power s upply. Placement o f t he p ower c omponent t o
minimize routing distance will also help to reduce emissions.

2.0 mH

33 W

1000 pF

Layout Guidelines

1. Place 12 V filter capacitor next to the IC and connect
capacitor ground to pin 11 (PGND).

2. Connect pin 11 (PGND) with a separate trace to the
ground terminals of the 5.0 V input capacitors.

3. Place fast feedback filter capacitor next to pin 8 (V

FFB

and connect it’s ground terminal with a separate, wide
trace directly to pin 14 (LGND).

4. Connect the ground terminals of the Compensation
capacitor directly to the ground of the fast feedback
filter capacitor to prevent common mode noise from
effecting the PWM comparator.

5. Place the output filter capacitor(s) as close to the load
as possible and connect the ground terminal to pin 14
(LGND).

6. Connect the V

pin directly to the load with a separate

FB

trace (remote sense).

7. Place 5.0 V input capacitors close to the switching
MOSFET and synchronous MOSFET.

Route gate drive signals V

GATE(H)

(pin 10) and V

GATE(L)

(pin 12 when used) with traces that are a minimum of 0.025
inches wide.

1.0 mF

COMP

V

CC

0.1 mF
15 11

of the input capacitors

)

Figure 20. Filter Components

2.0 mH
5

+

1200 pF × 3.0/16 V

Figure 21. Input Filter

Soft−Start

To the negative terminal of the output capacitors

Figure 22. Layout Guidelines

8

OFF TIME

100 p

V

FFB

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13

5.0V

MBRS

120

0.1 mF

CS5157H

MBRS120

0.1 mF

0.33 mF

330 pF

MBRS120

1.0 mF
V

CC1

V

ID0

V

ID1

V

ID2

V

ID3

V

ID4

C

OFF

SS
COMP

V

CC2

CS5157H

LGND

V

GATE(H)

V

GATE(L)

PGND

1.0 mF1.0 mF

Si4410DY

V

FB

V

FFB

3.3 k

+

Si9410DY

100 pF

Figure 23. Additional Application Diagram, 5.0 V to 3.3 V/10 A Converter

100 mF/10 V × 3

Tantalum

3.0 mH

+

3.3 V/10 A

100 mF/10 V × 3

Tantalum

0.1 mF

3.3 V

Si9410

33 mF/25 V × 3

+

Tantalum

5.0 mH

1.0 mF

330 pF

0.33 mF

12 V

V

CC1

V

ID0

V

ID1

V

ID2

V

ID3

V

ID4

C

OFF

SS
COMP

V

CC2

CS5157H

LGND

V

GATE(H)

V

GATE(L)

PGND

Si9410

V

FB

3.3 k

V

FFB

100 pF

Figure 24. Additional Application Diagram, 3.3 V to 2.5 V/7.0 A Converter with 12 V Bias

+

100 mF/10 V × 2
Tantalum

2.5 V/7.0 A

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14

5.0V

MBRS

120

0.1 mF

CS5157H

MBRS120

Si9410

+

100 mF/10 V × 3

Tantalum

3.0 mH

10 W

MBRS120

1.0 mF

1.0 mF1.0 mF

V

CC1

V

ID0

V

ID1

V

ID2

V

ID3

V

ID4

C

OFF

V

CC2

CS5157H

V

GATE(H)

V

GATE(L)

V

FB

Si4410

330 pF

0.1 mF

SS

COMP

LGND

0.33 mF

PGND

V

FFB

3.3 k

100 pF

Figure 25. Additional Application Diagram, 5.0 V to 3.3 V/10 A Converter with Current Sharing

Remote

Sense

3.3 V/10 A

100 mF/10 V × 3

+

Tantalum

Connect to other
circuits for current
sharing

0.1 mF

1.0 mF

330 pF

V

V

C

SS

COMP

0.33 mF

V
V
V

12 V

V

CC1

ID0

ID1

ID2
ID3

ID4

OFF

1N5818

22 W

1/4 W

1.0 mF

CS5157H

LGND

V

CC2

1N5818

V

GATE(H)

V

V

GATE(L)

PGND

V

FFB

FB

100 pF

1N4746

1.0 W

18 V

0.1 mF
FY10AAJ03

FY10AAJ03

3.3 k

12 V

820 mF/16 V × 4

+

Aluminum
Electrolytic

1.1 mH

FY10AAJ03

+

1200 mF/10 V × 2

Aluminum
Electrolytic

3.3 V/5.0 A

Figure 26. Additional Application Diagram, 12 V to 3.3 V/5.0 A Converter with Remote Sense

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15

CS5157H

PACKAGE DIMENSIONS

SOIC−16

D SUFFIX

CASE 751B−05

ISSUE J

−T−

−A−

16 9

−B−

18

G

K

C

SEATING

PLANE

D

16 PL

0.25 (0.010) A

M

S

B

T

S

PACKAGE THERMAL DATA

Parameter SOIC−16 Unit

R

q

JC

R

q

JA

8 PLP

0.25 (0.010) B

M

M

S

R X 45

_

F

J

Typical 28 °C/W
Typical 115 °C/W

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

DIM MIN MAX MIN MAX

A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7

____

P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019

INCHESMILLIMETERS

V2 is a trademark of Switch Power, Inc.
Pentium is a registered trademark of Intel Corporation.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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CS5157H/D

16