ON Semiconductor CS51021A, CS51022A, CS51023A, CS51024A Technical data

查询CS51021A供应商

CS51021A, CS51022A,
CS51023A, CS51024A

Enhanced Current Mode
PWM Controller

The CS51021A/2A/3A/4A Fixed Frequency PWM Current Mode
Controller family provides all necessary features required for AC–DC
or DC–DC primary side control. Several features are included
eliminating the additional components needed to implement them
externally. In addition to low start–up current (75 µA) and high
frequency operation capability, the CS51021A/2A/3A/4A family
includes overvoltage and undervoltage monitoring, externally
programmable dual threshold overcurrent protection, current sense
leading edge blanking, current slope compensation, accurate duty cycle
control and an externally available 5.0 V reference. The CS51021A
and CS51023A feature bidirectional synchronization capability, while
the CS51022A and CS51024A offer a sleep mode with 100 µA
maximum IC current consumption. The CS51021A/2A/3A/4A family
is available in a 16 lead narrow body SO package.

Device Sleep/Synch VCC Start/Stop

CS51021A Synch 8.25 V/7.7 V
CS51022A Sleep 8.25 V/7.7 V
CS51023A Synch 13 V/7.7 V
CS51024A Sleep 13 V/7.7 V

Features

• 75 µA Max. Startup Current

• Fixed Frequency Current Mode Control

• 1.0 MHz Switching Frequency

• Undervoltage Protection Monitor

• Overvoltage Protection Monitor with Programmable Hysteresis

• Programmable Dual Threshold Overcurrent Protection with

Delayed Restart

• Programmable Soft Start

• Accurate Maximum Duty Cycle Limit

• Programmable Slope Compensation

• Leading Edge Current Sense Blanking

• 1.0 A Sink/Source Gate Drive

• Bidirectional Synchronization (CS51021A/3A)

• 50 ns PWM Propagation Delay

• 100 µA Max Sleep Current (CS51022A/4A)

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SO–16

16

1

PIN CONNECTIONS AND

MARKING DIAGRAM

1

GATE

SLEEP or SYNC

CS51021AED16 SO–16 48 Units/Rail
CS51021AEDR16 SO–16 2500 Tape & Reel
CS51022AED16 SO–16 48 Units/Rail
CS51022AEDR16 SO–16 2500 Tape & Reel
CS51023AED16 SO–16 48 Units/Rail
CS51023AEDR16 SO–16 2500 Tape & Reel
CS51024AED16 SO–16 48 Units/Rail
CS51024AEDR16 SO–16 2500 Tape & Reel

* Consult your local sales representative for other
package options.

SENSE

SLOPE

TCT

I

SET

x = Specific Device Code
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week

ORDERING INFORMATION*

Device Package Shipping

D SUFFIX

CASE 751B

16

CS5102xA

AWLYWW

V

C

PGNDI
V

CC

V

REF

LGNDUV
SSOV

COMPR
V

FB

 Semiconductor Components Industries, LLC, 2001

September, 2001 – Rev. 5

1 Publication Order Number:

CS51021A/D

PGND

V

IN

(36 V to 72 V)

51 k

CS51021A, CS51022A, CS51023A, CS51024A

100

BAS21

1.0 µF

SYNC/SLEEP

0.01 µF

11 V

10 k

330 pF

4700 pF

51 k

0.01 µF

FZT688

22 k

22 µF

V

C

V

REF

COMP
V

FB

RTC

SYNC/
SLEEP

C

SS

LGND

10

T

10 K

18 V

V

CC

UV
OV

I

SET

SLOPE

GATE

I

SENSE

CS51021A/2A

PGND

470 pF

1.0 K

24.3 k,

1.0%

6.98 k,

1.0%

200 k,

1.0%

2.49 k,

1.0%

IRF6345

6.98 k,

1.0%

180

MOC81025

BA521

100

100 p

62

TL431

10 k

100:1

1.0 k

4:1

5.1 k0.1 µF

1000 pF

10

680 pF

2.0 k,

1.0%

2:5

100 µF 100 µF

2.0 k, 1.0%

V

OUT

(5 V/5 A)

SGND

Figure 1. Typical Application Diagram, 36–72 V to 5.0 V, 5.0 A DC–DC Converter

MAXIMUM RATINGS*

Rating Value Unit

Power Supply Voltage, V
Driver Supply Voltage, V
SYNC, SLEEP, RTCT, SOFT START, VFB, SLOPE, I

C

CC

SENSE

, UV, OV, I

(Logic Pins) 0.25 to V

SET

Peak GATE Output Current 1.0 A
Steady State Output Current ±0.2 A
Operating Junction Temperature, T
Storage Temperature Range, T

J

S

ESD (Human Body Model) 2.0 kV
Lead Temperature Soldering: Reflow: (SMD styles only) (Note 1) 230 peak °C

1. 60 second maximum above 183°C.
*The maximum package power dissipation must be observed.

–0.3, 20 V
–0.3, 20 V

REF

150 °C

–65 to +150 °C

V

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2

CS51021A, CS51022A, CS51023A, CS51024A

ELECTRICAL CHARACTERISTICS (Unless otherwise stated, specifications apply for –40°C < T

–40°C < T

< 150°C, 3.0 V < VC < 20 V, 8.2 V < VCC < 20 V, RT = 12 kΩ, CT = 390 pF)

J

Characteristic

Test Conditions Min Typ Max Unit

< 85°C,

A

Under Voltage Lockout

START Threshold (CS51021A/2A) – 7.95 8.25 8.8 V
START Threshold (CS51023A/4A) – 12.4 13 13.4 V
STOP Threshold – 7.4 7.7 8.2 V
Hysteresis (CS51021A/2A) – 0.50 0.75 1.00 V
Hysteresis (CS51023A/4A) – 4.0 5.0 6.0 V
ICC @ Startup (CS51021A/2A) VCC < UV
ICC @ Startup (CS51023A/4A) VCC < UV

Threshold – 40 75 µA

START

Threshold – 45 75 µA

START

ICC Operating (CS51021A/3A) – – 7.0 9.0 mA
ICC Operating (CS51022A/4A) – – 6.0 8.0 mA
ICC Operating Includes 1.0 nF Load – 7.0 12 mA

Voltage Reference

Initial Accuracy TA = 25°C, I
Total Accuracy 1.0 mA < I
Line Regulation 8.2 V < VCC < 18 V, I
Load Regulation 1.0 mA < I

= 2.0 mA, VCC = 14 V, Note 2 4.95 5.0 5.05 V

REF

< 10 mA 4.9 5.0 5.15 V

REF

= 2.0 mA – 6.0 20 mV

REF

< 10 mA – 6.0 15 mV

REF

NOISE Voltage Note 2 – 50 – µV
OP Life Shift T = 1000 Hours, Note 2 – 4.0 20 mV
FAULT Voltage Force V
OK Voltage Force V
OK Hysteresis Force V
Current Limit Force V

REF

REF

REF

REF

0.90 × V

0.94 × V

REF

REF

0.93 × V

0.96 × V

REF

REF

0.95 × V

0.985 × V

REF

75 165 250 mV

–20 – – mA

REF

Error Amplifier

Initial Accuracy TA = 25°C, I

V

= COMP, Note 2

FB

= 2.0 mA, VCC = 14 V,

REF

2.465 2.515 2.565 V

Reference Voltage VFB = COMP 2.440 2.515 2.590 V
VFB Leakage Current VFB = 0 V – –0.2 –2.0 µA
Open Loop Gain 1.4 V < COMP < 4.0 V, Note 2 60 90 – dB
Unity Gain Bandwidth Note 2 1.5 2.5 – MHz
COMP Sink Current COMP = 1.5 V, VFB = 2.7 V 2.0 6.0 – mA
COMP Source Current COMP = 1.5 V, VFB = 2.3 V –0.2 –0.5 – mA
COMP High Voltage VFB = 2.3 V 4.35 4.8 5.0 V
COMP Low Voltage VFB = 2.7 V 0.4 0.8 1.2 V
PS Ripple Rejection FREQ = 120 Hz, Note 2 60 85 – dB
SS Clamp, V
I

Clamp Note 2 0.95 1.0 1.15 V

LIM(SET)

COMP

VSS = 2.5 V, VFB = 0 V, I

= 2.0 V 2.4 2.5 2.6 V

SET

2. Guaranteed by design, not 100% tested in production.

V
V

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3

CS51021A, CS51022A, CS51023A, CS51024A

ELECTRICAL CHARACTERISTICS (continued) (Unless otherwise stated, specifications apply for –40°C < T

–40°C < T

< 150°C, 3.0 V < VC < 20 V, 8.2 V < VCC < 20 V, RT = 12 kΩ, CT = 390 pF)

J

< 85°C,

A

Characteristic UnitMaxTypMinTest Conditions

Oscillator

Accuracy RT = 12 k, CT = 390 pF 230 255 280 kHz
Voltage Stability Delta Frequency 8.2 V < VCC < 20 V – 2.0 3.0 %
Temperature Stability T

< TA < T

MIN

Note 3 – 8.0 – %

MAX,

Min Charge & Discharge Time Note 3 0.333 – – µs
Duty Cycle Accuracy RT = 12 k, CT = 390 pF 70 77 83 %
Peak Voltage Note 3 – 3.0 – V
Valley Voltage Note 3 – 1.5 – V
Valley Clamp Voltage 10 k Resistor to ground on RTC

T

1.2 1.4 1.6 V
Discharge Current – 0.8 1.0 1.2 mA
Discharge Current TA = 25°C, Note 3 0.925 1.0 1.075 mA

Synchronization (CS51021A/3A)

Input Threshold – 1.0 1.5 2.7 V
Output Pulsewidth – 160 260 400 ns
Output High Voltage I

= 100 µA 3.5 4.3 4.8 V

SYNC

Input Resistance Note 3 35 70 140 kΩ
Drive Delay SYNC to GATE RESET 80 120 150 ns
Output Drive Current 1.0 k Load 1.25 2.0 3.5 mA

SLEEP (CS51022A/4A)

SLEEP Input Threshold Active High 1.0 1.5 2.7 V
SLEEP Input Current V

= 4.0 V 11 25 46 µA

SLEEP

ICC @ SLEEP VCC ≤ 15 V – 50 100 µA

GATE Driver

HIGH Voltage

Measure VC – GATE, VC = 10 V, 150 mA Load – 1.5 2.2 V
LOW Voltage Measure GATE – PGND, 150 mA SINK – 1.2 1.5 V
HIGH Voltage Clamp VC = 20 V, 1.0 nF 11 13.5 16 V
LOW Voltage Clamp Measured at 10 mA Output Current – 0.6 0.8 V
Peak Current VC = 20 V, 1.0 nF, Note 3 – 1.0 – A
UVL Leakage VC = 20 V measured at 0 V – –1.0 –50 µA
RISE Time Load = 1.0 nF, 1.0 V < GATE < 9.0 V,

= 20 V, TA = 25°C

V

C

FALL Time Load = 1.0 nF, 9.0 V > GATE > 1 .0 V,

V

= 20 V

C

– 60 100 ns

– 15 40 ns

SLOPE Compensation

Charge Current SLOPE = 2.0 V –63 –53 –43 µA
COMP Gain Fraction of slope voltage added to I

SENSE

,

0.095 0.100 0.105 V/V

Note 3

Discharge Voltage SYNC = 0 V – 0.1 0.2 V

3. Guaranteed by design, not 100% tested in production.

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4

CS51021A, CS51022A, CS51023A, CS51024A

ELECTRICAL CHARACTERISTICS (continued) (Unless otherwise stated, specifications apply for –40°C < T

–40°C < T

< 150°C, 3.0 V < VC < 20 V, 8.2 V < VCC < 20 V, RT = 12 kΩ, CT = 390 pF)

J

< 85°C,

A

Characteristic UnitMaxTypMinTest Conditions

Current Sense

OFFSET Voltage Note 4 0.09 0.10 0.11 V
Blanking Time – – 55 160 ns
Blanking Disable Voltage Adjust V

FB

1.8 2.0 2.2 V
Second Current Threshold Gain – 1.21 1.33 1.45 V/V
I

Input Resistance – – 5.0 – kΩ

SENSE

Minimum On Time GATE High to Low 30 70 110 ns
Gain Note 4 0.78 0.80 0.82 V/V

OV & UV Voltage Monitors

OV Monitor Threshold

– 2.4 2.5 2.6 V
OV Hysteresis Current – –10 –12.5 –15 µA
UV Monitor Threshold – 1.38 1.45 1.52 V
UV Monitor Hysteresis – 25 75 100 mV

SOFT START (SS)

Charge Current

SS = 2.0 V –70 –55 –40 µA
Discharge Current SS = 2.0 V 250 1000 – µA
Charge Voltage, V

SS

Discharge Voltage, V

SS

– 4.4 4.7 5.0 V
– 0.25 0.27 0.30 V

4. Guaranteed by design, not 100% tested in production.

PACKAGE PIN DESCRIPTION

PACKAGE PIN # PIN SYMBOL FUNCTION

16 Lead SO Narrow

1
2 I
3 SYNC (CS51021A/3A) Bi–directional synchronization. Locks to the highest frequency.
3 SLEEP (CS51022A/4A) Active high chip disable. In sleep mode, V
4 SLOPE Additional slope to the current sense signal. Internal current source

5 UV Undervoltage protection monitor.
6 OV Overvoltage protection monitor.
7 RTC

8 I

9 V

10 COMP Error amplifier output. Frequency compensation network is usually

11 SS
12 LGND Logic ground.

GATE External power switch driver with 1.0 A peak capability.

SENSE

Current sense amplifier input.

charges the external capacitor.

T

SET

FB

Timing resistor RT and capacitor CT determine oscillator frequency and
maximum duty cycle, D

MAX.

Voltage at this pin sets pulse–by–pulse overcurrent threshold, and sec­ond threshold (1.33 times higher) with Soft Start retrigger (hiccup mode).

Feedback voltage input. Connected to the error amplifier inverting input.

connected between COMP and V
Charging external capacitor restricts error amplifier output voltage dur-

ing the start or fault conditions (hiccup).

FB

pins.

and GATE are turned off.

REF

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5

CS51021A, CS51022A, CS51023A, CS51024A

PACKAGE PIN DESCRIPTION (continued)

PACKAGE PIN # FUNCTIONPIN SYMBOL

16 Lead SO Narrow

V

CC

LGND

LEEP

SYNC

RTC

COMP

V

SLOPE

I

SENSE

I

SET

OV

13
14 V
15 PGND Output power stage ground connection.
16 V

+

Start
Stop

+–

–

4.3 V

T

+

SS
Clamp

–

+

2.5 V

–

FB

V

REF

53 µA

Q

2

+

E/A

–

+

2.0 V

–

0.1

0.8

V

REF

12.5 µA

+
–

_OK

V

CC

–

V

FB

Monitor

+

Σ

2.5 V

V

200 ns

0.1 V

REF

V

CC

C

REF

D

+–

= 5.0 V

2

D

G

4

OSC

–

I

SET

Clamp

+

1

1.33

+

OV
Monitor

–

5.0 V reference voltage output.
Logic supply voltage.

Output power stage supply voltage.

–

V

+

+

4.75 V

–

D

10 k

3

–

PWM
Comp

+

V

ISENSE

+

2nd

Threshold

20 k

DISABLE

55 ns
Blank

–

REF

_OK

G

1

SS

Monitor

V

REF

V

C

1

Monitor

G

4.7 V

Discharge

Latch

–

UV

+

1.45 V

ZD

13.5 V

GATE

1

PGND

SS

UV

2

D

4

V

REF

55 µA

+
–

SRQ

F

–

+

+
–

G

3

FAULT

Figure 2. Block Diagram

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6

CS51021A, CS51022A, CS51023A, CS51024A

CIRCUIT DESCRIPTION

200 ns

4.3 V

SYNC

R

TCT

TCHT

0 V

0 V

0 V

0 V

0 V

V

0 V

V

SLOPE

IN

DIS

IS + 0.1 SLOPE

IS

55 ns

Blanking

SLOP
E

IS

V

COMP

PWM COMP

GATE

V

DS

Figure 3. Typical Waveforms

THEORY OF OPERATION

Powering the IC

The IC has two supply and two ground pins. VC and
PGND pins provide high speed power drive for the external
power switch. VCC and LGND pins power the control
portion of the IC. The internal logic monitors the supply
voltage, V

. During abnormal operating conditions, the

CC

output is held low. The CS51021A/2A/3A/4A requires only
75 µA of startup current.

Voltage Feedback

The output voltage is monitored via the VFB pin and is
compared with the internal 2.5 V reference. The error
amplifier output minus one diode drop is divided by 3 and
connected to the negative input of the PWM comparator.
The positive input of the PWM comparator is connected to
the modified current sense signal. The oscillator turns the
external power switch on at the beginning of each cycle.
When current sense ramp voltage exceeds the reference side
of PWM comparator, the output stage latches off. It is turned
on again at the beginning of the next oscillator cycle.

Current Sense and Protection

The current is monitored at the I

SENSE

pin. The
CS51021A/2A/3A/4A has leading edge blanking circuitry
that ignores the first 55 ns of each switching period.
Blanking is disabled when VFB is less than 2.0 V so that the
minimum on–time of the controller does not have an
additional 55 ns of delay time during fault conditions. For
the remaining portion of the switching period, the current
sense signal, combined with a fraction of the slope
compensation voltage, is applied to the positive input of the
PWM comparator where it is compared with the divided by
three error amplifier output voltage. The pulse–by–pulse
overcurrent protection threshold is set by the voltage at the
I

pin. This voltage is passed through the I

SET

Clamp and

SET

appears at the non–inverting input of the PWM comparator,
limiting its dynamic range according to the following
formula:

Overcurrent Threshold 

0.8  V

I(SENSE)

 0.1 V  0.1 V

SLOPE

where

V

I(SENSE)

is voltage at the I

SENSE

pin.

and

V

SLOPE

is voltage at the SLOPE pin.

During extreme overcurrent or short circuit conditions,
the slope of the current sense signal will become much
steeper than during normal operation. Due to loop
propagation delay, the sensed signal will overshoot the
pulse–by–pulse threshold eventually reaching the second
overcurrent protection threshold which is 1.33 times higher
than the first threshold and is described by the following
equation:

2nd Threshold  1.33  V

I(SET)

Exceeding the second threshold will reset the Soft Start
capacitor CSS and reinitiate the Soft Start sequence,
repeating for as long as the fault condition persists.

Soft Start

During power up, when the output filter capacitor is
discharged and the output voltage is low, the voltage across
the Soft Start capacitor (VSS) controls the duty cycle. An
internal current source of 55 µA char ges CSS. The maximum
error amplifier output voltage is clamped by the SS Clamp.
When the Soft Start capacitor voltage exceeds the error
amplifier output voltage, the feedback loop takes over the
duty cycle control. The Soft Start time can be estimated with
the following formula:

tSS 9 104 C

SS

The Soft Start voltage, VSS, charges and discharges
between 0.25 V and 4.7 V.

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7

CS51021A, CS51022A, CS51023A, CS51024A

Slope Compensation

DC–DC converters with current mode control require a
current sense signal with slope compensation to avoid
instability at duty cycles greater than 50%. Slope capacitor
C

is charged by an internal 53 µA current source and is

S

discharged during the oscillator discharge time. The slope
compensation voltage is divided by 10 and is added to the
current sense voltage, V

I(SENSE)

. The signal applied to the
input of the PWM comparator is a combination of these two
voltages. The slope compensation, dV

SLOPE

/dt

,

calculated using the following formula:

dV

SLOPE

 0.1

dt

53 A

C

S

It should be noted that internal capacitance of the IC will
cause an error when determining slope compensation
capacitance CS. This error is typically small for large values
of CS, but increases as CS becomes small and comparable to
the internal capacitance. The effect is apparent as a reduction
in charging current due to the need to charge the internal
capacitance in parallel with C

.Figure 4 shows a typical

S

curve indicating this decrease in available charging current.

60
55
50
45
40
35
30

Charging Current (µA)

25
20

10 100 1000

Compensation Cap (pF)

Figure 4. The Slope Compensation Pin Charge

Current Reduces When a Small Capacitor Is Used.

Undervoltage (UV) and Overvoltage (OV) Monitor

Two independent comparators monitor OV and UV
conditions. A string of three resistors is connected in series
between the monitored voltage (usually the input voltage)
and ground (see Figure 5). When voltage at the OV pin
exceeds 2.5 V, an overvoltage condition is detected and
GATE shuts down. An internal 12.5 µA current source turns
on and feeds current into the external resistor, R

, creating

3

a hysteresis determined by the value of this resistor (the
higher the value, the greater the hysteresis). The hysteresis
voltage of the OV monitor is determined by the following
formula:

V

OV(HYST)

 12.5 A  R

3

where R3 is a resistor connected from the OV pin to ground.

When the monitored voltage is low and the UV pin is less
than 1.45 V, GATE shuts down. The UV pin has fixed 75 mV
hysteresis.

Both OV and UV conditions are latched until the Soft Start
capacitor is discharged. This way, every time a fault
condition is detected the controller goes through the power
up sequence.

is

V

Figure 5. UV/OV Monitor Divider

R

1

IN

R

2

V

UV

R

3

V

OV

To calculate the OV?UV resistor divider :

1. Solve for R3, based on OV hysteresis requirements.

V

R

where V

OV(HYST)



3

V

OV(HYST)

MAX

is the desired amount of

overvoltage hysteresis, and V

 2.5 V

 12.5 A

MAX

is the input voltage

at which the supply will shut down.

2. Find the total impedance of the divider.

R

 R1 R2 R

TOT

MAX



3

3

2.5

V

 R

3. Determine the value of R2 from the UV threshold
conditions.

where V

1.45  R

R



2

is the UV voltage at which the supply

MIN

V

MIN

TOT

 R

3

will shut down.

4. Calculate R1.

R1 R

TOT

 R2 R

3

5. The undervoltage hysteresis is given by :

V

 0.075



MIN

1.45

V

REF

Monitor

V

UV(HYST)

The 5.0 V reference voltage is internally monitored to
ensure that it remains within specifications. The monitor,
which outputs a fault, can be tripped by two methods:

• If the reference voltage drops below 4.75 V

• If VCC falls below the STOP threshold

As indicated in the block diagram, any fault causes the
output to stop switching and begins the discharge of the Soft
Start capacitor C

SS

.

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8

CS51021A, CS51022A, CS51023A, CS51024A

Synchronization

A bi–directional synchronization is provided to
synchronize several controllers. When SYNC pins are
connected together, the converters will lock to the highest
switching frequency. The fastest controller becomes the
master, producing a 4.3 V, 200 ns pulse train. Only one, the
highest frequency SYNC signal, will appear on the SYNC
line.

Sleep

The sleep input is an active high input. The CS51022A/4A
is placed in sleep mode when SLEEP is driven high. In sleep
mode, the controller and MOSFET are turned off. Connect
to GND for normal operation. The sleep mode operates at
VCC ≤ 15 V.

2500

1. CT = 47 pF

2. C

= 100 pF

2000

1500

1000

Frequency (kHz)

500

1

2

3

4
5

6

8

0

7

10 15 20 25 30 35 40 45 50 5 10 15 20 25 30 35 40 45 50 55

5

R

(kΩ)

T

Figure 6. Frequency vs. RT for Discrete

Capacitor Values

3. C

4. C

5. C

6. C

7. C

8. C

T

= 150 pF

T

= 220 pF

T

= 390 pF

T

= 470 pF

T

= 560 pF

T

= 680 pF

T

Oscillator and Duty Cycle Limit

The switching frequency is set by RT and CT connected to

the R

pin. CT charges and discharges between 3.0 V and

TCT

1.5 V.
The maximum duty cycle is set by the ratio of the on time,

tON, and the whole period, T = tON + t

. Because the

OFF

timing capacitor’s discharge current is trimmed, the
maximum duty cycle is well defined. It is determined by the
ratio between the timing resistor R

and the timing capacitor

T

CT. Refer to figures 6 and 7 to select appropriate values for
RT and CT.

1



1

;TSW tCH t

T

SW

6

2

Capacitor Values

7

3

RT (kΩ)

8

4

DIS

1. CT = 47 pF

2. C

= 100 pF

T

= 150 pF

3. C

T

4. C

= 220 pF

T

5. C

= 390 pF

T

6. C

= 470 pF

T

7. C

= 560 pF

T

8. C

= 680 pF

T

100

90

5

80

70

60

Duty Cycle (%)

50

40

Figure 7. Duty Cycle vs. RT for Discrete

f

SW

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9

CS51021A, CS51022A, CS51023A, CS51024A

PACKAGE DIMENSIONS

SO–16

D SUFFIX

CASE 751B–05

ISSUE J

–T–

–A–

16 9

–B–

18

G

K

C

SEATING

PLANE

D

16 PL

0.25 (0.010) A

M

S

B

T

S

PACKAGE THERMAL DATA

Parameter

R

Θ

JC

R

Θ

JA

8 PLP

M

0.25 (0.010) B

M

S

X 45

R



F

J

SO–16 Unit

Typical 28 °C/W
Typical 115 °C/W

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

DIM MIN MAX MIN MAX

A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7



P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019

INCHESMILLIMETERS

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10

Notes

CS51021A, CS51022A, CS51023A, CS51024A

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11

CS51021A, CS51022A, CS51023A, CS51024A

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CS51021A/D

12