ON Semiconductor CS1112 Technical data

查询CS1112供应商

CS1112

Quad Power Output Driver

The CS1112 is a Power Output Driver. The IC incorporates four protected DMOS low–side drivers designed to drive inductive and resistive loads in an automotive environment. The outputs are controlled by an 8–bit serial peripheral interface (SPI) or its associated parallel input. Each output contains overcurrent protection, open load detection, and inductive flyback clamps. The device is overvoltage protected. Overcurrent and open load faults are reported over the SPI port, and at the STATUS lead.

I/O Control

SPI communication is initiated by asserting CSB low. Data at the SI lead is transferred on the rising edge of SCLK. The MSB is transferred first. The outputs become active at the rising edge of CSB. Diagnostic status bits are transferred out the SO lead at the falling edge of SCLK. The SO lead is high impedance while CSB is high. An open drain output, (STATUS) reports a fault (short to V has occurred at one or more of the outputs.

Protection

Each output independently detects shorts to V is “on” and open load/short to ground while the output is “off”. The fault register will be set if a fault occurs at the output. The fault register will be reset if the fault condition is removed from the output. The fault data is latched when CSB is asserted low.

If an overcurrent condition or short circuit to V output goes into a low duty cycle mode for the duration of the fault. The outputs are disabled during an overvoltage or undervoltage condition.

Features

• 4.0 MHz Serial Input Bus

• Parallel Input Control

• 1.0 Ω DMOS Drivers (typ)

• Power On Reset

• Internal Flyback Clamps

• Status Output

• Fault Protection

– 46 V Peak Transient – Power Limiting – Undervoltage – Overvoltage

• Fault Reporting

– Open Load – Short Circuit

• 8 Internally Fused Leads

, GND, or open load)

PWR

while the output

PWR

occurs, the

BATT

http://onsemi.com

SO–24L DW SUFFIX CASE 751E

PIN CONNECTIONS AND

MARKING DIAGRAM

PWR

OUT0

IN0 GND GND

GND GND

IN1

OUT1

CSB

A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week

ORDERING INFORMATION

Device Package Shipping

CS1112YDWF24 CS1112YDWFR24

AWLYYWW

CS1112

SO–24L SO–24L

OSC

STATUS OUT3 IN3

GND GND GND GND

IN2

OUT2 SO SCLK

31 Units/Rail

1000 Tape & Reel

 Semiconductor Components Industries, LLC, 2000

October, 2000 – Rev. 10

1 Publication Order Number:

CS1112/D

CS1112

APPLICATION DIAGRAM

Micro Controller

with Bus

CSB

SCLK

OSC

IN1 IN2 IN3 IN4 V

Registers and

CMOS

Serial Shift

Latches

Bias

QPOD

PWR

DMOS

Low Side

Switches and

Protection

Circuitry

Fault

Reporting

Status

10 kΩ

OSC

82 kΩ

GND

ABSOLUTE MAXIMUM RATINGS*

Rating Value Unit

DC Supply (V Output DC Voltage (Out 0, 1, 2, 3) 46 V VDD Supply Voltage –0.3 to +7.0 V Peak Transient (1.0 ms rise time, 300 ms period, 32 V Load Dump @ 14 V V Digital Input Voltage –0.3 to VDD + 0.3 V Single Pulse Avalanche Energy (I = 450 mA)(Out 0, 1, 2, 3) 50 mJ Operating Junction Temperature, T ESD Capability (Human Body Model) 1.5 kV Lead Temperature Soldering: Reflow: (SMD styles only) (Note 1.) 230 peak °C

1. 60 second maximum above 183°C. *The maximum package power dissipation must be observed.

) –0.3 to 30 V

PWR

) 46 V

PWR

–40 to 150 °C

http://onsemi.com

CS1112

ELECTRICAL CHARACTERISTICS (9.0 V < V

5.5

V < V

< 25 V, (Outputs Functional); unless otherwise specified.)

PWR

Characteristic

< 17 V, 4.5 V < VDD < 5.5 V, –40°C < T

PWR

Test Conditions Min Typ Max Unit

J <

125°C,

Supply Voltages and Currents

VDD Power On Reset Threshold Outputs Latched Off By Event 2.5 3.0 3.5 V VDD Power On Reset Hysteresis – – 200 – mV V

Undervoltage Outputs Latched Off By Event 4.0 4.5 5.0 V

PWR

Overvoltage Lockout Outputs Latched Off By Event 30 35 45 V

PWR

Digital Supply Current, I Analog Supply Current, I Sleep Current, I

V(PWR)

V(DD)

V(PWR)

All Outputs On (@ 350 mA) – – 5.0 mA All Outputs On (@ 350 mA) – – 5.0 mA VDD ≤ 0.5 V – – 10 µA

Digital Inputs and Outputs

VIN High SI, SCLK, CSB, IN0, IN1, IN2, IN3 70 – – %V VIN Low SI, SCLK, CSB, IN0, IN1, IN2, IN3 – – 30 %V VIN Hysteresis – – 230 – mV Input Pulldown Current SI, IN0, IN1, IN2, IN3, VIN = 30% V Input Pullup Current CSB, VIN = 70% V Status Low I

= 0.5 mA – 0.1 0.5 V

STATUS

– – 25 µA – – –25 µA

Fault Detection/Timing

Overcurrent Sense Time, t

Overcurrent Shutdown Time Overcurrent Shutdown Time, R

Overcurrent Sense Time, R

= 82 kΩ 25 62.5 100 µs

OSC

= 82 kΩ 1.60 3.94 6.3

OSC

Fault Duty Cycle After the first fault cycle, Note 1. 1.4 1.56 1.7 % Open Load Trip Point IN = Low 40 50 60 %V Open Load Sense Time Open Load Sense Time, R

= 82 kΩ 12.5 – 100 µs

OSC

Power Outputs

Clamp ID = 20 mA, t

DRAIN

Drain Leakage Current V Drain Leakage Current V R

DS(ON)

= 17 V – – 25 µA

DRAIN

= 46 V – – 400 µA

DRAIN

= 13 V, ID = 0.5 A – 1.0 2.0 Ω

PWR

= 100 µs 48 52 64 V

CLAMP

Current Limit Note 2. 3.0 4.5 6.0 A Reverse Diode Drop Reverse Diode Drop I = 350 mA – – 1.4 V Fall Time Delay, t

phl

PWR

= 13 V, R

LOAD

= 33 Ω,

– – 10 µs

Note 3. (see Figure 2)

Rise Time Delay, t

plh

PWR

= 13 V, R

LOAD

= 33 Ω,

– – 15 µs

Note 3. (see Figure 2) Rise Time, t Fall Time, t

V V

PWR

= 13 V, R = 13 V, R

= 33 Ω 0.4 – 10 µs

LOAD

= 33 Ω 0.4 – 10 µs

LOAD

1. Guaranteed by design.

2. A duty cycle mode will initiate at a minimum of 1.0 A and before the current limit.

3. Output turn on delay and turn off delay from rising edge of CSB to the output reaching 50% of V

PWR

http://onsemi.com

CS1112

ELECTRICAL CHARACTERISTICS (continued) (9.0 V < V

5.5

V < V

< 25 V, (Outputs Functional); unless otherwise specified.)

PWR

< 17 V, 4.5 V < VDD < 5.5 V, –40°C < T

PWR

J <

125°C,

Characteristic UnitMaxTypMinTest Conditions

Serial Peripheral Interface V

PWR

= 14 V SCLK Clock Period CO = 200 pF 250 – – ns MAX Input Capacitance SI, SCLK, Note 1. – – 12 pF V

High SO, IOH = 1.0 mA VDD – 1.0 – – V

OUT

Low SO, IOL = 1.0 mA – – 0.5 V

OUT

SCLK High Time F

= 4.0 MHz, SCLK = 2.0 V to 2.0 V

SCLK

125 – – ns

(see Figure 1)

SCLK Low Time F

= 4.0 MHz, SCLK = 0.8 V to 0.8 V

SCLK

125 – – ns

(see Figure 1)

SI Setup Time SI = 0.8 V/2.0 V to SCLK = 2.0 V at 4.0 MHz;

25 – – ns

Note 1. (see Figure 1)

SI Hold Time SCLK = 2.0 V to SI = 0.8 V/2 .0 V at 4.0 MHz;

25 – – ns

Note 1. (see Figure 1)

SO Rise Time CLD = 200 pF (0.1 VDD to 0.9 VDD);

– 25 50 ns

Note 1.

SO Fall Time CLD = 200 pF (0.9 VDD to 0.1 VDD);

– – 50 ns

Note 1.

CSB Setup Time CSB = 0.8 V to SCLK = 2.0 V

60 – – ns

(see Figure 1) Note 1.

CSB Hold Time SCLK = 0.8 V to CSB = 2.0 V

75 – – ns

(see Figure 1) Note 1.

SO Delay Time SCLK = 0.8 V to SO Data Valid, VDD = 5.0 V

= 200 pF at 4.0 MHz

– 65 125 ns

(see Figure 1); Note 1.

Xfer Delay Time CSB rising edge to next falling edge.

1.0 – – µs

Note 1.

1. Guaranteed by design.

PACKAGE PIN DESCRIPTION

PACKAGE PIN #

24 Lead SOIC

1 V 2 V 3 OUT0 Open drain output one. 4 IN0 Parallel input one.

5, 6, 7, 8

17, 18, 19, 20

9 IN1 Parallel input two. 10 OUT1 Open drain output two. 11 SI SPI serial input. 12 CSB SPI active low chip select. 13 SCLK SPI clock input. 14 SO SPI serial output.

PIN SYMBOL FUNCTION

PWR

Input voltage to bias logic and control circuitry. Input voltage to bias gate drive circuitry.

GND Ground Reference.

http://onsemi.com

+ 8 hidden pages