OmniVision OV2640 User Manual
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Advanced Information
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Preliminary Datasheet
OV2640 Color CMOS UXGA (2.0 MegaPixel) CAMERACHIP
General Description
The OV2640 CAMERACHIPTM is a low voltage CMOS image
sensor that provides the full functionality of a single-chip
UXGA (1632x1232) camera and image processor in a small
footprint package. The OV2640 provides full-frame,
sub-sampled, scaled or windowed 8-bit/10-bit images in a
wide range of formats, controlled through the Serial Camera
Control Bus (SCCB) interface.
This product has an image array capable of operating at up
to 15 frames per second (fps) in UXGA resolution with
complete user control over image quality, formatting and
output data transfer. All required image processing functions,
including exposure control, gamma, white balance, color
saturation, hue control, white pixel canceling, noise
canceling, and more, are also programmable through the
SCCB interface. The OV2640 also includes a compression
engine for increased processing power. In addition,
OmniVision C
to improve image quality by reducing or eliminating common
lighting/electrical sources of image contamination, such as
fixed pattern noise, smearing, etc., to produce a clean, fully
stable color image.
AMERACHIPS use proprietary sensor technology
Note: The OV2640 uses a lead-free
Pb
package.
Features
• High sensitivity for low-light operation
• Low operating voltage for embedded portable apps
• Standard SCCB interface
• Output support for Raw RGB, RGB (RGB565/555),
GRB422, YUV (422/420) and YCbCr (4:2:2) formats
• Supports image sizes: UXGA, SXGA, SVGA, and any
size scaling down from SXGA to 40x30
•VarioPixel
• Automatic image control functions including Automatic
Exposure Control (AEC), Automatic Gain Control
(AGC), Automatic White Balance (AWB), Automatic
Band Filter (ABF), and Automatic Black-Level
Calibration (ABLC)
• Image quality controls including color saturation,
gamma, sharpness (edge enhancement), lens
correction, white pixel canceling, noise canceling, and
50/60 Hz luminance detection
• Line optical black level output capability
• Video or snapshot operation
• Zooming, panning, and windowing functions
• Internal/external frame synchronization
• Variable frame rate control
• Supports LED and flash strobe mode
• Supports scaling
• Supports compression
• Embedded microcontroller
®
method for sub-sampling
Ordering Information
Product Package
OV02640-VL9A (Color, lead-free) 38-pin CSP2
TM
with OmniPixel2TM Technology
Applications
• Cellular and Camera Phones
•Toys
• PC Multimedia
• Digital Still Cameras
Key Specifications
Array Size UXGA 1600 x 1200
Power Supply
Power
Requirements
Temperature
Range
Output Formats (8-bit)
Maximum
Image
Transfer Rate
Maximum Exposure Interval 1247 x t
Package Dimensions 5725 µm x 6285 µm
Stable Image 0°C to 50°C
Chief Ray Angle 25° non-linear
UXGA/SXGA 15 fps
Dynamic Range 50 dB
Gamma Correction Programmable
Dark Current 15 mV/s at 60°C
Well Capacity 12 Ke
Fixed Pattern Noise <1% of V
Core 1.2VDC +
Analog 2.5 ~ 3.0VDC
I/O 1.7V to 3.3V
125 mW (for 15 fps, UXGA
YUV mode)
Active
140 mW (for 15 fps, UXGA
Standby 600 µA
Operation -30°C to 70°C
Lens Size 1/4"
Sensitivity 0.6 V/Lux-sec
S/N Ratio 40 dB
Scan Mode Progressive
Pixel Size 2.2 µm x 2.2 µm
Image Area 3590 µm x 2684 µm
compressed mode)
• YUV(422/420)/YCbCr422
• RGB565/555
• 8-bit compressed data
• 8-/10-bit Raw RGB data
SVGA 30 fps
CIF 60 fps
Figure 1 OV2640 Pin Diagram (Top View)
A2 A4A3A5 A6
A1
DOGND EXPST_B
B1
C1
E1
F1
G1
AGND SGND VREFN STROBE
B2 B4B3B5 B6
AVDD SVDD SVDD PWDNDOVDD FREX
C2 C4C3C5 C6
HREF XVCLK VREFH RESETBSIO_D SIO_C
D2 D6
OV2640
E2 E4E3E5 E6
PCLK EGND Y6 DGNDY1 Y0
F2 F4F3F5 F6
Y2 Y4 Y8 DVDDEVDD DVDD
G2 G4G3G5 G6
Y3 Y5 Y7 Y9EVDD DGND
5%
ROW
PEAK-TO-PEAK
NCVSYNC
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Functional Description
Figure 2 shows the functional block diagram of the OV2640 image sensor . The OV2640 includes:
• Image Sensor Array (1632 x 1232 total image array)
• Analog Signal Processor
• 10-Bit A/D Converters
• Digital Signal Processor (DSP)
• Output Formatter
• Compression Engine
• Microcontroller
• SCCB Interface
• Digital Video Port
Figure 2 Functional Block Diagram
Column Sample/Hold
Image Array
(1632 x 1232)
Row Select
AMP
Gain
Control
Timing Generator and Control LogicPLL
10-Bit
A/D
PWDNRESETBVSYNC STROBEPCLKHREFXVCLK
Channel
Balance
Balance
Control
Black Level
Compensation
Control
Register
Bank
SCCB Slave
Interface
SIO_C SIO_D
DSP Formatter
Compression
Engine
Microcontroller
Video
Port
Y[9:
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Functional Description
Image Sensor Array
The OV2640 sensor has an image array of 1632 columns
by 1232 rows (2,010,624 pixels). Figure 3 shows a
cross-section of the image sensor array.
Figure 3 Sensor Array Region Color Filter Layout
Column
01234
0
GB GB GB GB GB GB
1
RG RG RG RG RG RG
GB GB GB GB GB GB
2
RG RG RG RG RG RG
3
4
5
6
7
8
GB GB GB
9
RG RG RG
10
GB GB GB
11
RG RG RG
12
GB GB GB
13
RG RG RG
GB GB GB GB GB GB
206
RG RG RG RG RG RG
207
208
GB GB GB GB GB GB
5
1626
1627
GB GB GB
RG RG RG
GB GB GB
RG RG RG
GB GB GB
RG RG RG
1628
1629
1630
1631
Dummy
Dummy
Dummy
Dummy
Optical
Black
Dummy
Dummy
Dummy
Dummy
1220
Active
Lines
10-Bit A/D Converters
After the analog amplifier, the bayer pattern Raw signal is
fed to two 10-bit analog-to-digital (A/D) converters, one for
G channel and one shared by the BR channels. These
A/D converters operate at speeds up to 20 MHz and are
fully synchronous to the pixel rate (actual conversion rate
is related to the frame rate).
Channel Balance
The amplified signals are then balanced with a chann el
balance block. In this block, the Red/Blue channel gain is
increased or decreased to match Green channel
luminance level.
Balance Control
Channel Balance can be done manually by the user or by
the internal automatic white balance (AWB) controller.
Black Level Compensation
231
RG RG RG RG RG RG
After the pixel data has been digitized, black level
calibration can be applied before the data is o utput. The
The color filters are arranged in a Bayer pattern. The
primary color BG/GR array is arranged in line-alternating
fashion. Of the 2,010,624 pixels, 1,991,040 (1632x1220)
are active. The other pixels are used for black level
black level calibration block subtracts the average signal
level of optical black pixels to compensate for the dark
current in the pixel output. The user can disable black
level calibration.
calibration and interpolation.
The sensor array design is based on a field integration
read-out system with line-by-line transfer and an
electronic shutter with a synchronous pixel read-out
scheme.
Windowing
The OV2640 allows the user to define window size or
region of interest (ROI), as required by the application.
Window size setting (in pixels) ranges from 2 x 4 to
1632 x1220 (UXGA) or 2 x 2 to 818 x 610 (SVGA), and
Analog Amplifier
408 x 304 (CIF), and can be anywhere inside the
1632 x1220 boundary. Note that modifying window size
When the column sample/hold circuit has sampled one
row of pixels, the pixel data will shift out one-by-one into
an analog amplifier.
Gain Control
or window position does not alter the frame or pixel rate.
The windowing control merely alters the assertion of the
HREF signal to be consistent with the programmed
horizontal and vertical ROI. The default window size is
1600 x 1200. Refer to Figure 4 and registers HREFST,
HREFEND, REG32, VSTRT, VEND, and COM1 for
details.
The amplifier gain can either be programmed by the user
or controlled by the internal automatic gain control circuit
(AGC).
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Figure 4 Windowing
ow Start
Row End
Column
Start
HREF
Column
R
o
w
Display
HREF
Window
Column
End
Sensor Array
Boundary
Zooming and Panning Mode
The OV2640 provides zooming and panning modes. The
user can select this mode under SVGA/CIF mode timing.
The related zoom ratios will be 2:1 of UXGA for SVGA and
4:1 of UXGA for CIF. Registers ZOOMS[7:0] (0x49) and
COM19[1:0] (0x48) define the vertical line start point.
Register ARCOM2[2] (0x34) defines the horizontal start
point.
Sub-sampling Mode
The OV2640 supports two sub-sampling modes. Each
sub-sampling mode has different resolution and maximum
frame rate. These modes are described in the following
sections.
CIF Mode
The OV2640 can also operate at a higher frame rate to
output 400 x 296 sized images. Figure 6 shows the
sub-sampling diagram in both horizontal and vertical
directions for CIF mode.
Figure 6 CIF Sub-Sampling Mode
Column
i
i+1
i+2
i+3
i+4
i+5
ow
n
B
n+1
n+2
n+3
n+4
n+5
G G G
n+6
n+7
n+8
B B B
n+9
n+10
n+11
n+12
n+13
G G G
n+14
n+15
n+16
B B B
n+17
n+18
n+19
n+20
n+21
G G G
n+22
n+23
Skipped Pixels
i+6
G G G
R R R
G G G
R R R
G G G
R R R
i+10
i+9
i+7
i+8
i+11
i+12
B B
i+13
i+14
i+15
i+16
i+17
i+18
i+19
Timing Generator and Control Logic
i+20
i+21
i+22
i+23
SVGA mode
The OV2640 can be programmed to output 800 x 600
(SVGA) sized images for applications where higher
resolution image capture is not required. In this mode,
In general, the timing generator controls the following:
• Frame Exposure Mode Timing
• Frame Rate Adjust
• Frame Rate Timing
both horizontal and vertical pixels will be sub-sampled
with an aspect ratio of 4:2 as shown in Figure 5.
Frame Exposure Mode Timing
Figure 5 SVGA Sub-Sampling Mode
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Column
i
i+1
i+3
i+4
i+2
n
ow
BBB
GGG
n+1
GGG
RRR
n+2
n+3
n+4
BBB
GGG
n+5
GGGRRR
n+6
n+7
Skipped Pixels
i+7
i+5
i+6
i+8
i+9
The OV2640 supports frame exposure mode. Typically,
the frame exposure mode must work with the aid of an
external shutter.
The frame exposure pin, FREX (pin B2), is the frame
exposure mode enable pin and the EXPST_B pin (pin A2)
serves as the sensor's exposure start trigger. When the
external master device asserts the FREX pin high, the
sensor array is quickly pre-charged and stays in reset
mode until the EXPST_B pin goes low (sensor exposure
time can be defined as the period between EXPST_B low
and shutter close). After the FREX pin is pulled low, the
video data stream is then clocked to the output port in a
line-by-line manner. After completing one frame of data
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Functional Description
output, the OV2640 will output continuous live video data
unless in single frame transfer mode. Figure 18 and
Figure 19 show the detailed timing and Table 11 shows
the timing specifications for this mode.
Frame Rate Adjust
The OV2640 offers three methods for frame rate
adjustment:
• Clock prescaler: (see “CLKRC” on page 23)
By changing the system clock divide ratio and PLL,
the frame rate and pixel rate will change together.
This method can be used for dividing the frame/pixel
rate by: 1/2, 1/3, 1/4 … 1/64 of the input clock rate.
• Line adjustment: (see “REG2A” on page 26 and
“FRARL” on page 26)
By adding a dummy pixel timing in each line
(between HSYNC and pixel data out), the frame rate
can be changed while leaving the pixel rate as is.
• Vertical sync adjustment:
By adding dummy line periods to the vertical sync
period (see “ADDVSL” on page 26 and “ADDVSH”
on page 26 or see “FLL” on page 27 and “FLH” on
page 27), the frame rate can be altered while the
pixel rate remains the same.
Frame Rate Timing
Default frame timing is illustrated in Figure 15, Figure 16,
and Figure 17. Refer to Table 1 for the actual pixel rate at
different frame rates.
Output Formatter
This block controls all output and data formatting required
prior to sending the image out.
Scaling Image Output
The OV2640 is capable of scaling down the image size
from CIF to 40x30. By using SCCB registers, the user can
output the desired image size. At certain image sizes,
HREF is not consistent in a frame.
Compression Engine
As shown in Figure 7, the Compression Engine consists
of three major blocks:
• DCT
•QZ
• Entropy Encoder
Figure 7 Compression Engine Block Diagram
Compression Engine
DCT QZ Entropy Encoder
Scale Factor
Q-Table H-Table Marker
Compressed
Stream
Table 1 Frame/Pixel Rates in UXGA Mode
Frame Rate (fps) 15 7.5 2.5 1.25
PCLK (MHz) 36 18 6 3
Microcontroller
The OV2640 embeds an 8-bit microcontroller with
512-byte data memory and 4 KB program memory. It
provides the flexibility of decoding protocol commands
from the host for controlling the system, as well as the
ability to fine tune image quality.
Digital Signal Processor (DSP)
This block controls the interpolation from Raw data to
RGB and some image quality control.
• Edge enhancement (a two-dimensional high pass
filter)
• Color space converter (can change Raw data to RGB
or YUV/YCbCr)
• RGB matrix to eliminate color cross talk
• Hue and saturation control
• Programmable gamma control
• Transfer 10-bit data to 8-bit
• White pixel canceling
• De-noise
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SCCB Interface
The Serial Camera Control Bus (SCCB) interface controls
the CAMERACHIP operation. Refer to OmniVision
Technologies Serial Camera Control Bus (SCCB)
Specification for detailed usage of the serial control port.
Slave Operation Mode
The OV2640 can be programmed to operate in slave
mode (default is master mode).
When used as a slave device, COM7[3] (0x12), CLKRC[6]
(0x11), and COM2[2] (0x09) register bits should be set to
OV2640 Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP™
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"1" and the OV2640 will use PWDN and RESETB pins as
vertical and horizontal synchronization triggers supplied
by a master device. The master device must provide the
following signals:
1. System clock MCLK to XVCLK pin
2. Horizontal sync MHSYNC to RESETB pin
3. Vertical frame sync MVSYNC to PWDN pin
See Figure 8 for slave mode connections and Figure 9 for
detailed timing considerations.
Figure 8 Slave Mode Connection
Y[9:0]
RESETB
PWDN
XVCLK
OV2640
MHSYNC
MVSYNC
MCLK
Master
Device
Figure 9 Slave Mode Timing
T
VSYNC
HSYNC
MCLK
NOTE:
1) T
HS
2) T
line
T
line
3) T
frame
T
frame
> 6 T
, Tvs > T
clk
= 1922 x T
= 595 x T
= 1248 x T
= 336 x T
T
VS
(UXGA); T
clk
(CIF)
clk
line
line
line
(UXGA); T
(CIF)
T
line
T
clk
frame
= 1190 x T
line
frame
clk
= 672 x T
T
HS
(SVGA);
(SVGA);
line
Power Down Mode
Two methods are available to place the OV2640 into
power-down mode: hardware power-down and SCCB
software power-down.
To initiate hardware power-down, the PWDN pin (pin B6)
must be tied to high. When this occurs, the OV2640
internal device clock is halted and all internal counters are
reset. The current draw is less than 15 µA in this standby
mode.
Executing a software power-down through the SCCB
interface suspends internal circuit activity but does not
halt the device clock. The current requirements drop to
less than 1 mA in this mode. All register content is
maintained in standby mode.
Digital Video Port
MSB/LSB Swap
The OV2640 has a 10-bit digital video port. The MSB and
LSB can be swapped with the control registers. Figure 10
shows some examples of connections with external
devices.
Figure 10 Connection Examples
MSB Y9
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
LSB Y0
OV2640
Default 10-bit Connection Swap 10-bit Connection
Y9
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
External
Device
LSB Y9
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
MSB Y0
OV2640 Externa
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Device
Strobe Mode
The OV2640 has a Strobe mode that allows it to work with
an external flash and LED.
Reset
The OV2640 includes a RESETB pin (pin C6) that forces
a complete hardware reset when it is pulled low (GND).
The OV2640 clears all registers and resets them to their
default values when a hardware reset occurs. A reset can
also be initiated through the SCCB interface.
MSB Y9
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
LSB Y0
OV2640
Default 8-bit Connection Swap 8-bit Connection
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
External
Device
LSB Y9
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
MSB Y0
OV2640 Externa
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Device
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Functional Description
Line/Pixel Timing
The OV2640 digital video port can be programmed to
work in either master or slave mode.
In both master and slave modes, pixel data output is
synchronous with PCLK (or MCLK if port is a slave),
HREF, and VSYNC. The default PCLK edge for valid data
is the negative edge but may be programmed using
register COM10[4] for the positive edge. Basic line/pixel
output timing and pixel timing specifications are shown in
Figure 14 and Table10.
Also, using register COM10[5], PCLK output can be gated
by the active video period defined by the HREF signal.
See Figure 11 for details.
Figure 11 PCLK Output Only at Valid Pixels
CLK
CLK active edge negative
REF
CLK
CLK active edge positive
SYNC
The specifications shown in Table 10 apply for
DVDD = +1.2 V, DOVDD = +2.8 V, T
working at 15 fps, external loading = 20 pF .
= 25°C, sensor
A
Pixel Output Pattern
Table 2 shows the output data order from the OV2640.
The data output sequence following the first HREF and
after VSYNC is: B
0,0 G0,1 B0,2 G0,3
After the second HREF the output is G
G
1,1598 R1,1599
…, etc. If the OV2640 is programmed to
… B
0,1598 G0,1599
1,0 R1,1 G1,2 R1,3
output SVGA resolution data, horizontal and vertical
sub-sampling will occur. The default output sequence for
the first line of output will be: B
G
. The second line of output will be: G
0,1597
R
1,5
… G
1,1596 R1,1597
.
0,0 G0,1 B0,4 G0,5
… B
0,1596
1,0 R1,1 G1,4
Table 2 Data Pattern
R/C 0 1 2 3 . . . 1598 1599
0 B
1 G
2 B
3 G
.
.
1198 B
1199 G
G
B
0,0
0,1
R
1,0
1,1
G
2,0
2,1
R
3,0
3,1
1198,0G1198,1B1198,2G1198,3
1199,0R1199,1G1199,2R1199,3
G
0,2
0,3
G
R
1,2
1,3
B
G
2,2
2,3
G
R
3,2
3,3
. . . B
0,1598
. . . G
1,1598
. . . B
2,1598
. . . G
3,1598
.
.
. . . B
1198,1598G1198,1599
. . . G
1199,1598R1199,1599
G
R
G
R
0,1599
1,1599
2,1599
3,1599
.
…
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Pin Description
Table 3 Pin Description
Pin Location Name Pin Type Function/Description
A1 DOGND Ground Ground for digital video port
Snapshot Exposure Start Trigger
A2 EXPST_B Input
A3 AGND Ground Ground for analog circuit
A4 SGND Ground Ground for sensor array
A5 VREFN Reference Internal analog reference - connect to ground using a 0.1 µF capacitor
A6 STROBE I/O
B1 DOVDD Power Power for digital video port
0: Sensor starts exposure (only effective in snapshot mode)
1: Sensor stays in reset mode
Note: There is no internal pull-up/pull-down resistor.
Flash control output
Default: Input
Note: There is no internal pull-up/pull-down resistor.
B2 FREX Input
B3 AVDD Power Power for analo g circuit
B4 SVDD Power Power for sensor array
B5 SVDD Power Power for sensor array
B6 PWDN Input
C1 SIO_D I/O SCCB serial interface data I/O
C2 SIO_C Input
C3 HREF I/O
C4 XVCLK Input
C5 VREFH Reference Internal analog reference - connect to ground using a 0.1 µF capacitor
C6 RESETB Input
D2 VSYNC I/O
Snapshot trigger - use to activate a snapshot sequence
Note: There is no internal pull-up/pull-down resistor.
Power-down mode enable, active high
Note: There is an internal pull-down resistor.
SCCB serial interface clock input
Note: There is no internal pull-up/pull-down resistor.
Horizontal reference output
Default: Input
Note: There is no internal pull-up/pull-down resistor.
System clock input
Note: There is no internal pull-up/pull-down resistor.
Reset mode, active low
Note: There is an internal pull-up resistor.
Vertical synchronization output
Default: Input
Note: There is no internal pull-up/pull-down resistor.
D6 NC – No connection
Video port output bit[1]
E1 Y1 I/O
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Default: Input
Note: There is no internal pull-up/pull-down resistor.
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Table 3 Pin Description
Pin Location Name Pin Type Function/Description
Video port output bit[0]
E2 Y0 I/O
E3 PCLK I/O
E4 EGND Ground Ground for internal regulator
E5 Y6 I/O
E6 DGND Ground Ground for digital core
F1 EVDD Power Power for internal regulator
F2 DVDD Power Sensor digital power (Core)
F3 Y2 I/O
Default: Input
Note: There is no internal pull-up/pull-down resistor.
Pixel clock output
Default: Input
Note: There is no internal pull-up/pull-down resistor.
Video port output bit[6]
Default: Input
Note: There is no internal pull-up/pull-down resistor.
Video port output bit[2]
Default: Input
Note: There is no internal pull-up/pull-down resistor.
Pin Description
Video port output bit[4]
F4 Y4 I/O
F5 Y8 I/O
F6 DVDD Power Sensor digital power (Core)
G1 EVDD Power Power for internal regulator
G2 DGND Ground Ground for digital core
G3 Y3 I/O
G4 Y5 I/O
G5 Y7 I/O
G6 Y9 I/O
Default: Input
Note: There is no internal pull-up/pull-down resistor.
Video port output bit[8]
Default: Input
Note: There is no internal pull-up/pull-down resistor.
Video port output bit[3]
Default: Input
Note: There is no internal pull-up/pull-down resistor.
Video port output bit[5]
Default: Input
Note: There is no internal pull-up/pull-down resistor.
Video port output bit[7]
Default: Input
Note: There is no internal pull-up/pull-down resistor.
Video port output bit[9]
Default: Input
Note: There is no internal pull-up/pull-down resistor.
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Figure 12 Pinout Diagram
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Table 4 Ball Matrix
A1
DOGND EXPST_B
B1
C1
E1
F1
G1
A2 A4
B2 B4
C2 C4
D2 D6
E2 E4
F2 F4
G2 G4
A3
AGND SGND VREFN STROBE
B3
AVDD SVDD SVDD PWDNDOVDD FREX
C3
HREF XVCLK VREFH RESETBSIO_D SIO_C
A5 A6
B5 B6
C5 C6
OV2640
NCVSYNC
E3
PCLK EGND Y6 DGNDY1 Y0
F3
Y2 Y4 Y8 DVDDEVDD DVDD
G3
Y3 Y5 Y7 Y9EVDD DGND
E5 E6
F5 F6
G5 G6
1 2 3 4 5 6
A DOGND EXPST_B AGND SGND VREFN STROBE
B DOVDD FREX AVDD SVDD SVDD PWDN
C SIO_D SIO_C HREF XVCLK VREFN RESETB
D
E Y1 Y0 PCLK EGND Y6 DGND
F EVDD DVDD Y2 Y4 Y8 DVDD
G EVDD DGND Y3 75 Y7 Y9
VSYNC NC
10 Proprietary to OmniVision Technologies Version 1.6, February 28, 2006
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Electrical Characteristics
Electrical Characteristics
Table 5 Absolute Maximum Ratings
Ambient Storage Temperature -40ºC to +95ºC
V
DD-A
Supply Voltages (with respect to Ground)
V
DD-C
V
DD-IO
All Input/Output Voltages (with respect to Ground) -0.3V to V
4.5V
3V
4.5V
DD-IO
+1V
Lead-free Temperature, Surface-mount process 245ºC
ESD Rating, Human Body model 2000V
NOTE: Exceeding the Absolute Maximum ratings shown above invalidates all AC and DC electrical specifications and may
result in permanent device damage.
Table 6 DC Characteristics (-30°C < TA < 70°C)
Symbol Parameter Min Typ Max Unit
Supply
V
DD-A
V
DD-D
V
DD-IO
I
DDA-A
I
DDA-D
I
DDA-IO
I
DDS-SCCB
I
DDS-PWDN
Digital Inputs
Supply voltage 2.5 2.8 3.0 V
Supply voltage 1.14 1.2 1.26 V
Supply voltage
Active (Operating) Current
Active (Operating) Current
Active (Operating) Current
Standby Current
a
b
b
b
b
1.71 2.8 3.3 V
30 40 mA
25 (YUV)
35 (Compressed)
35 (YUV)
50 (Compressed)
mA
610mA
12mA
600 1200 µA
V
IL
V
IH
C
IN
Input voltage LOW 0.54 V
Input voltage HIGH 1.26 V
Input capacitor 10 p F
Digital Outputs (standard loading 25 pF)
V
OH
V
OL
Output voltage HIGH 1.62 V
Output voltage LOW 0.18 V
Serial Interface Inputs
V
IL
V
IH
a. 1.8V I/O is supported. Contact your local OmniVision FAE for further details.
b. V
DD-A
I
DDS-SCCB
SIO_C and SIO_D -0.5 0 0.54 V
SIO_C and SIO_D 1.26 1.8 2.3 V
= 2.8V, V
refers to SCCB-initiated Standby, while I
= 1.2V, and V
DD-D
= 1.8V for 15 fps in UXGA mode
DD-IO
DDS-PWDN
refers to PWDN pad-initiated Standby
Version 1.6, February 28, 2006 Proprietary to OmniVision Technologies 11
OV2640 Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CAMERACHIP™
mni ision
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Table 7 AC Characteristics (TA = 25°C, V
DD-A
= 2.8V)
Symbol Parameter Min Typ Max Unit
ADC Parameters
B Analog bandwidth 20 MHz
DLE DC differential linearity error 0.5 LSB
ILE DC integral linearity error 1 LSB
Settling time for hardware reset <1 ms
Settling time for software reset <1 ms
Settling time for UXGA/SVGA mode change <1 ms
Settling time for register setting <300 ms
Table 8 Timing Characteristics
Symbol Parameter Min Typ Max Unit
Oscillator and Clock Input
f
OSC
t
r
, t
f
Frequency (XVCLK) 6 24 MHz
Clock input rise/fall time 5 ns
Clock input duty cycle 45 50 55 %
12 Proprietary to OmniVision Technologies Version 1.6, February 28, 2006
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Timing Specifications
Timing Specifications
Figure 13 SCCB Interface Timing Diagram
SIOC
SIOD IN
IOD OUT
t
SU:STA
t
F
t
LOW
t
HD:STA
t
HIGH
t
HD:DAT
t
AA
t
DH
t
SU:DAT
t
R
t
SU:STO
t
Table 9 SCCB InterfaceTiming Specifications
Symbol Parameter Min Typ Max Unit
f
SIO_C
t
LOW
t
HIGH
t
AA
Clock Frequency 400 KHz
Clock Low Period 1.3 µs
Clock High Period 600 ns
SIOC low to Data Out valid 100 900 ns
BUF
t
BUF
t
HD:STA
t
SU:STA
t
HD:DAT
t
SU:DAT
t
SU:STO
t
R, tF
t
DH
Bus free time before new START 1.3 µs
START condition Hold time 600 ns
START condition Setup time 600 ns
Data-in Hold time 0 µs
Data-in Setup time 100 ns
STOP condition Setup time 600 ns
SCCB Rise/Fall times 300 ns
Data-out Hold time 50 ns
Version 1.6, February 28, 2006 Proprietary to OmniVision Technologies 13
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