Omega DAQ-16 User Manual

(1*,1((5,1*,1&

DAQ-16

Data Acquisition Adapter

for 16-bit ISA compatible machines

Users Manual

INTERFACE CARDS FOR PERSONAL COMPUTERS

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OMEGA ENGINEERING, INC., warrants this unit to be free of defects in materials and workmanship fo r a period of 13

DAQ-16 Users Manual 2

months from the date of purchase. OMEGA warranty adds an additional one (1) month grace period to the normal one (1)
year product warranty

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DAQ-16 Users Manual 3

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DAQ-16 Users Manual 4

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Declaration of Conformity

DAQ-16 Users Manual 5

Manufacturer's Name: Omega Engineering Inc.

Manufacturer's Address: One Omega Drive

Stamford, CT 06907-0047

Application of Council Directive: 89/336/EEC

Standards to which
Conformity is Declared: * EN50081-2

(EN55022, EN60555-2, EN60555-3)

* EN50082-1
(IEC 801-2, IEC 801-3, & IEC 801-4)

Type of Equipment: Information Technology Equipment

Equipment Class: Light Industrial Equipment

Product Name: ISA Data Acquisition Card

Model Number : DAQ-16

Table of Contents

4.2 Programming the 8254 Counter/Timer

27

4.1.8 8254 Control Word/Status Register

27

4.1.7 Multi-Function Timer Register

27

4.1.6 Clock Rate Register (high word)

27

4.1.5 Clock Rate Register (low word)

27

4.1.4 DAC1 Register

27

4.1.3 DAC0 Register

27

4.1.2 Start of Conversion Register

25

4.1.1 Control Word Register

4.1 Register Description

4. Register Description and Programming

3. External Connections

22

2.8.1 External Interrupt

2.8 Interrupts

2.7 Direct Memory Access

2.6 Trigger Selection

19

2.5.2 External Clock

18

2.5.1 Internal Clock

2.5 Clock Selection

2.4 Base Address

2.3 Digital Input/Output

2.2 Digital to Analog Converters

2.1 Analog to Digital Converter

2. Circuit Board Description and Configuration

1.2 DAQ-16 Specifications

1.1 Installation

1. Introduction

DAQ-16 Users Manual 6

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8
8
9

10
10
14
15
16
17

20
21
22

23

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25
25

28

List of Figures and Tables

25

Table 4-1. DAQ-16 Address Map

15

Table 2-3. Jumper J4 Configuration

13

Table 2-2. A/D Conversion Format Examples

10

Table 2-1. A/D Converter Configurations

23

Figure 3-1. 62 Pin Connector Diagram

22

Figure 2-11. Jumpers J10 and J11 Configuration

21

Figure 2-10. Jumpers J8 and J9 Configuration

20

Figure 2-9. Jumper J1 Configuration

20

Figure 2-8. Pre-Divider External Clock Pulses

19

Figure 2-7. Sampling Rate External Clock Pulses

17

Figure 2-6. Jumper J2 Configuration

16

Figure 2-5. I/O Base Address Selection

14

Figure 2-4. Jumper J3 Configuration

12

Figure 2-3. Jumper J5 Configuration

11

Figure 2-2. Jumper J6 Configuration

11

Figure 2-1. Jumper J7 Configuration

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DAQ-16 Users Manual 7

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1. Introduction

The DAQ-16 is a high speed data acquisition adapter for IBM AT compatible machines

DAQ-16 Users Manual 8

offering eight differential analog input channels with 16-bit resolution, two analog output
channels with 12-bit resolution and four digital input/output lines. Other features of the
DAQ-16 include:

Analog to Digital Converter



100 KHz maximum sampling rate



Bipolar input ranges of ±2.5, ±5, and ±10 volts



Unipolar input ranges of 0 to +2.5, 0 to +5 and 0 to +10 volts



Selectable gain of 1, 10, and 100



Two DMA channels for continuous acquisition



Internal or external clock and trigger

Digital to Analog Converters



Two independent analog output channels



Output ranges of 0 to +5 volts and ±5 volts



Internal or external voltage reference

Other Features



Interrupt on one of four sources including an external interrupt input



High density D-62 connector for reduced noise

1.1 Installation

1. Configure the DAQ-16 utilizing the instructions in Chapter 2: Circuit Board
Description and Configuration.

2. Ensure that power is not applied to the computer system.

3. Remove the cover according to the instructions provided by the system
manufacturer.

4. Insert the DAC-16 into any vacant ISA expansion slot. The board is secured to the
slot by installing the Option Retaining Bracket (ORB) screw.

5. Replace the system cover per manufacturer instructions.

1.2 DAQ-16 Specifications

DACK 5, 6, 7

DRQ 5, 6, 7

DMA Levels:

IRQ 2, 3, 4. 5, 6, 7, 10, 11, 12, 14, 15

Interrupt Levels:

0000H - FFFFH

I/O Address Range:

ISA 16-bit

Bus Interface:

491.4mA

374.9 mA

+12 volts

---

---

-12 volts

1204.9mA

1069.0 mA

+5 volts

---

---

-5 volts

I(ms)

I(t)

Power Supply

Power Requirements:

DAQ-16 Users Manual 9

I(t) = Typical Current / I(ms) = Maximum Statisical Current

2. Circuit Board Description and Configuration

The base address of the DAQ-16 is selected using switches SW1 and SW2. The operating

2-3, 4-5

2.5 v

1-3

100

+0.025/±0.025

1-2, 4-5

5 v

1-3

100

+0.05/±0.05

2-3, 5-6

10 v

1-3

100

+0.1/±.1

2-3, 4-5

2.5v

2-410+0.25/±0.25

1-2, 4-5

5 v

2-410+0.5/±0.5

2-3, 5-6

10 v

2-4

10

+1/±1

2-3, 4-5

2.5 v

3-41+2.5/±2.5

1-2, 4-5

5 v

3-4

1

+5/±5

2-3, 5-6*

10 v

3-4*1+10/±10

---

---

---

---

Unipolar / Bipolar

A/D Range

Amplifier

Maximum Input Voltage

DAQ-16 Users Manual 10

mode of the DAQ-16 is controlled by jumpers J1 through J7, while DMA and interrupt
selections are set with jumpers J 8 through J11. Connecti ons to external equi pment are made
through the high density 62-pin connector CN1.

2.1 Analog to Digital Converter

The analog to dig ital (A/D ) section of the DAQ- 16 accepts up to 8 diff erenti al i nputs from the
D-62 connector. These inputs pass through a dual 8-to-1 multipl exer circuit whi ch selects the
channel to be converted. The selected input is then amplified and presented to the A/D
converter to be d igitized . The digi tal output of the A/D i s latched into a buf fer to be rea d by
the computer. T he multiplexer circuit selects one of the 8 diff erential channels to be input to
the A/D converter. The channel is software selected through the DAQ-16's control word
register. The typical characteristics of the multiplexer circuit are:



input resistance: 1.5 Kohm



switching time: 0.5 us



settling time: 3.5 us

The amplifier stage of the A/D converter circuit performs two functions: (1) amplifies low
level input signals and (2) converts this input signal into a voltage range acceptable to the
A/D converter. The amplifier circuit is controlled by jumpers J6 and J7. Table 2-1 below
shows the recommended jumper setti ngs for vari ous input voltage range s, (* ind icates factory
settings).

J7

J6

Table 2-1. A/D Converter Configurations

Figures 2-1 and 2-2 show the configuration options for jumpers J7 and J6.

DAQ-16 Users Manual 11

J7

3

1

Gain = 1 Gain = 10 Gain = 100

J6

4 5 6

1 2 3

4
2

Figure 2-1. Jumper J7 Configuration

1

J7 J7

3

J6

4 5 6

1 2 3

4
2

3
1

4 5 6

1 2 3

4
2

J6

10 volt range

Figure 2-2. Jumper J6 Configuration

WARNING: These settings are only suggestions, it is the user's responsibility to guarantee

that the maximum input voltage multiplied by the gain setting selected by jumper J7 does

not exceed the A/D voltage range set by jumper J6.

5 vo lt range

2.5 volt range

The final stage of the A/D converter circuit is the A/D converter IC. The converter must be

configured for unipolar or bipolar input voltages and for binary or 2's complement data

DAQ-16 Users Manual 12

conversion. These options are selected using jumper J5 as shown in Figure 2-3 below.

J5

4 5 6

1 2 3

Unipolar

J5

4 5 6

1 2 3

Binary

J5

4 5 6

1 2 3

Bipolar

J5

4 5 6

1 2 3

2's complement

Figure 2-3. Jumper J5 Configuration

To simplify the following discussions, a new variable, Vmax, is introduced. Vmax is defined
as the maximum input voltage amplitude and is equal to the A/D range selected by jumper J6
divided by the amplifier gain defined by jumper J7. In equation form:

A/D range
Vmax = --------------­ amp. gain

When configured for unipolar operation, the input voltage may range from 0 volts (analog
ground) to Vmax volts as defined above. When configured for bipolar operation, the input
voltage may range from -Vmax volts to +Vmax volts.

The digital "code" generated for any specific voltage is dependent upon the operating mode:
unipolar or bipolar; and the data conversion format: binary or 2's complement. Binary
conversion will result in unsigned integers ranging from 0 to 65,535, while 2's complement
conversion will produce signed integers ranging from -32,768 to +32,767. Table 2-2 lists A/D
conversion format examples. Unipolar entries marked “n/a” are not applicable because the
voltage is outside of the unipolar voltage range.

+32,767

+32,767

+65,535

+65,535

+Vmax

+16,384

0

+49,152

+32,768

+Vmax/2

0

-32,768

+32,76800

-16,384

n/a

+16,384

n/a

-Vmax/2

-32,768

n/a

0

n/a

-Vmax

bipolar

unipolar

bipolar

unipolar

2’s Complement2’s ComplementBinaryBinaryVoltage

DAQ-16 Users Manual 13

Table 2-2. A/D Conversion Format Examples

In order to calcul ate the actual input voltag e from the digita l "code " provided by the DAQ-16 ,
the user must know the configuration used to acquire the data. Given this information, the
input voltage can be calculated using the equations below:

Unipolar, binary

input = * Vmax

Bipolar, binary

input = - * 2 * Vmax

Unipolar, 2’s complement

input = + * Vmax

Bipolar, 2’s complement

input = * 2 * Vmax

CODE

65,536

CODE

65,536

CODE

65,536

CODE

65,536

1
2

1
2

2.2 Digital to Analog Converters

The digital to analog (D/A) section of the DAQ-16 consists of two independent 12-bit

DAQ-16 Users Manual 14

multiplyi ng D/A converter s, and two i ndepende nt two-stage output ampli fiers. Digi tal data,
(output to the D/A converter by the CPU), is converted to an analog voltage by the D/A
converter, ampl ified b y the output amplifie rs and becomes output to the 62 pin connector at
CN1. T he D /A converter s use d on the DA Q-16 a re 12- bi t resol ution converte rs. Of the 16 bi ts
written to the D /A, only the 12 least sig nificant bits ( D0 - D11) are used f or the conversion.
The 4 most significant bits (D12 - D15) are ignored.

The DAQ-16 implements multiplying D/A converters which makes the analog output
proportional to a reference voltage applied to the D/A. Under normal circumstances, the
reference voltage should be applied from the internal +5V reference source. An external
reference vol tag e may also be suppl i e d to the D/A. This input fr om the D - 6 2 connector should
not exceed 5 volts and has a typical input impedance of 7.5Kohms. The D/A reference voltage
source is selected using jumper J3 as illustrated in Figure 2-4.

D/A channel 0 reference

Internal Source

4 5 6

External Source

J3

1 2 3

Internal Source

D/A channel 1 reference

Figure 2-4. Jumper J3 Configuration

The D/A conve rter channels may also b e operate d in unipol ar mod e: 0 to +5 volts, or bipolar
mode: -5 to +5 volts. The output mode is selected using jumper J4 as shown in Figure 2-5. In
addition, a gain selection jumper is provided to select an output gain of 1 or 2. When using
an external voltage reference, this gain can be used to amplify the D/A output for small
reference voltages.

External Source

WARNING: When the internal voltage reference is used, the D/A gain MUST be set to the

gain = 1 position.

J4

connect 4-8

connect 2-6

Gain = 1

connect 3-7

connect 1-5

Bipolar
Channel 1

Channel 0

DAQ-16 Users Manual 15

5 6 7 8

1 2 3 4

Channel 0 select

Channel 0 gain

Channel 1 gain

Channel 1 select

Figure 2-5. Jumper J4 Configuration

Table 2-3 lists configuration options for jumper J4.

Unipolar

Gain = 2

open 1-5

open 2-6

open 3-7

open 4-8

Table 2-3. Jumper J4 Configuration

When configured for unipolar operation, the output voltage can be calculated from the
equation:

A = V * * gain

out ref

CODE

4096

For bipolar operation, the equation becomes:

A = - 1 * V * gain

out

CODE

2048

ref

2.3 Digital Input/Output

The DAQ-16 offers four bits of digital output and four bits of digital input for
control/monitoring of external digital devices. The four digital output lines are LS TTL
compatible and will initialize low (0 volts) on power-up. The four digital inputs are also LS
TTL compatible. There is no termination provided on the digital input lines and a read of an
unused digital input will result in an indeterminate value.

2.4 Base Address

The DAQ-16 uses 16 consecutive I/O address locations in the range 0 to 0FFFFH. Two

DAQ-16 Users Manual 16

six-position switches (SW1 and SW2) are used to select the base address. SW1 controls
address lines A15 - A10, and SW2 controls A9 - A4. Address lines A3 - A0 are used
internally by the DAQ-16 to select which register to access.

When selecting a base address for the DAQ- 16, an address selection switch in the "OFF"
position corresponds to an address bit of "1" while a switch in the "ON" position corresponds
to an addre ss bit of "0". T he base add ress of the DAQ-16 must b e set on a 16 byte boundar y,
meaning A3 - A0 are "0". The address of the DAQ-16 as shipped from the factory is 0300H.
This setting and other examples are shown in the Figure 2-5.

xxxxx

x

123456

O
N

A A A A A A A A A A AA

15 14 13 12 11 10 9 8 7 6 5 4

SW1

xxxxxx

123456

O
N

SW2

03 00

00000 11 0000

0

123456

O
N

Example1: Base I/O Address = 0300H

6

11010 10 1110

0

123456

O
N

123456

O
N

A

123456

O
N

D

Example 2: Base I/O Address = 6AD0H

0000

Bit=0 Bit=1

0

xxxx Hex
0000 : 0

0001 : 1
0010 : 2
0011 : 3
0100 : 4
0101 : 5
0110 : 6
0111 : 7
1000 : 8

1001 : 9
1010 : A
1011 : B
1100 : C
1101 : D
1110 : E
1111 : F

Figure 2-5. I/O Base Address Selection

2.5 Clock Selection

The DAQ-16 i s equipped with a prog rammable clock circuit to produce data sampling r ates

DAQ-16 Users Manual 17

independent from the clock rate of the host computer. An onboard 8254 programmable
interval timer, with a 10 MHz clock input and either two or three cascaded 16-bit timers,
provides the sa mpl i n g r a te. This enabl e s the sampling rate to be adjusted from 1 0 us between
samples to almost a year between samples, in as small as 100ns increments.

The DAQ-16's sampling rate can al so b e generated from an external clock input. This external
clock can be connected directly to the A/D converter or through a 16-bit pre-divider, the
multi-function timer. Samples are taken on the low to high transition of the clock.

WARNING: For the DAQ-16, the maximum data sampling rate is 10 us. This restricts

clock frequency to a maximum of 100 KHz. Sampling rates in excess of 100 KHz may

result in erratic operation and unpredictable results.

The clock source, internal or external clock, is software selectable through the DAQ-16's
control word register. The configuration of the clock source itself is controlled by jumper
block J2 as shown in Figure 2-6, (* indicates factory default).

Internal Timer: 2 timers cascaded

J2

5 6 7 8

External Timer: w/o pre-divider

1 2 3 4

Figure 2-6. Jumper J2 Configuration

connect 1-2, 6-7*

3 timers cascaded
connect 2-6, 7-8

connect 1-2, 3-4

with pre-divider
connect 2-3, 4-8

2.5.1 Internal Clock

Sampling rates for the internal clock can be calculated using the following equation:

DAQ-16 Users Manual 18

t = 100ns * [N1*N2] or

f = 10MHz / [N1*N2]

where N1 is the low 16-bits of the clock divider and N2 is the high 16-bits of the clock
divider. The following criteria must be met when selecting values for N1 and N2:

2 < N1 < 65,535

2 < N2 < 65,535
N1 * N2 > 100

Using the equations above, the minimum and maximum data sampli ng rates for the internal
clock can be calculated.

Maximum sampling rate: Minimum Sampling Rate:

N1 = 2, N2 = 50 N1 = 65535, N2 = 65535

t = 100 x 10 * [(2)*(50)] t = 100 x 10 * [(65535)*(65535)]

t = 100 x 10 * 100 t = 100 x 10 * [4.295 x 10 ]

−9 −9

−9 −99

t = 10 us t = 429.5 sec

f = 10 x 10 / [(2)*(50)] f = 10 x 10 / [(65535)*(65535)]
f = 10 x 10 / 100 f = 10 x 10 / [4.295 x 10 ]

66
669

f = 100 Khz f = 2.328 mHz

If extremely slow data sampling rates are needed, the third 8254 timer, the multi-function
timer, can be cascaded with the other two to produce a 48-bit clock divider. The sampling
rates are then calculated as follows:

t = 100ns * [N1*N2*N3] or

f = 10MHz / [N1*N2*N3]

where N1 is the low 16-bits of the clock divider, N2 is the intermediate 16-bits of the clock
divider, and N3 is the high 16-bits of the divider. The following criteria must be met when
selecting values for N1, N2, and N3:

2 < N1 < 65,535
2 < N2 < 65,535
2 < N3 < 65,535

N1 * N2 * N3 > 100

When configured for a 48-bit divider, the first sampling period will be slightly longer than

the others because the first clock period is required to load the initial value of the

DAQ-16 Users Manual 19

multi-function timer. The following equation calculates the additional time of the first period:

t = 100ns * [N1 * N2]

add

To minimize the amount of additional time required for the first sample, select clock dividers
such that N1 and N2 are as small as possible and N3 is as large as possible. Using the
equations above, the minimum and maximum data sampling rates and the amount of
additional time required for the first sample can be calculated.

Maximum sampling rate: Minimum sampling rate:

N1 = 2, N2 = 2, N3 = 25 N1 = 65535, N2 = 65535, N3 = 65535

t = 100 x 10 * [(2)*(2)*(25)] t = 100 x 10 * [(65535)*(65535)*(65535)]
t = 100 x 10 * 100 t = 100 x 10 * [2.815 x 10 ]
t = 10 us t = 28.146 x 10 sec
f = 10 x 10 / [(2)*(2)*(25)] t = 325 days, 18 hours, 23 minutes, 29 sec

f = 10 x 10 / 100 f = 10 x 10 / [(65535)*(65535)*(65535 ) ]

f = 100 Khz f = 10 x 10 / [2.815 x 10 ]

−9 −9

−9 −914

6

6

66

614

f = 35.529 nHz

t = 100 x 10 * [2 * 2] t = 100 x 10 * [65535 * 65535]
t = 100 x 10 * 4 t = 100 x 10 * [4.295 x 10 ]
t = 400 ns t = 429.5 sec

add
add
add add

−9

−9

add
add

−9

−99

2.5.2 External Clock

The external cl ock input to the DAQ-16 is a TTL level (0 - 5 volt) signal. This input may be
used to control the sampling rate directly, or it may be fed through a pre-divider (the
multi-function timer) with the timer output controlling the A/D sampling rate. When used to
control the sampling rate directly, the frequency of the external clock input may be varied
from DC to 100 KHz as long as the width of the low and high portions of the clock are a
minimum of 1 us each. The A/D conversion cycle will begin on each rising edge of the
external clock input. (See Figure 2-7).

1 usec min 1 usec min

10 usec

min

Figure 2-7. Sampling Rate External Clock Pulses

When the multi-function timer is used as a pre-divider, the frequency of the external clock

input may b e varied from DC to 10 MHz as long as the high portion of the cl ock is at least

DAQ-16 Users Manual 20

30ns and the low portion i s at least 50ns. Except for the fi rst period, the sampli ng rate of the
DAQ-16 will be the external clock frequency divided by the count value written to the
multi-functi on timer. Si nce one clock pul se is requi red to load the initi al count val ue into the
timer, the first sampling interval will be one clock cycle longer than the rest. The valid range
of count values for the mul ti-function timer is 2 < count < 65,535 but the resulting sampling
rate must be less than 100KHz to assure proper operation of the A/D converter circuitry.
(See Figure 2-8).

30 nsec min 50 nsec min

100 nsec

min

Figure 2-8. Pre-Divider External Clock Pulses

2.6 Trigger Selection

The DAQ-16 is capable of accepting an internal software trigger or an external hardware
trigger. The trigger selection and trigger level bits in the DAQ-16 control word register select
the trigger source and level. Upon reset, the trigger selection and trigger level bits default to
the internal software trigger. When the internal trigger is used, an output to the
start-of-conversion register will trigger the DAQ-16 to begin sampling the input. For
triggering off an external event, the DAQ-16 accepts a level sensitive, TTL compatible trigger
input from the D-62 connector. The trigger level bit in the DAQ-16 control word register
determines which TTL level is used to trigger the A/D converter to begin sampling.

When an internal clock source is used, a delay of not more than 225ns will occur between the
trigger and the first data sample. When an external clock is used, the delay will be dependent
on the frequency and duty cy cle of the clock input. If these delay s are unacceptabl e, the clock
and trigger circuitry can be bypassed and a start of conversion pulse can be input directly into
the A/D circuitry w ith a maximum delay of 25ns. If the user controls the start of conversion
pulse directly, the sample will be taken on the low to high transition of the pulse, the pulse
must have a durati on of at l east 10 us, and the duty cycl e must be betw een 5 and 80 per cent.
Jumper J1, shown in Figure 2-9, configures start of conversion control.

J1

Start of Conversion:

(* indicates factory default)
DAQ-16 controlled: connect 1-2*

1 2 3

Figure 2-9. Jumper J1 Configuration

User controlled: connect 2-3

2.7 Direct Memory Access

Direct Memory Access (DMA) transfers provide a way of transferring data from the

DAQ-16 Users Manual 21

DAQ-16's A/D converter into the computer's memory without using the Central Processing
Unit (CPU). DMA capability enables other system software to be executed while data is being
input from the DAQ-16.

The DAQ-16 actually implements two DMA channels. The advantage of having two DMA
channels is that one channel can be transferring data while the second channel is being
programmed. When the first channel is finished, the second channel will automatically take
over and continue the data transfer. The fi rst channel can then be re-prog rammed while the
second channel is transferring data. In this way, the DAQ-16 can acquire data continuously
until terminated by the user.

The DAQ-16 supports 16-bi t DMA transf ers on channel s 5, 6, and 7. The D MA channel( s) are
selected by jumpers J8 and J9 as shown in Figure 2-10.

DMA Cha nnel 1 DMA Cha nnel 2

J8

DRQ7
DACK7

DRQ6
DACK6

DRQ5
DACK5

J9

DRQ7
DACK7

DRQ6
DACK6

DRQ5
DACK5

Figure 2-10. Jumpers J8 and J9 Configuration

WARNING: To properly implement the DMA capability, the DRQ and DACK of each

DMA channel must be jumpered to the same number, i.e. DRQ 5/DACK 5. If both DMA

channels are to be used, each channel must be jumpered to a different number, i.e. channel

1 is jumpered to DRQ 5 /DACK 5 and channel 2 is jumpered to DRQ 7/DACK 7.

2.8 Interrupts

DAQ-16 Users Manual 22

The DAQ-16 is capable of generating an interrupt from one of four sources:

1. End of conversion signal

2. DMA terminal count

3. Multi-function timer output

4. External interrupt input

The interrupt source is software selected through the DAQ-16 control word register. The
interrupt level is selected using the jumpers J10 and J11 as shown in Figure 2-11.

J10

IRQ 14

IRQ 15

IRQ 12

IRQ 11

IRQ 10

IRQ 3

IRQ 2

IRQ 4

IRQ 5

IRQ 6

J11

IRQ 7

Factory default = IRQ 5

Figure 2-11. Jumpers J10 and J11 Configuration

2.8.1 External Interrupt

The external interrupt is a TTL compatible input from the D-62 connector. An interrupt
request is generated on a high to low transition of this input.

3. External Connections

The DAQ-16 is equipped with a high density 62-pin connector as shown in Figure 3-1.

DAQ-16 Users Manual 23

2 - CH1+

4 - CH2-

6 - CH4+
8 - CH5-

10 - CH7+
12 - AOUT0
14 - DOUT0
6 - DOUT3
18 - EXT TRIG
20 - DIN1
22 - CH0+
24 - CH1­ 26 - CH3+
28 - CH4­ 30 - CH6+
32 - CH7­ 34 - AOUT1
36 - DOUT1

38 - EXT INT

40 - DIN3
42 - DIN0
43 - CH0­ 45 - CH2+
47 - CH3­ 49 - CH5+
51 - CH6­ 53 - VREF0
55 - VREF1
57 - DOUT2
59 - EXT CLK
61 - DIN2

1

2

4

10

11

12

13

14

15

16

17

18

19

20
21

22

43

23

44

24

26

27

28

30
31

32

33

34

36

37

40

25

29

35

38

39

41

42

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61
62

3

5

6

7

8

9

Figure 3-1. 62 Pin Connector Diagram

Analog Ground - 1, 3, 5, 7, 9, 11, 13, 44, 46, 48, 50, 52, 54
Digital Ground - 15, 17, 19, 21, 37, 39, 41, 56, 58, 60, 62

CH0-,CH0+,...,CH7-,CH7+ : Analog inputs to the analog to digital converter. Amplitude and

DAQ-16 Users Manual 24

polarity depend upon jumper settings. The input resistance of these lines is 1.5K ohms
typical.
AOUT0, AOUT1: Analog outputs from the digital to analog converters. Polarity and
maximum amplitude depend on the jumper settings and voltage references. Output
resistance of the analog outputs is typically 70 ohms.

VREF0, VREF1: External voltage references for the digital to analog converters. Input range
is 0 to 5.5 volts with a no-load input resistance of 7.5K ohms.

EXT CLK, EXT TRG, EXT INT: External clock, trigger, and interrupt inputs respectively.
Inputs are TTL compatible.

DOUT0, DOUT1, DOUT2, DOUT3: TTL compatible digital output lines.

DIN0, DIN1, DIN2, DIN3: TTL compatible input lines.

4. Register Description and Programming

The DAQ-16 uses 16 consecutive I/O address locations in the range 0 to FFFFH. The card

Read/Write 8-bit 8254 Control Word/Status Register

Base F *

Read/Write 8-bit Multi-function Timer Register

Base E *

Read/Write 8-bit Clock Rate Register (high)

Base + D *

Read/Write 8-bit Clock Rate Register (low)

Base + C *

Reserved

Base 9, A, B

Read/Write 8-bit Digital Input/Output Register

Base + 8

Write only 16-bit D/A Channel 1 Register

Base + 6, 7

Write only 16-bit D/A Channel 0 Register

Base + 4, 5

Write only 16-bit Start Conversion Register

Base + 2, 3
Read/Write 16-bit Control Word Register

Base + 0, 1

DAQ-16 Users Manual 25

utilizes these addresses for the registers listed in Table 4-1. (* indicates registers located in
8254 counter).

Read only 16-bit A/D Data Register

Table 4-1. DAQ-16 Address Map

4.1 Register Description

4.1.1 Control Word Register

The control word register defines and controls many of the DAQ-16's data conversion
functions. This register is 16-bit read/write.

Write Read Write Read

D15 INT2 INT2 D7 RUN RUN

D14 INT1 INT1 D6 0 EOC
D13 INT0 INT0 D5 0 VALID
D12 DMAEN DMAEN D4 0 0

D11 DMACT DMACH D3 0 0

D10 LEVEL LEVEL D2 CHSL2 CHSL2

D9 TRIG TRIG D1 CHSL1 CHSL1

D8 CLK CLK D0 CHSL0 CHSL0

INT2, INT1 and INT0 control the DAQ-16 interrupt source.

INT2 INT1 INT0 DESCRIPTION

0 0 0 Interrupt disabled
1 0 0 Interrupt timer 2
1 0 1 Interrupt on terminal count
1 1 0 External interrupt
1 1 1 Interrupt on end of conversion

DMAEN - enables / disables DMA. When set, logic 1, DMA transfers are enabled.

DMACT - enables the multi-channel DMA capability of the DAQ-16. When set, logic 1, a

DAQ-16 Users Manual 26

terminal count on the active D MA channel causes DMA transfers to begi n on the "stand-by"
channel. When cleared, logic 0, DMA transfers halt when the terminal count is reached on
the active channel.

DMACH - indicates which of the DAQ-16's DMA channels is currently active to transfer
data. Logic 0 indicates DMA channel 0, logic 1 indicates DMA channel 1.

LEVEL - selects the edge of the external trigger input. When set, logic 1, A/D conversions
will begin on the falling edge of the external trigger input. When cleared, logic 0, conversions
will begin on the rising edge of the external trigger. IMPORTANT: LEVEL must be logic 0
when internal triggering is used.

TRIG - selects betwee n internal a nd e x ter n al trigger s. When set, log ic 1, the e xte r na l tr igger
is selected.

CLK - sel ects between internal and external clock sources. When set, logic 1, the external
clock source is selected.

RUN - when set, logic 1, the A/D converter is placed in the 'run' mode and will begin
converting data when a trigger is received. RUN may be cleared at any time by writing a "0"
to it. When using DMA transfers, RUN is automatically cleared when a terminal count is
received with DMACT set to "0".

EOC - when set, indicates an end of conversion has taken place and the data is available in
the A/D converter data register.

VALID - when set, logic 1, indicates at least one data sample was lost because it was read by
the computer before the next sample was converted . The data was lost because the sampling
rate was too fast for the computer to acquire data. VALID is reset by writing to the start
conversion register.

CHSL2, CHSL1, CHSL0 - select the multiplexer channel for the analog input signal.

CHSL2 CHSL1 CHSL0 MUX channel

0 0 0 channel 0

0 0 1 channel 1

0 1 0 channel 2
0 1 1 channel 3
1 0 0 channel 4
1 0 1 channel 5
1 1 0 channel 6
1 1 1 channel 7

4.1.2 Start of Conversion Register

DAQ-16 Users Manual 27

The start of conversion register is 16-bit write only and performs two functions:

1. When configured for internal triggering, writing a "0" to this register generates the
software trigger, starting the data conversion process.

2. Writing a "0" to this register at any time resets the VALID bit in the control word
register. This allow s the VALID b it to be reset at any ti me duri ng the conversion
process or before the event of an external trigger.

4.1.3 DAC0 Register

An output to this register causes the lower twelve bits of data to be converted to an analog
output on D/A converter channel 0. The four most significant bi ts of data are i gnored. This
register is 16-bit write only.

4.1.4 DAC1 Register

An output to this register causes the lower twelve bits of data to be converted to an analog
output on D/A converter channel 1. The f our most signif icant bits of d ata are ig nored. Thi s
register is 16-bit write only.

The remaining four registers are contained in an 8254 counter/timer.

4.1.5 Clock Rate Register (low word)

The low word of the clock divider is contained in counter 0 of an 8254 counter/timer. The
output of this counter i s cascaded i nto the input of counter 1 to pr oduce a 32- bit time r. Mode
2 must be selected for counter 0 with a minimum count of 2. This register is 8-bit read/write.

4.1.6 Clock Rate Register (high word)

The high word of the clock divi der is contained in counter 1 of the 8254 counter/timer. Mode
2 must be selected for counter 1 with a minimum count of 2. This register is 8-bit read/write.

4.1.7 Multi-Function Timer Register

The multi-function timer is implemented usi ng counter 2 of the 8254 counter/timer. Mode
2 must be selected for this timer with a minimum count of 2. This register is 8-bit read/write.

4.1.8 8254 Control Word/Status Register

This register is used to program the mode and report the status of the 8254 counter/timer.
This register is 8-bit read/write.

4.2 Programming the 8254 Counter/Timer

This section provides programming information for the 8254 counter/timer as implemented

DAQ-16 Users Manual 28

on the DAQ-16. For more details on the 8254, consult the Intel Micro-Processor and Peripheral
Handbook.

To program any of the counters contained in the 8254 counter/timer, three steps are required:

1. Write the configuration by te to the 8254 mode select/status register. This byte sets
the operating mode of the selected counter.

2. Write the least significant byte of the count value to the selected counter register.

3. Write the most significant byte of the count value to the selected counter register.

The following examples illustrate the programming sequence for each of the counters in the

8254. The variable 'base_address' is the base add ress of the DAQ-16 as defined by the address
selection switches.

Counter 0 - Clock rate register (low word)

operating mode: 2
minimum count value: 2
configuration byte: 0 / 0 / 1 / 1 / 0 / 1 / 0 / 0 = 34H

Example: Program the value 2675H into the low word of the clock rate register.

output 34H to base_address + 0FH
output 75H to base_address + 0CH
output 26H to base_address + 0CH

Example: Program the value 0008H into the low word of the clock rate register.

output 34H to base_address + 0FH
output 08H to base_address + 0CH
output 00H to base_address + 0CH

Counter 1 - Clock rate register (high word)

operating mode: 2

DAQ-16 Users Manual 29

minimum count value: 2
configuration byte: 0 / 1 / 1 / 1 / 0 / 1 / 0 / 0 = 74H

Example: Program the value 13A4H into the high word of the clock rate register.

output 74H to base_address + 0FH
output A4H to base_address + 0DH
output 13H to base_address + 0DH

Example: Program the value FFFFH into the high word of the clock rate register.

output 74H to base_address + 0FH
output FFH to base_address + 0DH
output FFH to base_address + 0DH

Counter 2 - Multi-function timer register

operating mode: 2
minimum count value: 2
configuration byte: 1 / 0 / 1 / 1 / 0 / 1 / 0 / 0 = B4H

Example: Program the value 000AH into the multi-function timer register.

output B4H to base_address + 0FH
output 0AH to base_address + 0EH
output 00H to base_address + 0EH

Example: Program the value 0100H into the multi-function timer register.

output B4H to base_address + 0FH
output 00H to base_address + 0EH
output 01H to base_address + 0EH

DAQ-16 Users Manual
Version 2.20
January 28, 1999
Part No. 940-0032-220