98 UP1_2Inout, 4MA, SR, PU, SMT Microcontroller port 1-2
99 UP1_3Inout, 4MA, SR, PU, SMT Microcontroller port 1-3
100 UP1_4Inout, 4MA, SR, PU, SMT Microcontroller port 1-4
101 UP1_5Inout, 4MA, SR, PU, SMT Microcontroller port 1-5
102 UP1_6SCLInout, 4MA, SR, PU, SMT
103 UP1_7SDAInout, 4MA, SR, PU, SMT
104 UP3_0RXDInout, 4MA, SR, PU, SMT
105 UP3_1TXDInout, 4MA, SR, PU, SMT
Inout, 2-16MA,
SR, PU, SMT
Inout, 2-16MA,
SR, PU, SMT
Inout, 2-16MA,
SR, PU, SMT
Inout, 2-16MA,
SR, PU, SMT
Microcontroller address latch enable
Flash chip select, active low / IO
Microcontroller write strobe, active low
Microcontroller read strobe, active low
Microcontroller port 1-6
2
I
C clock pin
Microcontroller port 1-7
2
I
C data pin
Microcontroller port 3-0
8032 RS232 RXD
Microcontroller port 3-1
8032 RS232 TXD
106 UP3_4RXD SCLInout, 4MA, SR, PU, SMT
107 UP3_5TXD SDAInout, 4MA, SR, PU, SMT
111 IRInput, SMTIR control signal input
112 INT0#
Inout, 2-16MA,
SR, PU, SMT
Microcontroller port 3-4
Hardwired RD232 RXD
2
I
C clock pin
Microcontroller port 3-5
Hardwired RD232 TXD
2
I
C data pin
Microcontroller external interrupt 0, active low
Page 7
EGOFOOLLER
Audio Interface (14)
For Education by EgoFooller
No.NameAlt.I/OFunction
Audio DAC master clock of SPDIF input
208 SPMCLKSCLK0Inout
209 SPDATASDIN0Inout
210 SPLRCKSDO0Inout
211 SPBCK
213 ALRCK
214 ABCKFs64
215 ACLKInout, 4MAAudio DAC master clock
217 ASDATA0
218 ASDATA1
219 ASDATA2
220 ASDATA3
222 ASDATA4INT1#
224 MC_DATAINT2#Inout
225 SPDIF
SDCS0
ASDATA5
Inout
Inout
4MA, PD, SMT
Output
4MA
Inout, 4MA,
PD SMT
Inout, 4MA,
PD SMT
Inout, 4MA,
PD SMT
Inout, 4MA,
PD SMT
Inout, 4MA,
PD SMT
Output, 2-16MA,
SR : ON/OFF
While SPDIF input is not used:
Serial interface port 0 clock pin
GPIO
Audio data of SPDIF input
While SPDIF input is not used:
Serial interface port 0 data-in
GPIO
Audio left/right channel clock of SPDIF input
While SPDIF input is not used:
Serial interface port 0 data-out
GPIO
Audio bit clock of SPDIF input
While SPDIF input is not used:
Serial interface port 0 chip select
Audio serial data 5 part I : DSD data sub-woofer
channel or Microphone output
GPIO
Audio left/right channel clock
Trap value in power-on reset:
1 : use external 373
0: use internal 373
Audio bit clock
Phase de-modulation
Audio serial data 0 (Front-Left/Front-Right)
DSD data left channel
Trap value in power-on reset :
1 : manufactory test mode
0 : normal operation
Audio serial data 1 (Left-Surround/Right-Surround)
DSD data right channel
Trap value in power-on reset :
1 : manufactory test mode
0 : normal operation
While only 2 channels output:
GPIO
Audio serial data 2 (Center/LFE)
DSD data left surround channel
Trap value in power-on reset :
1 : manufactory test mode
0 : normal operation
While only 2 channels output:
GPIO
Audio serial data 3 (Center-back/ Center-left-back/Center-right-back, in 6.1 or
7.1 mode)
DSD data right surround channel
Trap value in power-on reset :
1 : manufactory test mode
0 : normal operation
While only 2 channels output:
GPIO
Audio serial data 4 (Down-mixed Left/Right)
DSD data center channel
Trap value in power-on reset :
1 : manufactory test mode
0 : normal operation
While only 2 channels output:
Microcontroller external interrupt 1
GPIO
Microphone serial input
While not support Microphone:
Microcontroller external interrupt 2
GPIO
SPDIF output
Page 8
EGOFOOLLER
Video Interface (18)
For Education by EgoFooller
No.NameAlt.I/OFunction
189 DACVDDCPower3.3V power pin for VIDEO DAC circuitry
190 VREFAnalogBandgap reference voltage
191 FSAnalogFull scale adjustment
192 YUV0CIN
193 DACVSSCGroundGround pin for VIDEO DAC circuitry
194 YUV1Y
195 DACVDDBPower3.3V power pin for VIDEO DAC circuitry
196 YUV2C
197 DACVSSBGroundGround pin for VIDEO DAC circuitry
198 YUV3CVBS
199 DACVDDAPower3.3V power pin for VIDEO DAC circuitry
200 YUV4Y/G
201 DACVSSAGroundGround pin for VIDEO DAC circuitry
202 YUV5B/Cb/Pb
203 YUV6R/Cr/Pr
205 VSYNV_ADIN1
206 YUV7
207 HSYN
INT3#
ASDATA5
INT4#
V_ADIN2
Output
4MA, SR
Output
4MA, SR
Output
4MA, SR
Output
4MA, SR
Output
4MA, SR
Output
4MA, SR
Output
4MA, SR
Inout
4MA, SR
SMT
Inout
4MA, SR
SMT
Inout
4MA, SR
SMT
Video data output bit 0
Compensation capacitor
Video data output bit 1
Analog Y output
Video data output bit 2
Analog chroma output
Video data output bit 3
Analog composite output
Video data output bit 4
Green or Y
Video data output bit 5
Blue or CB
Video data output bit 6
Red or CR
Vertical sync input/output
While no External TV-encoder:
Vertical sync for video-input
Version AD input port 1
GPIO
Video data output bit 7
While no External TV-encoder:
Microcontroller external interrupt 3
Audio serial data 5 part II : DSD data sub-woofer channel or Microphone
output
GPIO
Horizontal sync input/output
While no External TV-encoder:
Horizontal sync for video-input
Microcontroller external interrupt 4
Version AD input port 2
GPIO
MISC (8)
No.NameAlt.I/OFunction
43 USB_VSSUSB GroundUSB ground pin
44 USBPAnalog InoutUSB port DPLUS analog pin
45 USBMAnalog InoutUSB port DMINUS analog pin
46 USB_VDD3USB PowerUSB Power pin 3.3V
110 PRST#Input PU, SMT Power on reset input, active low
While using 16-bits wide DRAM:
Line Locked Clock input/output
Digital Video output C bit 0
GPIO
DRAM data 17
While using 16-bits wide DRAM:
Video input data 0
Digital Video output C bit 1
GPIO
DRAM data 18
While using 16-bits wide DRAM:
Video input data 1
Digital Video output C bit 2
GPIO
DRAM data 19
While using 16-bits wide DRAM:
Video input data 2
Digital Video output C bit 3
GPIO
DRAM data 20
While using 16-bits wide DRAM:
Video input data 3
Digital Video output C bit 4
GPIO
DRAM data 21
While using 16-bits wide DRAM:
Video input data 4
Digital Video output C bit 5
GPIO
DRAM data 22
While using 16-bits wide DRAM:
Video input data 5
Digital Video output C bit 6
GPIO
DRAM data 23
While using 16-bits wide DRAM:
Video input data 6
Digital Video output C bit 7
GPIO
Data Mask 2
While using 16-bits wide DRAM:
Video input data 7
GPIO
Data Mask 3
While using 16-bits wide DRAM:
Microcontroller external interrupt 6
Digital Video output Clock
USB port CLK input (48MHz) part II
GPIO
DRAM data 24
While using 16-bits wide DRAM:
Serial interface port 1 data-in
MS Card BS pin part II
Digital Video output Y bit 0
GPIO
DRAM data 25
While using 16-bits wide DRAM:
Serial interface port 1 data-out
MS Card SDIO pin part II
Digital Video output Y bit 1
GPIO
Page 10
EGOFOOLLER
No.NameAlt.I/OFunction
For Education by EgoFooller
DRAM data 26
174 RD26
172 RD27
171 RD28
170 RD29
169 RD30
168 RD31
166 RA4InoutDRAM address 4
165 RA5InoutDRAM address 5
164 RA6InoutDRAM address 6
162 RA7InoutDRAM address 7
160 RA8InoutDRAM address 8
159 RA9InoutDRAM address 9
158 RA11GPIO
157 CKEoutputDRAM clock enable
156 RCLKInoutDRAM clock
154 RCLKBUSB_CLKInout
153 RVREFV_ADIN3Analog Inout
151 RA3InoutDRAM address 3
150 RA2InoutDRAM address 2
149 RA1InoutDRAM address 1
147 RA0InoutDRAM address 0
146 RA10InoutDRAM address 10
145 BA1InoutDRAM bank address 1
143 BA0InoutDRAM bank address 0
SDCS1
MSCLK
SMPTE_Y[2]
SCLK2
SDCLK
SMPTE_Y[3]
SDIN2
SD_CMD
SMPTE_Y[4]
SDO2
SD_DAT
SMPTE_Y[5]
SDCS2
SMPTE_Y[6]
INT5#
ASDATA5
SMPTE_Y[7]
Inout
Non-pull
Inout
Non-pull
Inout
Non-pull
Inout
Non-pull
Inout
Pull-Up
Inout
Pull-Up
Inout
Pull-Down
While using 16-bits wide DRAM:
Serial interface port 1 chip select
Memory Stick Clock part II
Digital Video output Y bit 2
GPIO
DRAM data 27
While using 16-bits wide DRAM:
Serial interface port 2 clock pin
Security Disk Clock part II
Digital Video output Y bit 3
GPIO
DRAM data 28
While using 16-bits wide DRAM:
Serial interface port 2 data-in
SD Card CMD pin part II
Digital Video output Y bit 4
GPIO
DRAM data 29
While using 16-bits wide DRAM:
Serial interface port 2 data-out
SD Card Data pin part II
Digital Video output Y bit 5
GPIO
DRAM data 30
While using 16-bits wide DRAM:
Serial interface port 2 chip select
Digital Video output Y bit 6
GPIO
DRAM data 31
While using 16-bits wide DRAM:
Microcontroller external interrupt 5
Audio serial data 5 part III : DSD data sub-woofer channel or Microphone
output
Digital Video output Y bit 7
GPIO
DRAM address bit 11
While using DRAM size <=4MB:
GPIO
DRAM clock invert
While not using DDR:
I) USB port CLK input (48MHz) part I
Reference voltage for DDR DRAM
While not using DDR :
Version AD input port 3
Page 11
EGOFOOLLER
No.NameAlt.I/OFunction
For Education by EgoFooller
142 RCS#outputDRAM chip select, active low
140 RAS#outputDRAM row address strobe, active low
139 CAS#outputDRAM column address strobe, active low
138 RWE#outputDRAM Write enable, active low
137 DQM1InoutData mask 1
Data strobe 1 for DDR DRAM
136 DQS1
135 RD8InoutDRAM data 8
133 RD9InoutDRAM data 9
132 RD10InoutDRAM data 10
131 RD11InoutDRAM data 11
130 RD12InoutDRAM data 12
129 RD13InoutDRAM data 13
128 RD14InoutDRAM data 14
126 RD15InoutDRAM data 15
125 RD0InoutDRAM data 0
124 RD1InoutDRAM data 1
123 RD2InoutDRAM data 2
121 RD3InoutDRAM data 3
120 RD4InoutDRAM data 4
118 RD5InoutDRAM data 5
117 RD6InoutDRAM data 6
115 RD7InoutDRAM data 7
114 DQS0
113 DQM0InoutData mask 0
INT7#
MS_BS
SCLK1
MS_SDIO
Inout
Inout
While not using DDR:
Microcontroller external interrupt 7
MS Card BS pin part I
GPIO
Data strobe 0 for DDR DRAM
While not using DDR:
Serial interface port 1 clock pin
MS Card SDIO pin part I
GPIO
JTAG Interface (4)
No.NameAlt.I/OFunction
JTAG data in
While not using Boundary Scan:
Serial interface port 3 data-out
Version AD input port 4
SD Card Data pin part I
GPIO
While not using Boundary Scan:
Serial interface port 3 data-in
Version AD input port 5
SD Card CMD pin part I
GPIO
JTAG clock
While not using Boundary Scan:
Serial interface port 3 clock pin
Version AD input port 6
Security Disk Clock part I
GPIO
JTAG data out
While not using Boundary Scan:
Serial interface port 3 chip-select
Version AD input port 7
Memory Stick Clock part I
GPIO
48 TDI
49 TMS
50 TCK
51 TDO
SDO3
V_ADIN4
SD_DAT
SDIN3
V_ADIN5
SD_CMD
SCLK3
V_ADIN6
SDCLK
SDCS3
V_ADIN7
MSCLK
Inout
Inout
Inout
Inout
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