OKI MSM82C59A-2JS, MSM82C59A-2RS, MSM82C59A-2GS-K Datasheet

E2O0021-27-X3

¡ Semiconductor MSM82C59A-2RS/GS/JS

¡ Semiconductor

This version: Jan. 1998

Previous version: Aug. 1996

MSM82C59A-2RS/GS/JS

PROGRAMMABLE INTERRUPT CONTROLLER

GENERAL DESCRIPTION

The MSM82C59A-2 is a programmable interrupt for use in MSM80C85AH and MSM80C86A10/88A-10 microcomputer systems. Based on CMOS silicon gate technology, this device features an extremely low standby current of 100mA (max.) in chip non-selective status. During interrupt control status, the power consumption is very low with only 5 mA (max.) being required. Internally, the MSM82C59A-2 can control priority interrupts up to 8 levels, and can be expanded up to 64 levels by cascade connection of a number of devices.

FEATURES

• Silicon gate CMOS technology for high speed and low power consumption

• 3 V to 6 V single power supply

• MSM80C85AH system compatibility (MAX5 MHz)

• MSM80C86A-10/88A-10 system compatibility (MAX8 MHz)

• 8-level priority interrupt control

• Interrupt levels expandable up to 64 levels

• Programmable interrupt mode

• Maskable interrupt

• Automatically generated CALL code (85 mode)

• TTL compatible

• 28-pin Plastic DIP (DIP28-P-600-2.54): (Product name: MSM82C59A-2RS)

• 28-pin Plastic QFJ (QFJ28-P-S450-1.27): (Product name: MSM82C59A-2JS)

• 32-pin Plastic SSOP (SSOP32-P-430-1.00-K): (Product name: MSM82C59A-2GS-K)

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¡ Semiconductor MSM82C59A-2RS/GS/JS

g

BLOCK DIAGRAM

INTA INT

Data

D

- D

7

0

Bus

Buffer

Control Logic

RD

WR

A

CS

CAS CAS CAS

SP/EN

Read/

Write

0

Logic

In-

Service

Register

Priority

Resolver

(ISR)

0

1

2

Cascade

Buffer/

Comparator

Interrupt Mask Register (IMR)

Interrupt

Request Register

(IRR)

IR IR IR IR IR IR IR IR

0 1 2 3 4 5 6 7

Internal Bus (8 bits)

MSM82C59A-2 Internal Block Dia

ram

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¡ Semiconductor MSM82C59A-2RS/GS/JS

PIN CONFIGURATION (TOP VIEW)

32 pin Plastic SSOP

WR

CAS CAS

GND

28 pin Plastic DIP

1

CS

2 3

RD

4

D

7

5

D

6

D

5

7

D

4

8

D

3

9

D

2

10

D

1

11

D

0

12

0

13

1

14

28

V

CC

27

AO

26

INTA

25

IR

7

24

IR

6

23

IR

5

22

IR

4

21

IR

3

20

IR

2

19

IR

1

18

IR

0

17

INT

16

SP/EN

15

CAS

2

28 pin Plastic QFJ

WR

CAS CAS

GND

CS

RD

NC

D D D D D D D D

NC

1 2 3 4 5

7

6

7

5

8

4

9

3

10

2

11

1

12

0

13 14

0

15

1

16

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

V

CC

AO

INTA

NC IR

7

IR

6

IR

5

IR

4

IR

3

IR

2

IR

1

IR

0

NC INT SP/EN CAS

2

7

D

RD3WR2CS1V

4

5

D

6

D

5

7

D

4

8

D

3

9

D

2

10

D

1

11

D

0

13

1

CAS

14

GND

12

0

CAS

15

2

CAS

CC

28

16

SP/EN

A027INTA

26

17

18

0

IR

INT

25

24

23

22

21

20

19

IR

7

IR

6

IR

5

IR

4

IR

3

IR

2

IR

1

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¡ Semiconductor MSM82C59A-2RS/GS/JS

ABSOLUTE MAXIMUM RATINGS

Parameter Unit

Power Supply Voltage

Input Voltage

Output Voltage

Storage Temperature

Power Dissipation

Symbol

V

CC

V

IN

V

OUT

T

STG

P

D

Conditions

Respect

to GND

—

Ta = 25°C

MSM82C59A-2RS

MSM82C59A-2GS MSM82C59A-2JS

–0.5 - +7

–0.5 - V

CC

+0.5

–55 - +150

0.7

0.90.9

OPERATING RANGES

Rating

Parameter UnitSymbol

Power Supply voltage

Operating Temperature

V

CC

T

OP

Range

3 - 6

–40 - +85

RECOMMENDED OPERATING CONDITIONS

V

°C

W

V

°C

Parameter UnitSymbol

Power Supply Voltage

Operating Temperature

"L" Lebel Input Voltage V

"H" Lebel Input Voltage

Min.

V

CC

T

OP

IL

V

IH

4.5

-40

-0.5

2.2

Typ.

5V

+25

—

Max.

+85

+0.8

V

CC

5.5

+0.5

DC CHARACTERISTICS

Parameter Unit

"L" Level Output Voltage

"H" Level Output Voltage

Input Leak Current

IR Input Leak Current

Output Leak Current

Standby Power Supply Current

Symbol

V

OL

V

OH

I

LI

I

LIR

I

LO

I

CCS

I

= 2.5 mA

OL

I

= –2.5 mA

OH

I

= –100 mA

OH

0 £ V

CS = V V

= 0 V, V

IL

IN

OUT

CC,

£ V

IR = V

IH

Conditions

CC

V

CC

Ta

= –40°C - +85°C

CC

= VCC

= 4.5 V - 5.5 V

Typ. Max.

— 0.4 V

——

—1mA

V

Min.

—

3.0

–0.4

CC

–1

–300 — 10

–10

—

—10mA

0.1 100 mA

°C

V

mA

Average Operation Power Supply Current

V

= 0 V/VCC

I

CC

IN

C

L

= 0 pF

—

5mA

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¡ Semiconductor MSM82C59A-2RS/GS/JS

AC CHARACTERISTICS

Parameter

Address Setup Time (to RD) Address Hold Time (after RD) RD/INTA Pulse Width Address Setup Time (to WR)

Address Hold Time (after WR)

WR Pulse Width Data Setup Time (to WR) Data Hold Time (after WR)

IR Input Width(Low) CAS Input Setup Time (to INTA) (Slave)

End of RD to Next RD End of INTA to Next INTA

End of WR to Next WR

End of Command to Next Command Data Valid Following RD/ INTA Data Floating Following RD/ INTA

INT Output Delay Time CAS Valid Following 1 st. INTA (master)

EN Active Following RD/INTA EN Inactive Following RD/ INTA

Data Valid after Address

Data Valid after CAS

t

AHRL

t

RHAX

t

RLRH

t

AHWL

t

WHAX

t

WLWH

t

DVWH

t

WHDX

t

JLJH

t

CVIAL

t

RHRL

t

WHWL

t

CHCL

t

RLDV

t

RHDZ

t

JHIH

t

IALCV

t

RLEL

t

RHEH

t

AHDV

t

CVDV

Min. Max.

10

5

160

0

—ns

0—

190

160

0

100

40

160

190

400

—

10

—

—ns

120 ns

85 ns

300 ns

360 ns

100 ns

150 ns

200 ns

Ta = –40°C - +85°C, V

UnitSymbol

TEST Conditions

—

1

2

1 1

1

Read INTA timing

Write timing

INTA sequence

Other timing

Delay times

= 5 V ± 10%

CC

AC Test Circuits

Output from

Device under Test

* Includes Stray and Jig Capacitance

Test Condition Definition Table

Test Condition R2V1

1

2

V1

R1

R2

1.7 V

4.5 V

Test Point

R1

523 W

1.8k W

C1*

1.8k W

Open

A.C. Testing Input, Output Waveform

Input

VIH+0.4 V

1.5V 1.5 V

V

–0.4 V

IL

A. C. Testing: All input signals must switch between

V

–0.4 V and VIH+0.4 V.

IL

T

and TF must be less than of equal to 15 ns.

R

C1

100 pF

30 pF

Output

V

OH

V

OL

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¡ Semiconductor MSM82C59A-2RS/GS/JS

TIMING CHART

Write Timing

WR

t

WLWH

Address Bus

Data Bus

Read/INTA Timing

RD/INTA

Address Bus

Data Bus

CS

A

EN

CS

A

t

AHWL

0

t

DVWH

t

RLRH

t

RLEL

t

AHRL

0

t

RLDV

t

AHDV

t

WHAX

t

RHEH

t

WHDX

t

RHAX

t

RHDZ

Other Timing

RD/INTA/WR

RD/INTA

WR

t

RHRL

t

WHWL

t

CHCL

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¡ Semiconductor MSM82C59A-2RS/GS/JS

INTA Sequence (85 mode)

t

IR

t

JLJH

INT

INTA

Data Bus

JHIH

t

CVIAL

CAS Address Bus

INTA Sequence (86 mode)

IR

INT

INTA

t

CVDV

t

IALCV

Data Bus

CAS Address Bus

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¡ Semiconductor MSM82C59A-2RS/GS/JS

PIN FUNCTION DESCRIPTION

Pin Symbol

D7 - D

0

CS

RD

WR

A

0

Name

Bidirectional

Input/Output

Data Bus

Chip Select

Input

Read Input

Input

Write Input Input

Address

Input

Function

This 3-state 8-bit bidirectional data bus is used in reading status registers and writing command words through the RD/WR signal from the CPU, and also in reading the CALL instruction code by the INTA signal from the CPU.

Data transfer with the CPU is enabled by RD/WR when this pin is at low level. The data bus (D

thru D7) is switched to high impedance

0

when the pin is at high level. Note that CS does not effect INTA.

Data is transferred from the MSM82C59A-2 to the CPU when this pin is at low level. IRR (Interrupt Request Register), ISR (In-Service Register), IMR (Interrupt Mask Register), or a Poll word is selected by OCW3 and A

.

0

Commands are transferred from the CPU to the MSM82C59A-2 when this pin is at low level.

This pin is used together with the CS, WR, and RD signals to write commands in the command registers, and to select and read status registers. This is normally connected to the least significant bit of the address bus. (A

for MSM80C85AH, A1 for MSM80C86A-10/88A-10).

0

CAS

SP/EN

INT

INTA

IR

0

-

0

2

Cascade

Address

Input/Output

These pins are outputs when the MSM82C59A-2 is used as the master, and inputs when used as a slave (in cascade mode). These pins are outputs when in single mode.

Slave Program

Input/Enable

Buffer Output

Interrupt

Output

Interrupt

Acknowledge

Input

Input/Output

Output

Input

This dual function pin is used as an output to enable the data bus buffer in Buffered mode, and as an input for deciding whether the MSM82C59A-2 is to be master (SP/EN = 1) or slave (SP/EN =0) during Non-buffered mode.

When an interrupt request is made to the MSM82C59A-2, the INT output is switched to high level, and INT interrupt is sent to the CPU.

When this pin is at low level, the CALL instruction code or the interrupt vector data is enabled onto the data bus. When the CPU acknowledges the INT interrupt, INTA is sent to the MSM82C59A-2. (Interrupt acknowledge sequence).

These interrupt request input pins for the MSM82C59A-2 can be set to edge trigger mode or level trigger mode ( by ICW1). In edge trigger mode, interrupt request is executed by the rising edge of the IR input

7

Request

Input

and holds it until that input is acknowledged by the CPU. In level trigger mode, interrupt requests are executed by high level IR inputs and holds them until that input is acknowledged by the CPU. These pins have a pull up resistor.

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¡ Semiconductor MSM82C59A-2RS/GS/JS

SYSTEM INTERFACE

Address Bus

Control Bus

Data Bus

8 bits

Cascade

Address Bus

A

CS RD INT

CAS

0

CAS

1

CAS

2

D

- D

0

7

0

MSM82C59A-2

SP/EN IR0IR1IR2IR3IR4IR5IR6IR

Slave

Program/Enable

Buffer

Interrupt Requests

WR INTA

7

BASIC OPERATION DESCRIPTION

Data transfers between the 82C59A-2 internal registers and the data bus are listed below.

A

D

0

1

¥

0 0

0

1

¥

D

4

0 0

1

RD

3

¥

0 1

¥

WR

0

1 1

1

¥

0

CS

1

0 0

0

0 1

¥

0

IRR, ISR, or Poll Word Æ Data Bus

0

IMR Æ Data bus

Data Bus Æ OCW2

0 0

Data Bus Æ OCW3

0

Data Bus Æ 1CW1

0

Data Bus Æ OCW1, ICW2, ICW3, ICW4

0

Data Bus Set to High Impedance (when INTA = 1)

1

¥

Combinations Prohibited

Function

Opearation

Read

Write

—

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OKI MSM82C59A-2JS, MSM82C59A-2RS, MSM82C59A-2GS-K Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual