OKI MSM80C86A-10RS, MSM80C86A-10GS-K, MSM80C86A-10JS Datasheet

E2O0010-27-X2

¡ Semiconductor MSM80C86A-10RS/GS/JS

¡ Semiconductor

This version: Jan. 1998

Previous version: Aug. 1996

MSM80C86A-10RS/GS/JS

16-Bit CMOS MICROPROCESSOR

GENERAL DESCRIPTION

The MSM80C86A-10 is complete 16-bit CPUs implemented in Silicon Gate CMOS technology. They are designed with same processing speed as the NMOS 8086-1 but have considerably less power consumption. It is directly compatible with MSM80C88A-10 software and MSM80C85AH hardware and peripherals.

FEATURES

• 1 Mbyte Direct Addressable Memory Space

• Internal 14-word by 16-bit Register Set

• 24-Operand Addressing Modes

• Bit, Byte, Word and String Operations

• 8 and 16-bit Signed and Unsigned Arithmetic Operation

• From DC to 10 MHz Clock Rate (Note)

• Low Power Dissipation 10 mA/MHz

• Bus Hold Circuitry Eliminated Pull-up Resistors

• 40-pin Plastic DIP (DIP40-P-600-2.54): (Product name: MSM80C86A-10RS)

• 44-pin Plastic QFJ (QFJ44-P-S650-1.27): (Product name: MSM80C86A-10JS)

• 56-pin Plastic QFP (QFP56-P-1519-1.00-K): (Product name: MSM80C86A-10GS-K)

(Note) 10 MHz Spec is not compatible with Intel 8086-1 Spec.

1/37

¡ Semiconductor MSM80C86A-10RS/GS/JS

CIRCUIT CONFIGURATION

Exeuction Unit

Register File

Data

Pointer

and

Index

Registers

(8 Words)

16-Bit ALU

Flags

Bus Interface Unit

Relocation

Register File

Segment

Registers

and

Instruction

Pointer

(5 Words)

Bus

Interface

Unit

BHE/S

7

A

19/S6

.

4

16

4

.

A16/S

3

AD15 - AD

INTA, RD, WR, M/IO

0

TEST

INTR

RQ/GT

HOLD HLDA

NMI

0, 1

3

DT/R, DEN, ALE

6Byte

Instruction

Queue

LOCK

2

Control & Timing

MN/MXREADYRESETCLK

3

GND

V

2

3

CC

, QS

QS

0

S2, S1, S

1

0

2/37

¡ Semiconductor MSM80C86A-10RS/GS/JS

PIN CONFIGURATION (TOP VIEW)

40 pin Plastic DIP

AD

AD AD AD AD

AD AD AD AD AD AD

NC

NC NC

1

GND

2

AD

14

3

AD

13

4

AD

12

5

AD

11

6

AD

10

7

AD

9

8

AD

8

9

AD

7

10

AD

6

11

AD

5

12

AD

4

13

AD

3

14

AD

2

15

AD

19/S6

(M/IO)

2

(DT/R)

1

(DEN)

0

AD

NMI

INTR

CLK

GND

7

(HOLD)

0

1

16

0

17 18 19 20

56 pin Plastic QFP

3

4

5

/S

11

12

13

AD 56

AD 55

AD 54

AD

14

53

52NC51

GND50NC49V

CC

15

CC

V

AD

48

47NC46

1 2

10

3

9

4

8

5

7

6

7 8 9

5

10

4

11

3

12

2

13

1

14

0

/S

16

17

18

A

45

44

43

NC

42

A

41

BHE/S

40

MN/MX

39

RD

38

RQ/GT

37

NC

36

NC

35

NC

34 33

RQ/GT1(HLDA)

32

LOCK(WR)

31

S

30

S

29

S

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

V

CC

AD

15

A16/S

3

A17/S

4

A18/S

5

A19/S

6

BHE/S

7

MN/MX

RD

(HOLD)

RQ/GT

0

(HLDA)

RQ/GT

1

LOCK(WR)

(M/IO)

S

2

(DT/R)

S

1

(DEN)

S

0

(ALE)

QS

0

(INTA)

QS

1

TEST

READY RESET

15

NMI

16

INTR

17

CLK

18NC19NC20

GND

21

CC

V

22NC23NC24

25

RESET

READY

26

TEST

27

(INTA) QS

28

(ALE)

0

1

QS

7

AD

10

AD

8

9

AD

9

8

AD

10

7

AD

11

6

AD

12

5

AD

13

4

14

AD

3

15

AD

2

16

AD

1

AD

17 S

0

44 pin Plastic QFJ

11AD12AD13AD14

AD 6

5

4

3

18192021222324

NC

NM1

INTR

CLK

GND

2

GND

NC 1

NC

V

CC

AD

43

44

252627

RESET

3

/S

15

16

A

424140

READY

TEST

4

/S

17

A

)

INTA(QS

1

5

/S

18

A

28

)

0

ALE(QS

39

NC

38

A BHE/S

37

MN/MX

36

RD

35

RQ/GT

34

RQ/GT

33 32

LOCK(WR)

31

S S

30 29

19/S6

(M/IO)

2

(DT/R)

1

(DEN)

0

7

(HOLD)

0

(HLDA)

1

3/37

¡ Semiconductor MSM80C86A-10RS/GS/JS

ABSOLUTE MAXIMUM RATINGS

Rating

CC

IN

D

Conditions

With respect

to GND

—

Ta = 25°C

MSM80C86A-10RS

1.0

MSM80C86A-10GS

–0.5 to + 7 –0.5 to V –0.5 to V

CC

+0.5 +0.5

–65 to +150

MSM80C86A-10JS

0.7

Parameter Unit

Power Supply Voltage Input Voltage Output Voltage Storage Temperature Power Dissipation

Symbol

V

OUT

T

STG

P

OPERATING RANGE

Parameter UnitSymbol

Power Supply Voltage Operating Temperature

V

CC

T

op

Range

4.75 to 5.25 0 to +70

RECOMMENDED OPERATING CONDITIONS

Parameter UnitSymbol

Power Supply Voltage Operating Temperature "L" Input Voltage V

"H" Input Voltage

V

CC

T

OP

IL

*1 —

V

IH

*2 —2.0 V

Min.

V

CC

4.75 0

–0.5

–0.8

Typ.

5.0 V

+25

—

Max.

5.25 +70

+0.8

V

CC

+0.5 +0.5

V V V

°C

W

V

°C

V V V

*1 Only CLK *2 Except CLK

4/37

¡ Semiconductor MSM80C86A-10RS/GS/JS

DC CHARACTERISTICS

(VCC = 4.5 to 5.5 V, Ta = –40°C to +85°C)

Parameter UnitSymbol Min.

"L" Output Voltage V

"H" Output Voltage V

Input Leak Current I Output Leak Current I Input Leakage Current

(Bus Hold Low) Input Leakage Current

(Bus Hold High) Bus Hold Low Overdrive Bus Hold High Overdrive

I I

Operating Power Supply Current

Standby Power Supply Current

OL

OH

LI

LO

I

BHL

I

BHH

BHLO

BHHO

I

CC

I

CCS

V

—

3.0

CC

–1.0

–10

—

Typ.

—

–0.4

—

Max.

0.4

V

——V

+1.0

+10

400

–400

600

–600

10

500

mA mA

mA50

mA–50

mA— mA—

mA/MHz

mA

Conditions

= 2.5 mA

I

OL

I

= –2.5 mA

OH

I

= –100 mA

OH

0 £ V

VO = V

V

IN

V

IN

V

IL

V

IH

V

CC

Outputs Unloaded

V

= V

IN

£ V

IN

or GND

CC

= 0.8 V

*3

= 3.0 V

*4

*5 *6

= GND

= VCC

= 5.5 V

or GND

CC

Input Capacitance C Output Capacitance C I/O Capacitance C

IN

OUT

I/O

— —

—

10 15 20

pF pF pF

*7 *7 *7—

*3 Test condition is to lower VIN to GND and then raise VIN to 0.8 V on pins 2-16, and 35-39. *4 Test condition is to raise VIN to VCC and then lower VIN to 3.0 V on pins 2-16, 26-32, and 34-

39. *5 An external driver must source at least I *6 An external driver must sink at least I

BHHO

to switch this node from LOW to HIGH.

BHLO

to switch this node from HIGH to LOW.

*7 Test Conditions: a) Freq = 1 MHz.

b) Unmeasured Pins at GND. c) VIN at 5.0 V or GND.

5/37

¡ Semiconductor MSM80C86A-10RS/GS/JS

AC CHARACTERISTICS

Minimum Mode System Timing Requirements

Parameter

CLK Cycle Period CLK Low Time CLK High Time

CLK Rise Time (From 1.0 V to 3.5 V)

CLK Fall Time (From 3.5 V to 1.0 V)

Data in Setup Time Data in Hold Time RDY Setup Time into

MSM 82C84A-2 (See Notes 1, 2) RDY Hold Time into MSM 82C84A-2

(See Notes 1, 2) READY Setup Time into

MSM80C86A-2 READY Hold Time into MSM80C86A-10 READY inactive to CLK

(See Note 3) HOLD Setup Time INTR, NMI, TEST Setup Time

(See Note 2) Input Rise Time (Except CLK)

(From 0.8 V to 2.0 V) Input Fall Time (Except CLK)

(From 2.0 V to 0.8 V)

Symbol

t

CLCL

t

CLCH

t

CHCL

t

CH1CH2

t

CL2CL1

t

DVCL

t

CLDX

t

R1VCL

t

CLR1X

t

RYHCH

t

CHRYX

t

RYLCL

t

HVCH

t

INVCH

t

ILIH

t

IHIL

5 MHz Spec. V

= 4.5 V to 5.5 V

CC

Ta = –40 to +85°C

Min.

200 118

69 —

—

30 10

35

0

118

30

–8

35 30

—

Max.

DC

— —

10

— —

—

— —

15

8 MHz Spec. V

= 4.75 V to 5.25 V

CC

Ta = 0 to +70°C

Max.Min.

125 DC

68 — 44 —

20 — 10 —

68 —

20 —

10 MHz Spec. V

= 4.75 V to 5.25 V

CC

Ta = 0 to +70°C

Max.Min.

100 DC ns

46 — ns 44 — ns

—10ns—10

20 — ns 10 — ns

35 — ns35 —

0—ns0—

46 — ns

20 — ns

–8 — ns–8 —

20 — ns20 — 15 — ns15 —

—15ns—15

Unit

6/37

¡ Semiconductor MSM80C86A-10RS/GS/JS

Timing Responses

Parameter

Address Valid Delay Address Hold Time Address Float Delay ALE Width ALE Active Delay ALE Inactive Delay Address Hold Time to ALE Inactive Data Valid Delay Data Hold Time Data Hold Time after WR Control Active Delay 1 Control Active Delay 2 Control Inactive Delay Address Float to RD Active

RD Active Delay RD Inactive Delay RD Inactive to Next Address Active

HLDA Valid Delay

RD Width WR Width

Address Valid to ALE Low Ouput Rise Time (From 0.8 V to 2.0 V) Output Fall Time (From 2.0 V to 0.8 V)

Symbol

t

CLAV

t

CLAX

t

CLAZ

t

LHLL

t

CLLH

t

CHLL

t

LLAX

t

CLDV

t

CHDX

t

WHDX

t

CVCTV

t

CHCTV

t

CVCTX

t

AZRL

t

CLRL

t

CLRH

t

RHAV

t

CLHAV

t

RLRH

t

WLWH

t

AVAL

t

OLOH

t

OHOL

5 MHz Spec. V

= 4.5 V to 5.5 V

CC

Ta = -40 to +85°C

Min.

10 10

t

CLAX

t

CLCH

— —

t

CLCH

10 10

t

CLCH

10 10 10

0

10

t

CLC

10

2t

CLCL

2t

CLCL

t

CLCH

— —

-20

-10

-30

-45

-60

-75

Max.

110

— 80 — 80 85 —

110

—

— 110 110 110

— 165

150

—

160

— — — 15 15

8 MHz Spec. V

= 4.75 V to 5.25 V

CC

Ta = 0 to +70°C

Max.Min.

10 60 10 —

t

CLAX

-10 —

CLCH

-10 —

CLCH

-30 —

CLCH

10 80

t

-40 —

CLCH

10 100

-50 —

CLCL

-40 —

CLCL

-40 —

CLCH

10 MHz Spec. V Ta = 0 to +70°C

50

= 4.75 V to 5.25 V

CC

Max.Min.

10 60 ns 10 — ns

t

CLCH

CLAX

-10 — nst

50 ns

—40ns—50 —45ns—55

t

CLCH

-10

—nst 10 60 ns10 60 10 — ns10 —

t

-25 — nst

CLCH

10 55 ns10 70 10 50 ns10 60 10 55 ns10 70

0—ns0—

10 70 ns10 100

10 60 ns

t

-35 — ns

CLCL

10 60 ns

2t

-40 — ns2t

CLCL

2t

-35 — ns2t

CLCL

t

-35 — nst

CLCH

—15ns—15

Unit

Notes: 1. Signal at MSM82C84A-2 or MSM82C88-2 are shown for reference only.

2. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.

3. Applies only to T2 state. (8 ns into T3)

7/37

¡ Semiconductor MSM80C86A-10RS/GS/JS

Maximum Mode System (Using MSM82C88-2 Bus Controller)

Timing Requirements

Parameter

CLK Cycle Period CLK Low Time CLK High Time

CLK Rise Time (From 1.0 V to 3.5 V)

CLK Fall Time (From 3.5 V to 1.0 V)

Data in Setup Time Data in Hold Time RDY Setup Time into

MSM 82C84A-2 (See Notes 1, 2) RDY Hold Time into MSM 82C84A-2

(See Notes 1, 2) READY Setup Time into

MSM80C86A-10 READY Hold Time into MSM80C86A-10 READY inactive to CLK

(See Note 3) Setup Time for Recognition (NMI,

INTR, TEST) (See Note 2)

RQ/GT Setup Time RQ Hold Time into MSM80C86A-10

Input Rise Time (Except CLK) (From 0.8 V to 2.0 V)

Input Fall Time (Except CLK) (From 2.0 V to 0.8 V)

Symbol

t

CLCL

t

CLCH

t

CHCL

t

CH1CH2

t

CL2CL1

t

DVCL

t

CLDX

t

R1VCL

t

CLR1X

t

RYHCH

t

CHRYX

t

RYLCL

t

INVCH

t

GVCH

t

CHGX

t

ILIH

t

IHIL

5 MHz Spec. V

= 4.5 V to 5.5 V

CC

Ta = –40 to +85°C

Min.

200 118

69 —

—

30 10

35

0

118

30

–8

30

30 40

—

Max.

DC

— —

10

— —

—

— —

15

8 MHz Spec. V

= 4.75 V to 5.25 V

CC

Ta = 0 to +70°C

Max.Min.

125 DC

68 — 44 —

20 — 10 —

68 —

20 —

10 MHz Spec. V

= 4.75 V to 5.25 V

CC

Ta = 0 to +70°C

Max.Min.

100 DC ns

46 — ns 44 — ns

—10ns—10

20 — ns 10 — ns

35 — ns35 —

0—ns0—

46 — ns

20 — ns

–8 — ns–8 —

15 — ns15 —

15 — ns15 — 20 — ns30 —

—15ns—15

Unit

8/37

¡ Semiconductor MSM80C86A-10RS/GS/JS

Timing Responses

50

—

10 MHz Spec.

= 4.75 V to 5.25 V

V

CC

Ta = 0 to +70°C

Unit

Max.Min.

535ns 545ns

—45ns

10 45 ns10 60 10 60 ns10 70 10 60 ns10 60 10 — ns10 —

t

CLAX

50 nst —25ns—25 —30ns—30 —25ns—25 —25ns—25

425ns425 10 60 ns10 60 10 — ns10 —

545ns

0—ns0— 10 70 ns10 100 10 60 ns10 80

t

CLCL

-35

—nst

—50ns—50

—30ns—30

045ns050

2t

-40

CLCL

—ns2t —15ns—15 —15ns—15

5 MHz Spec.

= 4.5 V to 5.5 V

V

Timing Response

Symbol

Parameter

Command Active Delay (See Note 1) Command Inactive Delay (See Note 1) READY Active to Status Passive

(See Note 4) Status Active Delay Status Inactive Delay Address Valid Delay Address Hold Time Address Float Delay Status Valid to ALE High (See Note 1) Status Valid to MCE High (See Note 1) CLK Low to ALE Valid (See Note 1) CLK Low to MCE High (See Note 1) ALE Inactive Delay (See Note 1) Data Valid Delay Data Hold Time Control Active Delay (See Note 1) 5 45 ns Control Inactive Delay (See Note 1) Address Float to RD Active

RD Active Delay RD Inactive Delay RD Inactive to Next Address Active

Direction Control Active Delay (See Note 1)

Direction Control Inactive Delay (See Note 1)

GT Active Delay (See Note 5) GT Inactive Delay RD Width

Output Rise Time (From 0.8 V to 2.0 V) Output Fall Time (From 2.0 V to 0.8 V)

t

CLML

t

CLMH

t

RYHSH

t

CHSV

t

CLSH

t

CLAV

t

CLAX

t

CLAZ

t

SVLH

t

SVMCH

t

CLLH

t

CLMCH

t

CHLL

t

CLDV

t

CHDX

t

CVNV

t

CVNX

t

AZRL

t

CLRL

t

CLRH

t

RHAV

t

CHDTL

t

CHDTH

t

CLGL

t

CLGH

t

RLRH

t

OLOH

t

OHOL

CC

Ta = –40 to +85°C

Min.

Max.

5 5

—

10 10 10

110

110 130 110

10

t

CLAX

— — — —

4

10

110

10

5 5

0

t

CLCL

10 10

165 150

-45

—

0 0

2t

-75

CLCL

— —

8 MHz Spec. V

CC

Ta = 0 to +70°C

45 45

— 80 35 35 35 35 35

— 45 45

—

CLCL

50

35

85 85 — 15 15

= 4.75 V to 5.25 V

Max.Min.

535 545

—65

CLAX

545 545

-40

-50

CLCL

Notes: 1. Signals at MSM82C84A-2 or MSM82C88-2 are shown for reference only.

2. Setup requirement for asynchronous signal only to guarantee recognition at next CLK

3. Applies only to T2 state (8 ns into T3)

4. Applies only to T3 and wait states.

5. CL = 40 pF (RQ/GT0, RQ/GT1)

9/37

¡ Semiconductor MSM80C86A-10RS/GS/JS

TIMING DIAGRAM

Input/Output A.C. Testing Load Circuit

2.4

1.5

Test Points

0.45

AC, Testing: Inputs are driven at 2.4 V for a logic "1" and 0.45 V for a logic "0". Timing measurements are 1.5 V for both a logic "1" and "0".

Minimum Mode

CLK (MSM82C84A-2 Output)

BHE/S

, A19/S6 - A16/S

7

RDY (MSM82C84A-2 Input)

See NOTE 5

M/IO

3

ALE

Device

1.5

Under

Test

CL = 100 pF

C

includes jig capacitance.

L

t

CHDX

T

4

t

CLCH

T

1

t

CLCL

V

IH

V

IL

t

CHCTV

t

CLAV

t

CLLH

t

CHLL

t

CLAX

BHE, A

t

LHLL

t

AVAL

19

- A

T

2

t

CH1CH2tCL2CL1

t

CHCL

t

CLDV

16

t

LLAX

V

IH

V

IL

t

RYLCL

t

R1VCL

T

3

S7 - S

t

CLR1X

Tw

3

(MSM80C86A-10 Input)

Read Cycle

(NOTE 1)

(WR, INTA = V

OH

READY

)

AD

15

- AD

RD

DT/R

DEN

t

CHRYX

t

AVAL

t

LLAX

t

CLAV

AD

t

AZRL

15

- AD

0

t

CHCTV

0

t

CLRL

t

CVCTV

t

RYHCH

t

CLAZ

t

CLAX

Float

t

RLRH

t

DVCL

t

CLRH

t

CVCTX

Data In

t

CLDX

Float

t

RHAV

t

CHCTV

10/37

¡ Semiconductor MSM80C86A-10RS/GS/JS

Minimum Mode (continued)

CLK (MSM82C84A-2 Output)

BHE/S

, A19/S6 - A16/S

7

Write Cycle

AD

(NOTE 1) (RD, INTA DT/R = V

OH

)

INTA Cycle

AD

(NOTES 1&3)

OL

OH

)

(RD, WR = V BHE = V

15

V

M/IO

ALE

- AD

DEN

WR

- AD

DT/R

INTA

T

1

t

CLCL

IH

IL

t

CHCTV

t

CLAV

3

t

CLLH

t

CLAV

0

BHE, A19 - A

t

CHLL

t

CVCTV

t

CHCTV

LHLL

AVAL

AD15 - AD

t

CVCTV

t

CLAZ

t

CVCTV

t

LLAX

t

0

t

CVCTV

t

CH1CH2

t

CHCL

16

AVAL

Float

T

t

CLDV

t

CLAX

2

CLDV

CLAX

LLAX

Data Out

t

WLWH

t

DVCL

T

3

t

CL2CL1

S7 - S

t

CVCTX

t

CVCTX

3

t

Pointer

T

W

WIDX

t

CHDX

t

CHDX

T

t

CLDX

4

t

CLCH

Float

t

CHCTV

t

CVCTX

Software Halt RD, WR, INTA = V

OH

DT/R = Indeterminate

DEN

AD15 - AD

t

0

CLAV

Invalid Address

Software Halt

11/37

¡ Semiconductor MSM80C86A-10RS/GS/JS

Maximum Mode

CLK (MSM82C84A-2 Output)

QS0, QS

S2, S1, S0 (Except Halt)

BHE/S7, A19/S6 - A16/S

ALE See NOTE 5

(MSM82C88-2 Output)

RDY

(MSM82C84A-2 Input)

READY (MSM80C86A-10 Input)

Read Cycle

AD

15

V

- AD

RD

DT/R

T

1

t

CLAX

t

CLAZ

A

15

CH1CH2

- A

19

- AD t

AZRL

t

CLCL

IH

V

t

IL

CLAV

1

t

CHSV

t

CLAV

3

t

SVLH

t

CLLH

t

CLAV

0

t

CHDTL

BHE

AD

t

CHCL

16

t

CHLL

V V

0

t

CLRL

IH

IL

T

t

CLDV

t

RYLCL

t

RYHSH

t

Float

2

t

CLAX

RYHCH

t

CL2CL1

t

R1VCL

t

RLRH

T

3

t

CLSH

S7 - S

t

CLR1X

t

DVCL

Data In

T

w

(See NOTE 8)

t

CHDX

3

t

CLRH

t

CLCH

t

CHRYX

CLDX

T

4

Float

t

RHAV

t

CHDTH

MSM82C88-2

Outputs

(See NOTES 5, 6)

MRDC or

IORC

DEN

t

CLML

t

CVNV

t

CLMH

t

CVNX

12/37