OKI MSM80C85AHGS-2K, MSM80C85AHJS, MSM80C85AHRS Datasheet

E2O0009-27-X2

¡ Semiconductor MSM80C85AHRS/GS/JS

¡ Semiconductor

This version: Jan. 1998

Previous version: Aug. 1996

MSM80C85AHRS/GS/JS

8-Bit CMOS MICROPROCESSOR

GENRAL DESCRIPTION

The MSM80C85AH is a complete 8-bit parallel; central processor implemented in silicon gate C-MOS technology and compatible with MSM80C85A. It is designed with higher processing speed (max.5 MHz) and lower power consumption compared with MSM80C85A and power down mode is provided, thereby offering a high level of system integration. The MSM80C85AH uses a multiplexed address/data bus. The address is split between the 8bit address bus and the 8-bit data bus. The on-chip address latch : of a MSM81C55-5 memory product allows a direct interface with the MSM80C85AH.

FEATURES

• Power down mode (HALT-HOLD)

• Low Power Dissipation: 50mW(Typ)

• Single + 3 to + 6 V Power Supply

• –40 to + 85°C, Operating Temperature

• Compatible with MSM80C85A

• 0.8 ms instruction Cycle (VCC = 5V)

• On-Chip Clock Generator (with External Crystal)

• On-Chip System Controller; Advanced Cycle Status Information Available for Large System Control

• Bug operation in MSM80C85AH is fixed

• Four Vectored interrupt (One is non-maskable) Plus the 8080A-compatible interrupt.

• Serial, In/Serial Out Port

• Decimal, Binary and Double Precision Arithmetic

• Addressing Capability to 64K Bytes of Memory

• TTL Compatible

• 40-pin Plastic DIP(DIP40-P-600-2.54): (Product name: MSM80C85AHRS)

• 44-pin Plastic QFJ(QFJ44-P-S650-1.27): (Product name: MSM80C85AHJS)

• 44-pin Plastic QFP(QFP44-P-910-0.80-2K): (Product name: MSM80C85AHGS-2K)

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¡ Semiconductor MSM80C85AHRS/GS/JS

FUNCTIONAL BLOCK DIAGRAM

RST

INTR INTA 5.5 6.5 7.5 TRAP SID SOD

Interrupt Control Serial I/O Control

8-Bit Internal Data Bus

Accumulator

(8)

Power Supply

Power Down

CLK GEN

CLK OUT

Temporary Register

(8)

+5V GND

Control Status DMA Reset

READY RD WR ALE S0 S1 IO / M HOLD HLDA RESET IN RESET OUT

Flag (5)

Flip Flops

Arithmetic Logic Unit

ALU(8)

Timing And Control

Instruction Register (8)

Instruction

Decoder

And

Machine

Cycle

Encoding

B REG (8)

D REG (8)

H REG (8)

Stack Pointer (16)

Program Counter (16)

Incrementer/Decrementer

Address Latch (16)

Address Buffer (8)

Address Bus

C REG (8)

E REG (8)

C REG (8)

- A

Data/Address

Buffer (8)

- AD

Address/Data Bus

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¡ Semiconductor MSM80C85AHRS/GS/JS

PIN CONFIGURATION (TOP VIEW)

40 pin Plastic DIP

44 pin Plastic QFP

SOD

2X1

RESET OUT

SID 4443424140

TRAP

RST7.5

RST6.5

RST5.5

INTR

INTA

11 A

NC 39

HOLD

HLDA

CLK(OUT)

363534

RESET IN

33 32 31 30 29 28 27

26 25 24 23

READY IO/M S

RD WR

ALE S

RESET OUT

SOD

SID

TRAP RST7.5 RST6.5 RST5.5

INTR

INTA

AD AD AD AD AD AD AD AD

GND

3 4 5 6 7 8

9 10 11 12

44 pin Plastic QFJ

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

HOLD HLDA CLK(OUT)

RESET IN

READY IO/M S

RD WR

ALE S

12131415161718

4AD5AD6AD7

GND

192021

A10A

SID

SOD

RESET OUT

X2X1NC

TRAP

RST7.5

RST6.5

RST5.5

INTR

INTA

13 14

17 A

18192021222324

5AD6AD7

HOLD

HLDA

CLK(OUT)

RESET IN

424140

READY

IO/M

ALE

33 32

262728

GND

A10A11A

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¡ Semiconductor MSM80C85AHRS/GS/JS

MSM80C85AH FUNCTIONAL PIN DEFINITION

The following describes the function of each pin:

Symbol Function

- A

(Output, 3-state) A0 - A

(Input/Output) 3-state

ALE (Output)

, S1 , IO/M

(Output)

(Output, 3-state)

READY (Input)

HOLD (Input)

HLDA (Output)

INTR (Output)

INTA

(Output) RST 5.5

RST 6.5 RST 7.5 (Input)

TRAP (Input)

Address Bus: The most significant 8-bits of the memory address or the 8-bits of the I/O address, 3-stated during Hold and Halt modes and during RESET.

Multiplexed Address/Data Bus: Lower 8-bits of the memory address (or I/O address) appear on the bus during the first clock cycle (T state) of a machine cycle. It then becomes the data bus during the second and third clock cycles.

Address Latch Enable: It occurs during the first clock state of a machine cycle and enables address to get latched into the on-chip latch peripherals. The falling edge of ALE is set to guarantee setup and hold times for the address information. The falling edge ALE can also be used to strobe the status information ALE is never 3-state.

Machine cycle status:

S0 States

IO/M S

Memory write

Memory read

I/O write

I/O read

Opcode fetch

can be used as an advanced R/W status. IO/M, S

IO/M S

S0 States

Interrupt Acknowledge

Halt = 3-state

Hold (high impedance)

Reset ¥ = unspecified

¥

and S1 become valid at the beginning of

a machine cycle and remain stable throughout the cycle. The falling edge of ALE may be used to latch the state of these lines.

READ control: A low level on RD indicates the selected memory or I/O device is to be read that the Data Bus is available for the data transfer, 3-stated during Hold and Halt modes and during RESET.

WRITE control: A low level on WR indicates the data on the Data Bus is to be written into the selected memory or I/O location. Data is set up at the trailing edge of WR, 3-stated during Hold and Halt modes and during RESET.

If READY is high during a read or write cycle, it indicates that the memory or peripheral is ready to send or receive data. If READY is low, the cpu will wait an integral number of clock cycles for READY to go high before completing the read or write cycle READY must conform to specified setup and hold times.

HOLD indicates that another master is requesting the use of the address and data buses. The cpu, upon receiving the hold request, will relinquish the use of the bus as soon as the completion of the current bus transfer. Internal processing can continue. The processor can regain the bus only after the HOLD is removed. When the HOLD is acknowledged, the Address, Data, RD, WR, and IO/M lines are 3-stated. And status of power down is controlled by HOLD.

HOLD ACKNOWLEDGE: Indicates that the cpu has received the HOLD request and that it will relinquish the bus in the next clock cycle. HLDA goes low after the Hold request is removed. The cpu takes the bus one half clock cycle after HLDA goes low.

INTERRUPT REQUEST: Is used as a general purpose interrupt. It is sampled on during the next to the last clock cycle of an instruction and during Hold and Halt states. If it is active, the Program Counter (PC) will be inhibited from incrementing and an INTA will be issued. During this cycle a RESTART or CALL instruction can be inserted to jump to the interrupt service routine. The INTR is enabled and disabled by software. It is disabled by Reset and immediately after an interrupt is accepted. Power down mode is reset by INTR.

INTERRUPT ACKNOWLEDGE: Is used instead of (and has the same timing as) RD during the instruction cycle after an INTR is accepted.

RESTART INTERRUPTS: These three inputs have the same timing as INTR except they cause an internal RESTART to be automatically inserted. The priority of these interrupts is ordered as shown in Table 1. These interrupts have a higher priority than INTR. In addition, they may be individually masked out using the SIM instruction. Power down mode is reset by these interrupts.

Trap interrupt is a nonmaskable RESTART interrupt. It is recognized at the same timing as INTR or RST 5.5 - 7.5. It is unaffected by any mask or Interrupt Disable. It has the highest priority of any interrupt. (See Table 1.) Power down mode is reset by input of TRAP.

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Symbol Function

Sets the Program Counter to zero and resets the Interrupt Enable and HLDA flip-flops and release

power down mode. The data and address buses and the control lines are 3-stated during RESET and RESET IN (Input)

RESET OUT (Output)

, X

(Input)

CLK (Output)

SID (Input)

SOD (Output)

GND Ground Reference.

because of the asynchronous nature of RESET IN, the processor's internal registers and flags may be

altered by RESET with unpredictable results. RESET IN is a Schmitt-triggered input, allowing

connection to an R-C network for power-on RESET delay. The cpu is held in the reset condition as

long as RESET IN is applied.

Indicated cpu is being reset. Can be used as a system reset. The signal is synchronized to

the processor clock and lasts an integral number of clock periods.

and X2 are connected to a crystal to drive the internal clock generator. X1 can also be an external

clock input from a logic gate. The input frequency is divided by 2 to give the processor's internal

operating frequency.

Clock Output for use as a system clock. The period of CLK is twice the X1, X2 input period.

Serial input data line. The data on this line is loaded into accumulator bit 7 whenever a RIM instruction

is executed.

Serial output data line. The output SOD is set or reset as specified by the SIM instruction.

+ 5 Volt supply

Name

TRAP RST 7.5

RST 6.5 RST 5.5

INTR

Table 1 Interrupt Priority, Restart Address, and Sensitivity

Priority

Address Branched To (1)

When Interrupt Occurs

1 24H 2 3 4 5

3CH

34H

2CH

(2)

Rising edge and high level unit sampled. Rising edge (latched). High level unitl sampled. High level until sampled. High level until sampled.

Type Trigger

Notes: (1) The processor pushes the PC on the stack before branching to the indicated

address.

(2) The address branched to depends on the instruction provided to the cpu

when the interrupt is acknowledged.

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¡ Semiconductor MSM80C85AHRS/GS/JS

FUNCTIONAL DESCRIPTION

The MSM80C85AH is a complete 8-bit parallel central processor. It is designed with silicon gate C-MOS technology and requires a single +5 volt supply. Its basic clock speed is 5 MHz, thus improving on the present MSM80C85A's performance with higher system speed and power down mode. Also it is designed to fit into a minimum system of two IC's: The CPU (MSM80C85AH), and a RAM/IO (MSM81C55-5)

The MSM80C85AH has twelve addressable 8-bit register pairs. Six others can be used interchangeably as 8-bit registers or 16-bit register pairs. The MSM80C85AH register set is as follows:

Mnemonic

ACC or A PC BC, DE, HL

SP Flags or F

Accumulator Program Counter General-Purpose Registers; data pointer (HL) Stack Pointer Flag Register

8-bits 16-bit address 8-bit ¥ 6 or 16-bits ¥ 3 16-bit address 5 flags (8-bit space)

Contents

The MSM80C85AH uses a multiplexed Data Bus. The address is spilt between the higher 8-bit Address Bus and the lower 8-bit Address/Data Bus. During the first T state (clock cycle) of a machine cycle the low order address is sent out on the Address/Data Bus. These lower 8-bits may be latched externally by the Address Latch Enable signal (ALE). During the rest of the machine cycle the data bus is used for mamory or I/O data.

The MSM80C85AH provides RD, WR, S0, S1, and IO/M signals for bus control. An Interrupt Acknowledge signal (INTA) is also provided. Hold and all Interrupts are synchronized with the processor's internal clock. The MSM80C85AH also provides Serial Input Data (SID) and Serial Output Data (SOD) lines for a simple serial interface. In addition to these features, the MSM80C85AH has three maskable, vector interrupt pins, one nonmaskable TRAP interrupt and power down mode with HALT and HOLD.

INTERRUPT AND SERIAL I/O

The MSM80C85AH has 5 interrupt inputs: INTR, RST 5.5 RST 6.5, RST 7.5, and TRAP. INTR is identical in function to the 8080A INT. Each of the three RESTART inputs, 5.5, 6.5, and 7.5, has a programmable mask. TRAP is also a RESTART interrupt but it is nonmaskable.

The three maskable interrupts cause the internal execution of RESTART ( saving the program counter in the stack branching to the RESTART address) it the interrupts are enable and if the interrupt mask is not set. The nonmaskable TRAP causes the internal execution of a RESTART vector independent of the state of the interrupt enable or masks. (See Table 1.)

There are two different types of inputs in the restart interrupt. RST 5.5 and RST 6.5 are high level-sensitive like INTR (and INT on the 8080A) and are recognized with the same timing as INTR. RST 7.5 is rising edge-sensitive.

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For RST 7.5, only a pulse is required to set an internal flip-flop which generates the internal interrupt request. The RST 7.5 request flip-flop remains set until the request is serviced. Then it is reset automatically, This flip-flop may also be reset by using the SIM instruction or by issuing a RESET␣ IN to the MSM80C85AH. The RST 7.5 internal flip-flop will be set by a pulse on the RST 7.5 pin even when the RST 7.5 interrupt is masked out.

The interrupts are arranged in a flixed priority that determines which interrupt is to be recognized if more than one is pending, as follows: TRAP-highest priority, RST 7.5, RST 6.5, RST

5.5, INTR-lowest priority. This priority scheme does not take into account the priority of a routine that was started by a higher priority interrupt. RST 5.5 can interrupt an RST 7.5 routine if the interrupt are re-enabled before the end of the RST 7.5 routine.

The TRAP interrupt is useful for catastrophic evens such as power failure or bus error. The TRAP input is recognized just as any other interrupt but has the highest priority. It is not affected by any flag or mask. The TRAP input is both edge and level sensitive. The TRAP input must go high and remain high until it is acknowledged. It will not be recognized again until it goes low, then high again. This avoids any false triggering due to noise or logic glitches. Figure 3 illustrates the TRAP interrupt request circuitry within the MSM80C85AH. Note that the servicing of any interrupt (TRAP, RST 7.5, RST 6.5, RST 5.5,INTR) disables all future interrupts (except TRAPs) until an El instruction is executed.

The TRAP interrupt is special in that it disables interrupts, but preserves the previous interrupt enable status. Performing the first RIM instruction following a TRAP interrupt allows you to determine whether interrupts were enabled or disabled prior to the TRAP. All subsequent RIM instructions provide current interrupt enable status. Performing a RIM instruction following INTR or RST 5.5-7.5 will provide current interrupt Enable status, revealing that Interrupts are disabled.

The serial I/O system is also controlled by the RIM and SIM instructions. SID is read by RIM, and SIM sets the SOD data.

External TRAP Interrupt Request

RESET IN

Inside the MSM80C85AH

TRAP

RESET

Schmitt

Trigger

Internal

TRAP

Acknowledge

+5 V

CLK

F/F

Clear

TRAP F.F

TRAP

Interrupt

Request

ure 3 Trap and RESET IN Circuit

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¡ Semiconductor MSM80C85AHRS/GS/JS

DRIVING THE X1 AND X2 INPUTS

You may drive the clock inputs of the MSM80C85AH with a crystal, or an external clock source. The driving frequency must be at least 1 MHz, and must be twice the desired internal clock frequency; hence, the MSM80C85AH is operated with a 6 MHz crystal (for 3 MHz clock). If a crystal is used, it must have the following characteristics:

Parallel resonance at twice the clock frequency desired CL (load capacitance) £ 30 pF CS (shunt capacitance) £ 7 pF RS (equivalent shunt resistance) £ 75 ohms Drive level: 10 mW

Frequency tolerance: ± 0.05% (suggested)

Note the use of the capacitors between X1, X2 and ground. These capacitors are required to assure oscillator startup at the correct frequency. Figure 4 shows the recommended clock driver circuits. Note in B that a pull-up resistor is required to assure that the high level voltage of the input is at least 4 V. For driving frequencies up to and including 6 MHz you may supply the driving signal to X, and leave X2 open-circuited (Figure 4B). To prevent self-oscillation of the MSM80C85AH, be sure that X2 is not coupled back to X1 through the driving circuit.

A. Quartz Crystal Clock Driver

MSM80C85AH

= 15 pF

INT

33 pF Capacitor required for crystal frequency 10 to 6.25 MHz 50 pF Capacitor required for crystal frequency 6.25 to 4 MHz 100

F Capacitor required for crystal frequency <4 MHz

B. 1 - 10 MHz Input Frequency External Clock Drive Circuit

VIH > 0.8 V High time > 40 ns Low time > 40 ns

* X

Left Floating

Note: Since the constant values may vary depending on oscillator, consult the manufacturer

of the oscillator used when designing a circuit.

Figure 4 Clock Driver Circuits

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¡ Semiconductor MSM80C85AHRS/GS/JS

BASIC SYSTEM TIMING

The MSM80C85AH has a multiplexed Data Bus. ALE is used as a strobe to sample the lower 8-bits of address on the Data Bus. Figure 5 shows an instruction fetch, memory read and I/O write cycle (as would occur during processing of the OUT instruction). Note that during the I/ O write and read cycle that the I/O port address is copied on both the upper and lower half of the address.

There are seven possible types of machine cycles. Which of these seven takes place is defined by the status of the three status lines (IO/M, S1, S0) and the three control signals (RD, WR,and INTA). (See Table 2.) The status line can be used as advanced controls (for device selection, for example), since they become active at the T1 state, at the outset of each machine cycle. Control lines RD and WR become active later, at the time when the transfer of data is to take place, so are used as command lines.

A machine cycle normally consists of three T states, with the exception of OPCODE FETCH, which normally has either four or six T states (unless WAIT or HOLD states are forced by the receipt of READY or HOLD inputs). Any T state must be one of ten possible states, shown in Table 3.

Machine Cycle

Opcode Fetch Memory Read Memory Write

I/O Read I/O Write

Acknowledge of INTR Bus Idle

Table 2 MSM80C85AH Machine Cycle Chart

Status Control

(OF) (MR) (MW) (IOR) (IOW)

(INA) (BI): DAD

ACK. OF RST, TRAP HALT

IO/M S

0 O O

1 1 0 1 0

1 1

1 0

1 1 0

1 0

RD WR INTA

0 O 1 O 1

1 1

1 1 0 1 0

1 1

1 1 1 1 1 0 1

1 1

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