OKI MSM80C50-xxxRS, MSM80C49-xxxRS, MSM80C48-xxxRS, MSM80C40RS, MSM80C40GS-2K Datasheet

E2E1022-27-Y4

¡ Semiconductor MSM80C48/49/50, MSM80C35/39/40

¡ Semiconductor

This version: Jan. 1998

Previous version: Nov. 1996

MSM80C48/49/50
MSM80C35/39/40

CMOS 8-Bit Microcontroller

GENERAL DESCRIPTION

The OKI MSM80C48/MSM80C49/MSM80C50 are 8-bit, low-power, high-performance micro­controllers implemented in silicon-gate complementary metal-oxide semiconductor technology.
Integrated within these chips are 8K/16K/32K bits of mask program ROM, 512/1024/2048 bits
of data RAM, 27 I/O lines, built-in 8 bit timer/counter, and oscillator. Program memory and data
paths are byte wide. Eleven new instructions have been added to the NMOS version's instruction
set, thereby optimizing power down, port data transfer, decrement and port float functions.
Available in 40-pin plastic DIP (RS) or 44-pin plastic flat packages QFP (GSK).

FEATURES

• Lower power consumption enabled by CMOS silicon gate process

• Completely static operation

• Improved power-down feature

• Instruction cycle :

• 111 instructions

• All instructions are usable even during execution of external ROM instructions.

• Operation facility
Addition, logical operations, and decimal adjust

• Program memory (ROM) : 1K words ¥ 8 bits (MSM80C48)

• Data memory (RAM) : 64 words ¥ 8 bits (MSM80C48)

• Two sets of working registers

• External and timer interrupts

• Two test inputs

• Built-in 8-bit timer counter

• Extendable external memory and I/O ports

• I/O port
Input-output port : 2 ports ¥ 8 bits
Data bus input-output port : 1 port ¥ 8 bits

• Single-step execution function

• Wide range of operating voltage, from + 2.5 V to + 6 V of V

• High noise margin action

• Compatible with Intel's 8048, 8049 and 8050

• Package
40-pin plastic DIP (DIP40-P-600-2.54) : (MSM80C48-¥¥¥RS)

44-pin plastic QFP(QFP44-P-910-0.80-2K) : (MSM80C48-¥¥¥GS-2K)

1.36 ms (11 MHz) VCC=4.5 to 6.0 V (MSM80C48/49)

2.5 ms (6 MHz) VCC=3.5 to 6.0 V (MSM80C50)

: 2K words ¥ 8 bits (MSM80C49)
: 4K words ¥ 8 bits (MSM80C50)

: 128 words ¥ 8 bits (MSM80C49)
: 256 words ¥ 8 bits (MSM80C50)

CC

(MSM80C49-¥¥¥RS)
(MSM80C50-¥¥¥RS)
(MSM80C35RS)
(MSM80C39RS)
(MSM80C40RS)

(MSM80C49-¥¥¥GS-2K)
(MSM80C50-¥¥¥GS-2K)
(MSM80C35GS-2K)
(MSM80C39GS-2K)
(MSM80C40GS-2K)
¥¥¥ indicates the code number.

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¡ Semiconductor MSM80C48/49/50, MSM80C35/39/40

BLOCK DIAGRAM

(DATA

BUS

PORT)

(PORT 1)

PLA

INSTRUC-

TION

REGISTER

BUS

BUS LATCH

AND LOW

PC TEMP

REGISTER

8

BUFFER

MULTIPLEXER

REGISTER 0

REGISTER 1

REGISTER 2

RAM ADDRESS

REGISTER

TEST0

TEST1

INT

REGISTER 3

REGISTER 4

REGISTER 5

REGISTER 6

DECODER

FLAG0

FLAG1

TIMER FLAG

PORT1

BUS

REGISTER 7

8-LEVEL

STACK

CARRY

ACC

8

BUFFER

AND

LATCH

OPTIONAL

SECOND

REGISTER

BANK

ACC Bit TEST

DATA STORE

64¥8 bits MSM80C48RS

DATA MEMORY (RAM)

128¥8 bits MSM80C49RS

256¥8 bits MSM80C50RS

8

(PORT 2)

(ROM)

PROGRAM MEMORY

1K¥8bits MSM80C48RS

2K¥8bits MSM80C49RS

4K¥8bits MSM80C50RS

2 or 3

4

HIGHER PROGRAM

COUNTER (4)

8

PORT2 BUS BUFFER

PORT2

LATCH

(HIGH4)

44

PORT2 LATCH

(LOW4) AND

EXPANDER

PORT I/O

LOWER PROGRAM

COUNTER (8)

(8)

TIMER/EVENT

COUNTER (8)

TEST1

∏480

OSC FREQ

TEMP REG (8) FLAGS

ACCUMULATOR

(8)

CONDI-

TIONAL

BRANCH

LOGIC

(8)

UNIT

LOGIC

ARITHMETIC

ACCUMULATOR

LATCH (8)

ADJUST

DECIMAL

WRRDSSPSENALEXTAL2XTAL1EAPROGRESETINT

CONTROL AND TIMING

WRITE

STROBE

READ

STROBE

SINGLE

ENABLE

MEMORY

PROGRAM

ADDRESS LATCH,

XTAL

OSCILLATOR

CPU MEMORY

PROM/

STROBE

EXPANDER

INITIALIZE

INTERRUPT

STEP

CLOCK

DATA LATCH

STROBE CYCLE

SEPARATE

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¡ Semiconductor MSM80C48/49/50, MSM80C35/39/40

PIN CONFIGURATION (TOP VIEW)

T0

XTAL1

XTAL2

RESET

SS

INT

EA

RD

PSEN

WR

ALE

DB

DB

DB

DB

DB

DB
DB

DB

V

SS

1

2

3

4

5

6

7

8

9

10
11

12

0

13

1

14

2

15

3

16

4

17

5

18

6

19

7

20

40

39

38

37

36

35

34

33

32

31
30

29

28

27

26

25

24
23

22

21

V

CC

T1

P2

7

P2

6

P2

5

P2

4

P1

7

P1

6

P1

5

P1

4

P1

3

P1

2

P1

1

P1

0

V

DD

PROG

P2

3

P2

2

P2

1

P2

0

V

P1

P1

P1

P1

P1

P1

P1

P1

P2

DD

NC

35

21

NC

4

34

33

32

31

30

29

28

27

26

25

24

23

22

RESET

DB

3

DB

2

DB

1

DB

0

ALE

WR
PSEN
RD

EA

INT
SS

3P22P21P20

NC

44

PROG

P2

43

42

41

40

VSSDB7DB6DB5DB

39

38

37

36

1

2

0

3

1

4

2

5

3

6

4

7

5

8

9

6

10

7

11

4

12

13

14

15

16

17

18

19

20

NC

5P26P27

P2

T1

CC

T0

V

XTAL1

XTAL2

NC: No-connection pin

40-Pin Plastic DIP 44-Pin Plastic QFP

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¡ Semiconductor MSM80C48/49/50, MSM80C35/39/40

PIN DESCRIPTIONS

Symbol

-P1

P1

0

(PORT 1)

P20-P2

(PORT 2)

DB0-DB

(BUS)

T0

(Test 0)

T1

(Test 1)

Type Description

7

7

I/O

8-bit quasi-bidirectional portI/O

8-bit quasi-bidirectional port
The high-order four bits of external program memory addresses can be output
from P2.0-P2.3, to which the I/O expander MSM82C43RS may also be connected.

7

I/O

Bidirectional port
The low-order eight bits of external program memory address can be output
from this port, and the addressed instruction is fetched under the control of
PSEN signal. Also, the external data memory address is output, and data is
read and written synchronously using RD and WR signals.
The port can also serve as either a statically latched output port or a
non-latching input port.

I/O

The input can be tested with the conditional jump instructions JT0 and JNT0.
The execution of the ENT0 CLK instruction causes a clock output.

I

The input can be tested with the conditional jump instructions JT1 and JNT1.
The execution of a STRT CNT instruction causes an internal counter input.

INT

(Interrupt)

I

Interrupt input. If interrupt is enabled, INT input initiates an interrupt.
Interrupt is disabled after a reset.
Also testable with a JNI instruction. Can be used to terminate the power-down
mode. (Active "0" level)

RD

A signal to read data from external data memory. (Active "0" level)O

(Read)

WR

A signal to write data to external data memory. (Active "0" level)O

(Write)

ALE

O
Address &
Data Latch

Clock

PSEN Program

O

Store Enable

RESET RESET input initialize the processor. (Active "0" level)

I

This signal is generated in each cycle. It may be used as a clock output.
External data memory or external program memory is addressed upon the
falling edge. For the external ROM, this signal is used to latch the bus port data
upon the ALE signal rise-up after the execution of the OUTL BUS, A instruction.

A signal to fetch an instruction from external program memory
(Active "0" level)

Used to terminate the power-down mode.

SS

(Single Step)

I

A program is executed step by step. This pin can also be used to control
internal oscillation when the power-down mode is reset.
(Active "0" level)

EA

(External Access)

PROG

(Expander Strobe)

I

When held at high level, all instructions are fetched from external memory.
(Active "1" level)

This output strobes the MSM82C43RS I/O expander.O

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¡ Semiconductor MSM80C48/49/50, MSM80C35/39/40

PIN DESCRIPTIONS (Continued)

Symbol

XTAL1

(Crystal 1)

XTAL2

(Crystal 2)

V

CC

V

DD

V

SS

Type Description

One side of the internal crystal oscillator. An external clock can also be input.I

Other side of the internal crystal oscillator.O

Power supply pin—

—

Standby control input. Normally, "1" level. When set to "0" level, oscillation is
stopped and prosessor goes into standby mode.

GND—

Note: A minimum of two machine cycles are required in RESET pulse duration under the

specified power supply and stable oscillator frequency.

5/20

¡ Semiconductor MSM80C48/49/50, MSM80C35/39/40

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol

Supply Voltage V

Input Voltage V

Storage Temperature T

CC

I

STG

Condition Rating Unit

Ta=25°C –0.5 to 7 V

Ta=25°C –0.3 to V

— –65 to +150 °C

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol

Supply Voltage V

Ambient Temperature T

CC

a

Fan Out N

* Minimum operating voltage is dependent on frequency.

Condition Range Unit

f

=DC to 11MHz* +2.5 to +6 V

OSC

— –40 to +85 °C

MOS load 10 —

TTL load 1 —

+0.5 V

CC

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