OKI MSM7719-01 Technical data

E2U0058-18-85

¡ Semiconductor

This version: Aug. 1998

MSM7719-01

¡ Semiconductor

MSM7719-01

Echo Canceler with ADPCM Transcoder

GENERAL DESCRIPTION

The MSM7719, developed for PHS (Personal Handyphone System) applications, is an LSI device and contains a line echo canceler, an acoustic echo canceler (for handsfree conversation), and a single channel full-duplex ADPCM transcoder. This device includes DTMF tone and several types of tone generation, transmit/receive data mute and gain control, and VOX function and is best suited for PHS applications.

FEATURES

• Single 5 V power supply VDD : 4.5 V to 5.5 V

• ADPCM : ITU-T Recommendations G.726

• PCM interface coding format : µ-law

• Built-in 2-channel (line and acoustic) echo canceler Line echo canceler Acoustic echo canceler (for handsfree conversation) Echo attenuation : 30 dB (typ.) Cancelable echo delay time :

27 ms (max.) for line echo canceler +27 ms (max.) for acoustic echo canceler Line echo canceler mode only : 54 ms (max.)

• Serial PCM/ADPCM transmission data rate : 64 kbps to 2048 kbps

• Low supply current Operating mode : Typically 50 mA (VDD = 5.0 V) Power-down mode : Typically 0.2 mA (VDD = 5.0 V)

• Master clock frequency : 9.6 to 10.0 MHz/19.2 to 20.0 MHz

• Transmit/receive mute, transmit/receive programmable gain control

• Built-in DTMF tone generator and various tones generator

• Control through parallel microcontroller interface Pin control available for line and acoustic echo cancelers

• Built-in VOX control Transmit side : Voice/silence detect Receive side : Background noise generation at the absence of voice signal

• Package:

100-pin plastic TQFP (TQFP100-P-1414-0.50-K) (Product name : MSM7719-01TS-K)

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BLOCK DIAGRAM

MSM7719-01

DETSL

DETT DETP

LTHR

LDCL

LCCL

LHD

LCLP

LHLD

LATT

LGC

LATTG2-0

LATTL2-0

SinL

ATTIL

RoutL

Line Echo Canceler Controller

ATTtgrx

ATTsL

Line

Adaptive FIR Filter

(LAFF)

Howling Detector

Double Talk Detector

GainL ATTrL

Line Echo Canceler

Center

Clip

Power Calc.

Tone Generator (DTMF etc).

ATTgL

SoutL

RinL

ATTtgtx

ATTrA GainA

RinA

Power Calc.

Howling Detector

Double Talk Detector

SoutA

Center Clip

ATTgA

Acoustic Echo Canceler

Power Detect Voice Detect

ADPCM TRANSCODER

Acoustic

Adaptive FIR Filter

(AAFF)

ATTsA

Mute

Note Gen.

ADPCM CODER

RoutA

ATTIA

–

SinA

MLV0-2 MUTE

VOXI

VOXO

VREF

Timing Gen.

P/S

BCLKA SYNCA

ECMODE

ATHR

ADCL ACCL

AHD ACLP AHLD

AATT

AGC AATTG2-0 AATTL2-0

Acoustic Echo Canceler Controller

MTYPE

MCUSL

MCU I/F

A4-0

D7-0

I/O Controller

N/L L/N N/L L/N N/L L/N

P/S&S/P

INT

PCMSL

PCMLNI

PCMLNO

PCMACI

PCMACO

PCMADI

PCMADO

DTHR

ADPCM DECODER

Timing Gen.

SYNCP

Clock Gen. Test I/F

MCK

BCLKP

MCKSL

PDN/RST

S/P

PDWN

TSTI1-6

CONTA IOSL0-1

DDD1-3

DDA

DG1-3 AG

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PIN CONFIGURATION (TOP VIEW)

MSM7719-01

DDD1

DDD3

PDN/RST

SYNCA

SYNCP

100

1 2WR 3RD 4A0 5A1 6A2 7V 8LDCL

9LCCL 10LHD 11LCLP 12DG1 13LHLD 14LATT 15LTHR 16LGC 17AGC 18ATHR 19AATT 20AHLD 21ACLP 22AHD 23ACCL 24ADCL 25NC

PDWN

TSTI1 86

INT

TSTI2 84

DETP 83

DG3 82

DETT

DETSL 80

ECMODE 79

IOSL1 78

IOSL0 77

NC 76

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

A3 VOX0 MCUSL PCMSL IS PCMLN0 PCMAD0 PCMAC0 V

DDD2

MUTE VOXI TSTI6 TSTI5 BCLKP BCLKA MTYPE DTHR MLV0 MLV1 MLV2 AG NC NC

LATTL1

LATTL2

LATTL0

LATTG2

DG2

AATTL0

AATTL1

AATTL2

LATTG0

LATTG1

NC: No-connect pin

100-Pin Plastic TQFP

AATTG1

AATTG2

AATTG0

PCMACI

PCMADI

CONTA

PCMLNI

DDA

TSTI4

TSTI3

MCK

MCKSL

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MSM7719-01

PIN FUNCTIONAL DESCRIPTION

Outputs of the analog signal ground voltage. The output voltage is approximately 2.4 V. Connect bypass capacitors of 10 mF and 0.1 mF (ceramic type) between these pins and the AG pin. During power-down, the output changes to 0 V.

Analog ground.

DG1, 2, 3

Digital ground.

DDA

+5 V power supply for analog circuits.

DDD1, 2, 3

+5 V power supply for digital circuits.

PDN/RST

Power-down reset control input. A logic “0” makes the LSI device enter a power-down state. At the same time, all control register data are reset to the initial state. Set this pin to a logic “1” during normal operating mode. Since this pin is ORed with CR0-B5 (bit 5 (B5) of control register CR0), set CR0-B5 to logic “0” when using this pin. When this pin control is not used (i.e., when controlling by the control register), set this pin to logic “1”.

PDWN

Power-down control input. The device changes to the power-down state, and each bit of control register and internal variables of control register are not reset when set to a logic “0”. During normal operation, set this pin to logic “1”. Since this pin is ORed with CR0-B6 (bit 6 (B6) of control register CR0), set CR0-B6 to logic “0” when using this pin. When this pin control is not used (i.e., when controlling by the control register), set this pin to logic “1”.

MCK

Master clock input. The frequency must be 9.6 to 10.0 MHz/19.2 to 20.0 MHz. The master clock signal is allowed to be asynchronous with SYNCP, SYNCA, BCLKP, and BCLKA.

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MCKSL

Master clock selection input. Set MCKSL to logic “0” when the master clock frequency is 9.6 to 10.0 MHz, and to logic “1” when it is 19.2 to 20.0 MHz.

PCMACO

PCM data output of the echo canceler. PCM is output from MSB in a sequential order, synchronizing with the rising edge of BCLKP and SYNCP. This pin is in a high impedance state except during 8-bit PCM output. When DTHR is set to logic “1”, this pin becomes a 4-bit output and the input data to the input pin set by IOSL0-1 is output as it is. In this case, this pin is in a high impedance state except during 4-bit output. Note that the echo canceler signal output mode for this pin changes depending on the setting of IOSL0-1. (This pin is also in a high impedance state during power-down or initial mode.) Refer to Figs. 1-5.

PCMACI

PCM data input of the echo canceler. PCM is shifted in at the falling edge of BCLKP and input from MSB. The start of the PCM data (MSB) is identified at the rising edge of SYNCP. When DTHR is set to logic “1”, this pin becomes a 4-bit input and the input data is output to the output pin set by IOSL0-1 as it is. This pin is provided with a 500-kW pull-up resistor. Note that the echo canceler signal input mode for this pin changes depending on the setting of IOSL0-1. Refer to Figs. 1-5.

MSM7719-01

PCMADO

PCM data output. PCM is serially output from MSB in synchronization with the rising edge of BCLKP and SYNCP. This pin is in a high impedance state except during 8-bit PCM output. When DTHR is set to logic “1”, this pin becomes a 4-bit output and the input data to the input pin set by IOSL0-1 is output as it is. In this case, this pin is in a high impedance state except during 4-bit output. Note that the signal ouput mode for this pin changes and the I/O control signal for this pin switches between BCLKA/SYNCA and BCLKP/SYNCP depending on the setting of IOSL0-1. (This pin is also in a high impedance state during power-down or initial mode.) Refer to Figs. 1-5.

PCMADI

PCM data input. PCM is shifted in at the falling edge of the BCLKP signal and input from MSB. The start of the PCM data (MSB) is identified at the rising edge of SYNCP. When DTHR is set to logic “1”, this pin becomes a 4-bit input and the input data is output to the output pin set by IOSL0-1 as it is. This pin is provided with a 500-kW pull-up resistor. Note that the signal input mode for this pin changes and the I/O control signal for this pin switches between BCLKA/SYNCA and BCLKP/SYNCP depending on the setting of IOSL0-1. Refer to Figs. 1-5.

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IOSL0-1

These pins specify PCM signal I/O mode for the PCMACO, PCMACI, PCMADO, and PCMADI pins. Since The IOSL0 and IOSL1 pins are ORed with the control register bits CR3-B6 and B5, set these bits to logic “0” before using these pins. When this pin control is not used (i.e., in the case of control with the control register), set these pins to logic “0”. Refer to Figs. 1-5.

Transmit ADPCM data output. This data is serially output from MSB in synchronization with the rising edge of BCLKA and SYNCA. This pin is in a high impedance state except during 4-bit ADPCM output. When CONTA is set to logic

“1”, this pin becomes an 8-bit output and the data that passed through the ADPCM is output. In this case, this pin is in a high impedance state except during 8-bit output. (This pin is also in a high imedance state during power-down or initial mode.) Refer to Figs. 1-5.

Receive ADPCM data input. ADPCM is shifted in on the rising edge of BCLKA in synchronization with SYNCA and input data orderly from MSB. When CONTA is set to logic “1”, this pin becomes an 8-bit input and the data is passed through the ADPCM transcoder and processed. This pin is provided with a 500-kW pull-up resistor.

MSM7719-01

transcoder

PCMLNO

PCM receive data output of the line echo canceler. PCM is output from MSB in a sequential order, synchronizing with the rising edge of BCLKP and SYNCP. This pin is in a high impedance state except during 8-bit PCM output. When DTHR is set to logic “1”, this pin becomes a 4-bit output and the input data to the input pin set by IOSL0-1 is output as it is. In this case, this pin is in a high impedance state except during 4-bit output. (This pin is also in a high impedance state during power-down or initial mode.) Refer to Figs. 1-5.

PCMLNI

PCM transmit data input of the line echo canceler. PCM is shifted in at the falling edge of the BCLKP signal and input from MSB. The start of the PCM data (MSB) is identified at the rising edge of SYNCP. When DTHR is set to logic “1”, this pin becomes a 4-bit input and the input data is output to the output pin set by IOSL0-1 as it is. This pin is provided with a 500-kW pull-up resistor. Refer to Figs. 1-5.

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BCLKA

Shift clock input for the ADPCM data (IS, IR). The frequency is from 64 kHz to 2048 kHz.

SYNCA

8 kHz synchronous signal input for ADPCM data. Synchronize this data with BCLKA signal. SYNCA is used for indicating the MSB of the serial ADPCM data stream.

BCLKP

Shift clock input for the PCM data (PCMLNO/PCMLNI, PCMACO/PCMACI, PCMADO/ PCMADI). The frequency is set in the range of 64 kHz to 2048 kHz.

SYNCP

8 kHz synchronous signal input for PCM data. This signal must be synchronized with the BCLKP signal.

MCUSL, MTYPE

MSM7719-01

If the microcontroller interface is not to be used, set the MCUSL input pin to logic “1”. This setting skips the intitial mode as the operating mode. For the MTYPE pin, which is the microcontroller interface selection pin, logic “0” sets the read/write independent control mode and logic “1” sets read/write shared control mode. When this pin control is not used (i.e., when controlling by the control register), set these pins to logic “0”.

CS, RD, WR

A 19-byte control register is provided in this LSI device. Data is read and written by using these pins from the external microcontroller. See the microcontroller write and read timing diagrams in the Electrical Characteristics. When this pin control is not used (i.e., when controlling by the control register), set these pins to logic “1”.

A4-A0, D7-D0

A4-A0 are address input pins of the control register, and D7-D0 are data I/O pins. When this pin control is not used (i.e., when controlling by the control register), set these pins to logic “0”.

INT

Reserved.

PCMSL

Reserved.

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MSM7719-01

CONTA

ADPCM transcoder setting pin. When this pin is set to logic “1”, the transcoder-through mode is set. In this mode, the IS and IR pins become 8-bit PCM serial input and output pins. Since this pin is ORed with the control register bit CR1-B7, set CR1-B7 to logic “0” to use this pin. When this pin control is not used (i.e., when controlling by the control register), set this pin to logic “0”. Refer to Figs. 1-5.

DTHR

Through mode setting pin. When this pin is set to logic “1”, the entire circuit is put in the through mode. In this mode, the PCM input and output pins become 4-bit serial input and output pins and all functions of the echo canceler, ADPCM transcoder, and MUTEVOX are disabled. Use this pin when making 32-kbps data communication. Since this pin is ORed with the control register bit CR1-B5, set CR1-B5 to logic “0” to use this pin. When this pin control is not used (i.e., when controlling by the control register), set this pin to logic “0”. Note that 64-kbps data communication is not supported in this device. Refer to Figs. 1-5.

SYNCP BCLKP CR2-B3, B2

Echo Canceler (54ms)

(a)

(c)

Output Control Input Control Input Control Output Control Output Control Input Control Input Control Output Control

PCMLNO PCMACI PCMACO PCMADOPCMLNI PCMADI IR IS SYNCA

Line Echo Canceler (27ms)

(c)(c)

Acoustic Echo Canceler (27ms)

(a)

(b)

ADPCM Transcoder

(b) (b)

(b)

(c)

BCLKA

Figure 1 Signal I/O Control 1

IOSL1="0", IOSL0="0" Control (a): ECMODE, CR0-B0 Control (b): CONTA, CR1-B7 Control (c): DTHR, CR1-B5

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Line

(a)

Echo Canceler (27ms)

Echo Canceler (54ms)

Acoustic Echo Canceler (27ms)

(a)

(b)

MSM7719-01

(b)

ADPCM Transcoder

(c)

Output Control Input Control Output Control Input Control Input Control Output Control

Input Control Output Control

(c)

SYNCP BCLKP CR2-B3, B2

PCMLNO PCMLNI IR IS SYNCA

SYNCP BCLKP CR2-B1, B0

PCMACI PCMACO PCMADO PCMADI SYNCP

BCLKP CR2-B4

Figure 2 Signal I/O Control 2

IOSL1="0", IOSL0="1" Control (a): ECMODE, CR0-B0 Control (b): CONTA, CR1-B7 Control (c): DTHR, CR1-B5

Line Echo Canceler (27ms)

Acoustic Echo Canceler (27ms)

ADPCM Transcoder

(b)

BCLKA

(b)

SYNCP BCLKP CR2-B3, B2

Output Control Input Control Input Control Output Control Output Control Input Control Input Control Output Control

(b) (b)

PCMLNO

PCMLNI

SYNCP BCLKP CR2-B1, B0

PCMACI PCMACO

PCMADO

PCMADI

SYNCP BCLKP CR2-B4

IR IS

Figure 3 Signal I/O Control 3

IOSL1="1", IOSL0="0" Control (a): ECMODE, CR0-B0 Control (b): CONTA, CR1-B7 Control (c): DTHR, CR1-B5

SYNCA BCLKA

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(

)

MSM7719-01

(b)

Line Echo Canceler (27ms)

SYNCP BCLKP CR2-B3

PCMLNO PCMACI PCMACO PCMADOPCMLNI PCMADI IR IS SYNCA

SYNCP BCLKP CR2-B1

Figure 4 Signal I/O Control 4

SYNCP/SYNCA

BCLKP/BCLKA PCM multiplexing

PCMADI/O data (DTHR="0")

PCMADI/O data (DTHR="1")

time slot 1

12345678 23456781

MSB

1234 1234

MSB

time slot 2 time slot 3 time slot 4

Acoustic Echo Canceler (27ms)

(c)(c)(c)

Output Control Input ControlInput Control Output ControlOutput Control Input Control

(b)

ADPCM Transcoder

(c)

Input Control Output Control

(b) (b)

SYNCA BCLKA CR2-B4

BCLKA

IOSL1="1", IOSL0="1" Control (a): ECMODE, CR0-B0 Control (b): CONTA, CR1-B7 Control (c): DTHR, CR1-B5

PCMLNI/O data PCMACI/O data (DTHR="0")

PCMLNI/O data PCMACI/O data (DTHR="1")

IR/IS data (CONTA="1")

IR/IS data

CONTA="0"

12345678 23456781 12345678 23456781

MSB

1234 1234 1234

MSB

12345678

MSB

1234

MSB

Note: The PCM signals (PCMADI and PCMADO) of the ADPCM transcoder can be assigned to

time slot 1 or 2. The PCM signals (PCMLNI, PCMLNO, PCMACI, and PCMACO) of the echo canceler can be assigned to one of the time slots 1 to 4. The ADPCM signals (IR and IS) of the ADPCM transcoder are always assigned to time slot

Figure 5 PCM Multiplexing/ADPCM Timing

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ECMODE

This pin specifies the operating mode of the echo canceler. When set to logic “0”, this device operates as a line echo canceler (with cancelable echo delay time of 27 ms max.) + an acoustic echo canceler (with cancelabel echo delay time of 27 ms max.); when set to logic “1”, it operates as a line echo canceler (with cancelable echo delay time of 54 ms max.). When this pin control is not used (i.e., when controlling by the control register), set these pins to logic “0”.

LTHR, ATHR

(L: Line A: Acoustic) These pins control the through mode of the echo canceler. In this mode, SinL/A data and RinL/A data is output directly to SoutL/A and RoutL/A respectively, while retaining their echo canceler coefficients. 0: Normal mode (Echo cancellation) 1: Through mode When this pin control is not used (i.e., when controlling by the control register), set these pins to logic “1”.

LDCL, ADCL

These pins control clearing the coefficient 1 of the adaptive FIR filter used by the echo canceler. If the echo path changes, reset both the coefficient 1 (by setting LDCL/ADCL to “0”) and the coefficient 2 (by setting LCCL/ACCL to “0”) of the adaptive FIR filter whenever possible. 0: Resets the coefficient 1: Normal operation When this pin control is not used (i.e., when controlling by the control register), set these pins to logic “1”.

MSM7719-01

LCCL, ACCL

These pins control clearing the coefficient 2 of the adaptive FIR filter used by the echo canceler. If the echo path changes, reset both the coefficient 1 (by setting LDCL/ADCL to “0”) and the coefficient 2 (by setting LCCL/ACCL to “0”) of the adaptive FIR filter whenever possible. 0: Resets the coefficient 1: Normal operation When this pin control is not used (i.e., when controlling by the control register), set these pins to logic “1”.

LHD, AHD

Howling detection ON/OFF control pins. 0: OFF, 1: ON When this pin control is not used (i.e., when controlling by the control register), set these pins to logic “0”.

LCLP, ACLP

These pins turn ON or OFF the Center Clipping funciton that forcibly sets the SoutL output of the line echo canceler to minimum positive value when it is –57 dBm0 or less. 0: Center Clipping OFF 1: Center Clipping ON When this pin control is not used (i.e., when controlling by the control register), set these pins to logic “0”.

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LHLD, AHLD

These pins control updating the coefficient of the adaptive FIR filter (AFF) for the echo canceler. 0: Normal mode (updates the coefficient) 1: Coefficient Fixed mode When this pin control is not used (i.e., when controlling by the control register), set these pins to logic “0”.

LATT, AATT

These pins turn ON or OFF the ATT function that prevents howling from occurring by means of attenuators ATTsL/A and ATTrL/A provided for the RinL/A input and the SoutL/A output of the echo canceler. When a signal is input to RinL/A only, the attenuator ATTsL/A of the SoutL/A output is activated. When a signal is input to SinL/A only or to both SinL/A and RinL/A, the attenuator ATTrL/A of the RinL/A input is activated. The ATT values are both about 6 dB. 0: ATT function ON 1: ATT function OFF When this pin control is not used (i.e., when controlling by the control register), set these pins to logic “0”.

LGC, AGC

MSM7719-01

These pins turn ON or OFF the gain control function that controls the RinL/A input level and prevents howling from occurring by the gain controller (GainL/A) provided for the RinL/A input of the echo canceler. The RinL/A input level is adjusted in the attenuation range of 0 to –8.5 dB. This adjusting starts at the RinL/A input level of –24 dBm0. 0: gain control OFF 1: gain control ON When this pin control is not used (i.e., when controlling by the control register), set these pins to logic “0”.

MUTE

Receive side voice path mute level enable pin. To set a mute level, set this pin to logic “1”. When this pin control is not used (i.e., when controlling by the control register), set this pin to logic “0”.

MLV0-2

Receive side voice path mute level setting pins. For the control method, refer to the control register (CR1) description. Since this signal is ORed with CR1-B2, B1, and B0 internally, set the bits of the register to logic “0” before using these pins.

DETSL

Reserved pin. Set this pin to logic “0”.

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