OKI MSM6896GS-BK, MSM6895GS-BK Datasheet

E2U0022-28-81

¡ Semiconductor MSM6895/6896

¡ Semiconductor

This version: Aug. 1998

Previous version: Nov. 1996

MSM6895/6896

Multi-Function PCM CODEC

GENERAL DESCRIPTION

The MSM6895/MSM6896, developed especially for low-power and multi-function applications in ISDN telephone terminals, are single +5 V power supply CODEC LSI devices. The devices consist of the analog speech paths directly connectable to a handset, the calling circuit directly connectable to a piezosounder, the push-button key scanning interface between push buttons and control processors, the dial tone generator, the B-channel interface, the CODEC, and the processor interface. The functions can be controlled via the 8-bit data bus.

FEATURES

• Single +5 V Power Supply

• Low Power Dissipation Power ON Mode : 20 mW Typ. 53 mW Max. CODEC Power Down Mode : 10 mW Typ. 21 mW Max.

• In compliance with ITU-T’s companding law m-law : MSM6895 A-law : MSM6896

• Transmission clocks Continuous CLK : 64, 128, 256 kHz Burst CLK : 192, 384, 768, 1536, 2048 kHz

• Built-in PLL

• Built-in Reference Voltage Supply

• Ringing Tone : Controlled by processor, 9 modes

• Ringing Tone Combination : Controlled by processor, 6 modes

• Information Tone : Controlled by processor, 9 modes

• Built-in PB Tone Generator

• B-Channel Selectable

• General Latch Output for Speech path Control : 4 bits

• Watchdog Timer : 500 ms

• Key Scanning I/O Output : 5 bits Input : 8 bits

• Direct Connection to Handset

• Built-in Preamplifier for Loudspeaker

• Handfree Interface

• Digital and Analog Interface for the phone-conference speech paths

• Package:

80-pin plastic QFP (QFP80-P-1420-0.80-BK) (Product name : MSM6895GS-BK)

(Product name : MSM6896GS-BK)

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BLOCK DIAGRAM

TMX1I

TPAO MLDYTPBI

TPAI

CAO R1I

R2I

TMX2I

T2O

MIX

PLL

T1 O

CAI

AIN

CODEC

AOUT

TEST

CK1536 TEST

B1T B1R

B2T B2R

BR1 BT1

BR2 BT2

HANDSET

BUZZER

RPO

RMI

RMO0

RMO1

SPO

SA0

SA1

MIX

F-TONE

GEN

R-TONE

GEN

DTMF TONE

GEN

–

S-TONE

MIX

SW CONT.

SGGEN

PO0 ~

VSGCVSG

PO4

VD VAG VDGVA

SCANNING OUTPUT

GEN

LATCH

KEY INTF.

KEY DATA INPUT

CK8

CK64

64K

SW0 SW1

WR RD

CE RESET

8BIT

LA ~ LD

PI0 to PI7

7654321043210

Data Bus AD0

AD1 INTT

TIME

4BIT

LOSS

LML

SWITCH HOOK

MPU INTF. CHANNEL SELECTOR

PUSH-BOTTON SWITCH

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PIN CONFIGURATION (TOP VIEW)

LML

TIME

RESET

BR2

BR1 75

BT2 74

BT1 73

B2R

B1R 71

B2T

B1T

AD1

LC LD

SW0 SW1

VDG

VAG

SA0 SA1

RM1

NC RMO0 RMO1

13 14

2 3

4 5

7 8 9

63 62

61 60

58 57 56

52 51

AD0 DB7

DB6 DB5

DB4

DB3 DB2 DB1

DB0

INTT

PI7

PI6 PI5

SPO

RPO

R2I R1I

TMX2I

MLDY

TPBI

TMX1I

17 18

20 21

22 23

TPAI

VSG

TPAO

T1O

T2O

30 NC

NC : No connect pin

80-Pin Plastic QFP

32 VA

CAI

VSGC

CA0

TEST

CK64

CK1536

CK8

LOSS

48 47

45 44

43 42

PI4

PI3

PI2 PI1

PI0

PO4 PO3 PO2

PO1

PO0

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PIN DESCRIPTION

Pin Symbol Type Description

1 LB DO Data Latch Output B 2 LC DO Data Latch Output C 3 LD DO Data Latch Output D 4 SW0 DI Sounder Tone Select (1) 5 SW1 DI Sounder Tone Select (2) 6 VDG — Digital Ground 7 VAG — Analog Ground 8 SA0 DO Sounder Output (+)

9 SA1 DO Sounder Output (–) 10 — — NC 11 RMI AI Receive Main Amp Input 12 — — NC 13 RMO0 AO 14 RMO1 AO 15 SPO AO Speaker Pre-Amp Output 16 RPO AO Receive Pre-Amp Output 17 R2I AI 18 R1I AI Receive Signal Input 19 — — NC 20 — — NC 21 TMX2I AI 22 MLDY AI Hold Tone Input 23 TPBI AI 24 TMX1I AI 25 TPAI AI 26 VSG AO Signal Ground 27 TPAO AO 28 T1O AO Transmit Signal Output (1) 29 T2O AO Transmit Signal Output (2) 30 — — NC

Receive MainAmp Output (+) Receive MainAmp Output (–)

Receive Addition Signal Input

Transmit Addtion Signal Input (2)

Transmit Pre-Amp (B) Input

Transmit Addtion Signal Input (1)

Transmit Pre-Amp (A) Input

Transmit Pre-Amp (A) Output

Pin Symbol Type Description

31 — 32 VA 33 CAI 34 VSGC 35 CAO 36 TEST 37 CK1536 38 CK64 39 CK8 40 LOSS 41 PO0 42 PO1 43 PO2 44 PO3 45 PO4 46 PI0 47 PI1 48 PI2 49 PI3 50 PI4 51 PI5 52 PI6 53 PI7 54 INTT 55 DB0 56 DB1 57 DB2 58 DB3 59 DB4 60 DB5

— —

AI AO AO

DI DO DO DO DO DO DO

DI DO I/O I/O I/O I/O I/O I/O

NC +5 V Analog Power Supply Analog Signal Input to CODEC Bypass Capacitor for Signal Ground Analog Signal Output from CODEC Control Input for Test Clock Input for Test Transmission Colck Input Frame Synchronous Clock Input Howler Tone Control Signal Key Scanning Signal Output (0) Key Scanning Signal Output (1) Key Scanning Signal Output (2) Key Scanning Signal Output (3) Key Scanning Signal Output (4) Key Scanned Data Input (0) Key Scanned Data Input (1) Key Scanned Data Input (2) Key Scanned Data Input (3) Key Scanned Data Input (4) Key Scanned Data Input (5) Key Scanned Data Input (6) Key Scanned Data Input (7) Interrupt Output Data Bus (0) Data Bus (1) Data Bus (2) Data Bus (3) Data Bus (4) Data Bus (5)

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PIN DESCRIPTION (Continued)

Pin Symbol Type Description

61 DB6 I/O Data Bus (6) 62 DB7 I/O Data Bus (7) 63 AD0 DI Address Data (0) 64 VD — 65 AD1 DI Address Data Input (1) 66 WR DI Write Signal Input 67 RD DI Read Signal Input 68 CE DI Chip Enable 69 B1T DO 70 B2T DO

+5 V Digital Power Supply

B1 Channel Transmit Output B2 Channel Transmit Output

Pin Symbol Type Description

71 B1R B1 Channel Recive Input 72 B2R B2 Channel Recive Input 73 BT1 74 BT2 75 BR1 76 BR2 77 RESET Reset Input 78 TIME Timer Output 79 LML Hold Tone Control Output 80 LA Data Latch Output (A)

DI DI DI

DI DO DO

DI DO DO DO

B Channel Selector Transmit Data (1) B Channel Selector Transmit Data (2) B Channel Selector Receive Data (1) B Channel Selector Receive Data (2)

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PIN AND FUNCTIONAL DESCRIPTIONS

LA, LB, LC, LD

General latch outputs for external control. Statuses of these outputs are controlled via the processor interface. Refer to the description of the control data for details.

SW0, SW1

External control signal inputs for setting the tone combination of the ringing tone. When the external control for setting the tone combination is selected, the tone combination is set by these pins.

SW0

0 0 1 1

VDG

Digital Ground.

SW1

0 1 0 1

Tone combination 1 Tone combination 2 Tone combination 3 Tone combination 1

1 / f1

Wambling Cycle

16 Hz 16 Hz 8 Hz 16 Hz

Wambling Cycle Time

1 / f2

1000 Hz 800 Hz 800 Hz 1000 Hz

1333 Hz 1000 Hz 1000 Hz 1333 Hz

VAG

Analog Ground.

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SA0, SA1

Sounder (ringing tone) driving outputs. The output signal on SA1 is inverted against the signal on SA0. The sounder circuit can be easily configured by connecting a piezo-sounder between SA0 and SA1. Through processor control, the ringing tone volume is selectable from four levels and one of six tone combinations is selectable. Initially, the ringing tone volume is set at a maximum and the tone combination is set externally. If these pins are used with no-load, tone volume cannot be controlled. When tone volume control is required, a load resistor must be connected between SA0 and SA1.

RMI, RMO0, RMO1

Receive main amplifier input and outputs. RMI is the main amplifier input and RMO0 and RMO1 are the main amplifier outputs. The output signal on RMO1 is inverted against RMO0, so the earphone of a piezo electric-type handset is directly connected between RMO0 and RMO1. The RMI input pin is connected to the receive preamplifier output pin (RPO).

If the adjusting of receive path frequency characteristics is required, insert the following circuit for adjustment. During initial setting, the speech path from RMI to RMO0 and RMO1 is disconnected and the output of RMO0 and RMO1 is at the VSG level (VA/2). The speech path is provided by processor control.

A circuit example for adjustment of frequency characteristics

RPO

RMI VSG

SPO

Output of preamplifier for speaker. Since the driving capability is 2.4 VPP for the load of 20 kW, SPO can not directly drive a speaker. During initial setting, SPO is in a non-signal state (VSG level), and a speech signal, RTONE0, RTONE1, FTONE, hold acknowledge tone, and PB signal acknowledge tone are output through processor control.

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R1I, R2I, RPO

Receive preamplifier inputs and output. R1I and R2I are for the inputs and RPO is for the output of the receive preamplifier. Normally, R1I is connected via an AC-coupling capacitor to the CODEC analog output (CAO), and R2I is used as the mixing signal input pin. During initial setting, the RPO output is in non-signal state (VSG level), and speech signal, RTONE1, RTONE2, FTONE, PB acknowledge tone, and side tone signal are output through processor control. And if the three-party speech function is required, the R2I pin is connected to the analog output of the other CODEC.

MLDY

Hold tone signal input. This pin is connected to the output of external melody IC. Through processor control, the signal applied to MLDYI is output from the TO output pin as a hold tone on the transmit path, and from the SPO output pin as a hold acknowledge tone on the receive path.

TPBI

Transmit signal input. When the handset is used, TPBI is connected to the transmit preamplifier output pin (TPAO). If adjustment of frequency characteristics on the transmit path is required, insert a circuit for adjustment of characteristic between TPAO and TPBI. Through processor control, the signal applied to this pin is output via the T1O and T2O pins on the transmit path output and its side tone via the RPO pin.

A circuit example for adjustment of frequency characteristics

TPAO TPBI VSG

C3R3

TMX1I, TMX2I

Transmit addition signal inputs. Through processor control, the input signals to TMX1I and TMX2I are added to the transmit signal and are output to T1O and T2O respectively.

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TPAI, TPAO

The transmit preamplifier input and output. TPAI is the input and TPAO is the output. Connect TPAI to the microphone of handset via an ACcoupling capacitor if the DC offset appears at a transmit signal (offset from SGT). The transmit path from TPAI to TPAO is always established regardless of processor control.

VSG

Signal ground level output. The output level is equal to a half of the power supply voltage.

VSGC

Bypass capacitor connecting pin for signal ground level. Insert a 0.1 mF capacitor with good higher frequency characteristic, between VSGC and VAG.

VA, VD

+5 V power supply. VA is for an analog circuit and VD is for digital supply. Connect both VA and VD to the +5 V analog path of the system.

CAI

CODEC analog output. Connect CAI to T1O.

CAO

CODEC analog output. Connect CAO to R1I via an AC-Coupling capacitor.

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TEST, CK1536

External master clock inputs. Since the MSM6895 and MSM6896 contain PLL internally, the external clock signal is eliminated. But the device can operate with the external clock through these pins. When these pins are not used, leave these pins open or at 0 V.

Mode

Internal PLL External master clock

TEST pin

0 V

Digital "1"

CK1536 pin

open or 0 V

Input the signal of 1536 kHz

When the external clock is used, the CK1536 signal is required to be synchronized in phase with the CK8 signal.

CK64

CODEC PCM data input and output shift clock input. When the continuous clock is set, the frequency is one of 64 kHz, 128 kHz, and 256 kHz. When the burst clock is used, one of 192, 384, 768, 1536, and 2048 kHz is available. If the BCLOCK signal is not applied, PLL is out of synchronization and goes into the self-running mode.

CK8

Synchronous signal input. CODEC PCM data is sent out sequencially from MSB at the rising edge of the CK64 signal in synchronization with the rise of the synchronous signal. PCM data should be entered from MSB in synchronization with the rise of the synchronous signal. PCM data is shifted in at the falling edge of the CK64 signal.

Since the CK8 signal is used for a trigger signal for PLL and for a clock signal to the tone generator, if this signal is not applied, not only any tone can not be output, but also PLL goes out of synchronization and goes into self-running mode. This signal has to be synchronous with the

CK64 signal and its frequency must be within 8 kHz ±50 ppm to ensure the CODEC AC

characteristics (mainly frequency characteristics).

LOSS

Signal output for controlling the external circuits. When the howler tone of sounder is selected through processor control, the output is in a digital "1". Initially, this output is set to a digital "0".

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PO0, PO1, PO2, PO3, PO4, PO5, PO6, PO7

Key scanning outputs. These output pins need external pull-up resistors because of their open- drain circuits. Through processor control, these outputs can be set open or to digital "0". Initially, these outputs are set at an opened state.

PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7

Key scanning inputs. In the READ mode, data on PI0 to PI7 can be read out of the processor via data bus (DB0 to DB7).

INTT

Interrupt signal output to the processor. INTT outputs interrupt signals (digital "0") at intervals of 8 ms by the interrupt release control signal from the processor. INTT does not output any signal while no CK8 signal is input.

Interrupt release signal

from processor

INTT output

t < 8 ms 8 ms < t < 16 ms t < 8 ms

8 ms 16 ms 8 ms

DB0, DB1, DB2, DB3, DB4, DB5, DB6, DB7

Data bus inputs and outputs.

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AD0, AD1

Address data inputs for the internal control registers. Addressing of the internal control registers is executed by AD0 and AD1 and sub address data, DB7 and DB6.

Write

Read

AD1 AD0 DB7 DB6

0000 0001 0010

0011

01—— 10—— 1100 1101

1110

1111 10——

Sounder Control Control of function key acknowledge tone PB tone control Control of the internal control latch and the general-purpose latch, Reset control of the watch dog timer. Control of channel selector Key scanning output control, interrupt release control Volume control and tone combination control of sounder CODEC power down control Level control of transmit path, PB tone, and Hold tone, Gain control of receive path Frequency control of howler tone Read of the key scanning data

Function

Write signal for internal control registers. Data on the data bus is written into the registers at the rising edge of WR under the condition of digital "0" of CE (Chip Enable). While CE is in digital "1" state, WR becomes invalid. The Write cycle is a minimum of 2 ms, but if the CK64 and CK8 signals are silent, the write cycle requires a minimum of 50 ms. A minimum of 2 ms specified as the write cycle is valid 10 ms after CK64 and CK8 signals are input.

Read signal input to read PI0 to PI7 out of the processor. When CE and RD are in digital "0" state, the digital values on PI0 to PI7 are output onto the data buses DB0 to DB7. While CE is in digital "1" state, the RD signal becomes invalid.

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Chip Enable signal input. When CE is in digital "0" state, WR and RD are valid.

B1T, B2T, B1R, B2R

B channel interface inputs and outputs. B1T and B2T are outputs, and B1R and B2R are inputs. Through channel control by the processor, various data paths are set. The CODEC input and output signals are input and output via these pins. Initially the B1T and B2T outputs are fixed in a digital "1", and the B1R and B2R inputs are neglected.

BR1, BR2, BT1, BT2

External digital inputs and outputs to the B-channel. BR1 and BR2 are outputs, and BT1 and BT2 are inputs. Through channel control by processor, the digital paths are set between these input and output pins and the B channel. These signals are applied to another CODEC interface of three-party the speech path and to the interface of 64 kbps at the rate adaptor circuit. Initially the BR1 and BR2 outputs are fixed in a digital "1", and the BT1 and BT2 inputs are neglected.

RESET

Reset signal input. Digital "0" input to RESET makes all of internal control registers to be initialized. When powered on, this RESET signal should be input for initializing the system.

TIME

Watchdog timer output. When the processor does not reset the timer, the 500 ms period (Digital "0" : 4 ms) digital signal is continuously output. When RESET is at digital "0", this timer is reset. And, in about 500 ms after RESET goes to digital "1", the first timer output signal is issued and then the timer signal is output at intervals of a 500 ms. If the CK8 signal is not input, the TIME signal is not output.

LML

Control signal output for external hold tone generator. LML goes to digital "1" state when the hold tone transmit mode on transmit path or the hold acknowledge tone mode on receive path is selected. During initialized state, LML is in digital "0" state.

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