OKI MSM56V16800F-8TS-K, MSM56V16800F-10TS-K, MSM56V16800F-8ATS-K Datasheet

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Semiconductor

M SM56V16800F

2-Bank ´ 1,048,576 Word ´ 8 Bit SYNCHRONOUS DYNAMIC RAM

DESCRIPTION

The MSM56V16800F is a 2-Bank ´ 1,048,576-word ´ 8 bit Synchronous dynamic RAM, fabricated in OKI’s CMOS silicon-gate process technology. The device operates at 3.3V. The inputs and outputs are LVTTL compatible.

FEATURES

· Silicon gate , quadruple polysilicon CMOS , 1-transistor memory cell

· 2-bank ´ 1,048,576-word ´ 8bit configuration

· 3.3V power supply ± 0.3V tolerance

· Input : LVTTL compatible

· Output : LVTTL compatible

· Refresh : 4096 cycles/64 ms

· Programmable data transfer mode

- CAS Latency (1,2,3)

- Burst Length (1,2,4,8,Full page)

- Data scramble (sequential , interleave)

· CBR auto-refresh, Self-refresh capability

· Package:

44-pin 400mil plastic TSOP (Type II) (TSOPII44-P-400-0.80-K) (Product : MSM56V16800F-xxTS-K)

xx : indicates speed rank.

PRODUCT FAMILY

Access Time (Max.)

Family

Max.

Frequency

t

AC2

t

AC3

MSM56V16800F-8A

125MHz

6ns 6ns MSM56V16800F-8 125MHz 9ns 6ns MSM56V16800F-10 100MHz 9ns 9ns

This version : Dec.1999

MSM56V16800F

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PIN CONFIGRATION (TOP VIEW)

Pin Name Function Pin Name Function

CLK System Clock DQM Data Input/Output Mask

CS Chip Select DQi Data Input/Output

CKE Clock Enable

V

CC

Power Supply (3.3V)

A0–A10 Address

V

SS

Ground (0V)

A11 Bank Select Address

V

CC

Q

Data Output Power Supply (3.3V)

RAS Row Address Strobe

V

SS

Q

Data Output Ground (0V)

CAS Column Address Strobe NC No Connection

WE Write Enable

Note: T he same power supply voltage must be provided to every VCC pin and VCCQ pin.

The same GND voltage level must be provided to every V

SS

pin and VSSQ pin.

44-Pin Plastic TSOP (II)

(K Type)

1 2 3 4 5

9 10 11 12 13

42 41 40 39 38

DQ1

DQ2

DQ3

V

CC

V

SS

DQ8

DQ7

NC NC

DQM

A9

6

7

8

14 15

RAS

DQ4

19 20 21 22 23

A0 A1 A2 A3

A11

16 17 18

24

25

CS

WE

A10

CAS

44 43

DQ6

DQ5

37 36

32 31 30 29 28 A8

A7 A6 A5 A4

35 34 33

CLK CKE NC

27 26

V

SS

V

CC

NC

V

CC

(Q)

V

SS

(Q) VSS(Q)

V

CC

(Q)

NC

V

SS

(Q)

V

CC

(Q)

V

SS

(Q)

V

CC

(Q)

MSM56V16800F

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PIN DESCRIPTION

CLK Fetches all inputs at the “H” edge. CS

Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE, UDQM and LDQM.

CKE

Masks system clock to deactivate the subsequent CLK operation. If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is deactivated. CKE should be asserted at least one cycle prior to a new command.

Address

Row & column multiplexed. Row address : RA0 – RA10 Column Address : CA0 – CA8

A11

Slects bank to be activated during row address latch time and s elects bank for prec harge and read/write during column address latch time. A11=”L” : Bank A, A11=”H” : Bank B

RAS CAS WE

Functionality depends on the combination. For details, see the function truth table.

DQM

Masks the read data of two clocks later when DQM is set “H” at the “H” edge of the clock signal. Masks the write data of the s ame clock when DQM is set “H” at the “ H” edge of the clock signal.

DQi Data inputs/outputs are multiplexed on the same pin.

MSM56V16800F

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BLOCK DIAGRAM

Timing

Register

Column

Decoders

Sense

Amplifiers

DQ1

- DQ8

RAS CAS

A0 - A11

Progra-

ming

Register

Bank

Controller

Latency & Burst

Controller

Internal

Col.

Address

Counter

I/O

Controller

Column

Address

Buffers

Internal

Row Address Counter

Row

Address

Buffers

8

Row

Decoders

Row

Decoders

12

Word

Drivers

Word

Drivers

8Mb

Memory

Cells

8Mb

Memory

Cells

Read

Data

Register

Output Buffers

Column

Decoders

Sense

Amplifiers

Input Data

Register

Input

Buffers

CKE

CL

K

CS

WE

DQM

A11

9

12

8

88

8

9

MSM56V16800F

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ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

(Voltages referenced to VSS)

Parameter Symbol Rating Unit

Voltage on Any Pin Relative to V

SS

VIN, V

OUT

-0.5 to VCC + 0.5

V

CC

Supply Voltage VCC, VCCQ

-0.5 to 4.6

V

Storage Temperature

T

stg

-55 to 150

°C

Power Dissipation

P

D

*

600 mW

Short Circuit Current

I

OS

50 mA

Operating Temperature

T

opr

0 to 70 °C

*: Ta = 25°C

Recommended Operating Conditions

(Voltages referenced to VSS = 0V)

Parameter Symbol Min. Typ. Max. Unit

Power Supply Voltage

V

CC

,

VCCQ

3.0 3.3 3.6 V

Input High Voltage

V

IH

2.0

¾

V

CC

+ 0.2

V

Input Low Voltage

V

IL

-0.3 ¾

0.8 V

Capacitance

(VCC = 1.4V, Ta = 25°C, f=1MHz)

Parameter Symbol Min. Max. Unit

Input Capacitance (CLK)

C

CLK

2.5 4 pF

Input Capacitance (RAS, CAS, WE, CS, CKE, DQM, A0-A11)

C

IN

2.5 5 pF

Input/Output Capacitance (DQ1-DQ8)

C

OUT

46.5pF

MSM56V16800F

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DC Characteristics

MSM56V16800F

Condition

8A 8 10

Parameter Symbol

Bank CKE Others Min Max Min Max Min Max

Unit Note

Output High Voltage

V

OH

¾¾

I

OH

= -2.0mA

2.4

¾

2.4

¾

2.4

¾

V

Output Low Voltage

V

OL

¾¾

I

OL

= 2.0mA

¾

0.4

¾

0.4

¾

0.4 V

Input Leakage Current

I

LI

¾¾ ¾-10

10

-10

10

-10

10 µA

Input Leakage Current

I

LO

¾¾ ¾-10

10

-10

10

-10

10 µA

I

CC1

One Bank Active

CKE³V

IH

tCC=min. t

RC

=min.

No Burst

¾

70

¾

70

¾

60 mA 1,2

Average power supply current

(Operating)

I

CC1D

Both Banks Active

CKE³V

IH

tCC=min. t

RC

=min.

t

RRD

=min.

No Burst

¾

105

¾

105

¾

85 mA 1,2

Power supply current (Standby)

I

CC2

Both Banks Precharge

CKE³V

IH

tCC=min.

¾

35

¾

35

¾

30 mA 3

Average power supply current

(Clock Suspension)

I

CC3S

Both Banks Active

CKE£V

IL

tCC=min.

¾

3

¾

3

¾

3mA2

Average power supply current

(Active Standby )

I

CC3

One Bank Active

CKE³V

IH

tCC=min.

¾

40

¾

40

¾

35 mA 3

Power supply current (Burst)

I

CC4

Both Banks Active

CKE³V

IH

tCC=min.

¾

95

¾

90

¾

80 mA 1,2

Power supply current

(Auto-Refresh)

I

CC5

One Bank Active

CKE³V

IH

tCC=min. t

RC

=min.

¾

70

¾

70

¾

60 mA 2

Average power supply current

(Self-Refresh)

I

CC6

Both Banks Precharge

CKE£V

IL

tCC=min.

¾

2

¾

2

¾

2mA

Average power supply current

(Power Down)

I

CC7

Both Banks Precharge

CKE£V

IL

tCC=min.

¾

2

¾

2

¾

2mA

Notes: 1. Measured with outputs open.

2. The address and data can be changed once or left unchanged during one cycle.

3. The address and data can be changed once or left unchanged during two cycles.

MSM56V16800F

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Mode Set Address Keys

CAS Latency Burst Type Burst Length

A6 A5 A4 CL A3 BT A2 A1 A0 BT = 0 BT = 1

0 0 0 Reserved 0 Sequential 0 0 0 1 1 0 0 1 1 1 Interleave 0 0 1 2 2 010 2 010 4 4 011 3 011 8 8 1 0 0 Reserved 1 0 0 Reserved Reserved 1 0 1 Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved 1 1 0 Reserved Reserved 1 1 1 Reserved 1 1 1 Full Page Reserved

Notes: A7, A8, A9, A10 and A11 should stay “L” during mode set cycle.

POWER ON SEQUENCE

1. With inputs in NOP state, turn on the power supply and start the system clock.

2. After the V

CC

voltage has reached the specified level, pause for 200ms or more with the input kept

in NOP state.

3. Issue the precharge all bank command.

4. Apply a CBR auto-refresh eight or more times.

5. Enter the mode register setting command.

MSM56V16800F

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AC Characteristic (1/2)

Note 1,2

MSM56V16800F

8A 8 10

Parameter Symbol

Min. Max. Min. Max. Min. Max.

Unit Note

CL = 3 8

¾

8

¾

10

¾

ns

CL = 2 10

¾

12

¾

15

¾

nsClock Cycles Time

CL = 1

t

CC

20

¾

24

¾

30

¾

ns

CL = 3

¾

6

¾

6

¾

9ns3,4

CL = 2

¾

6

¾

9

¾

9ns3,4Access Time from Clock

CL = 1

t

AC

¾

16

¾

22

¾

27 ns 3,4

Clock High Pulse Time

t

CH

3

¾

3

¾

3

¾

ns 4

Clock Low Pulse Time

t

CL

3

¾

3

¾

3

¾

ns 4

Input Setup Time

t

SI

2

¾

2

¾

3

¾

ns

Input Hold Time

t

HI

1

¾

1

¾

1

¾

ns

Output Low Impedance Time from Clock

t

OLZ

3

¾

3

¾

3ns

Output High Impedance Time from Clock

t

OHZ

¾

9

¾

9

¾

8ns

Output Hold from Clock

t

OH

3

¾

3

¾

3

¾

ns 3

RAS Cycle Time

t

RC

70

¾

70

¾

90

¾

ns

RAS Precharge Time

t

RP

20

¾

20

¾

30

¾

ns

RAS Active Time

t

RAS

48 10

5

48 10

5

60 10

5

ns

RAS to CAS Delay Time

t

RCD

20

¾

20

¾

30

¾

ns

Write Recovery Time

t

WR

8

¾

8

¾

15

¾

ns

RAS to RAS Bank Active Delay Time

t

RRD

20

¾

20

¾

20

¾

ns

Refresh Time

t

REF

¾

64

¾

64

¾

64 ms

Power-down Exit setup Time

t

PDE

t

SI

+1CLK

¾

t

SI

+1CLK

¾

t

SI

+1CLK

¾

ns

Input Level Transition Time

t

T

¾

3

¾

3

¾

3ns

CAS to CAS Delay Time(Min.)

l

CCD

111Cycle

Clock Disable Time from CKE

l

CKE

111Cycle

Data Output High Impedance Time from UDQM, LDQM

l

DOZ

222Cycle

Data Input Mask Time from UDQM, LDQM

l

DOD

000Cycle

Data Input Mask Time from Write Command

l

DWD

000Cycle

MSM56V16800F

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AC Characteristic (2/2)

Note 1,2

MSM56V16800F

8A 8 10

Parameter Symbol

Min. Max Min. Max. Min. Max.

Unit Note

Data Output High Impedance Time from Precharge Command

l

ROH

CL CL CL Cycle

Active Command Input Time from Mode Register Set Command Input (Min.)

l

MRD

333Cycle

Write Command Input Time from Output

l

OWD

222Cycle

Notes:

1) AC measurements assume that tT = 1ns.

2) The reference level for timing of input signals is 1.4V.

3) Output load.

4) The access time is defined at 1.5V.

5) If tT is longer than 1ns, then the reference level for timing of input signals is VIH and VIL.

Output

Z=50

W

50pF (External Load)