OKI MSM54V12222A-40-TS-K, MSM54V12222A-30-TS-K, MSM54V12222A-40JS, MSM54V12222A-30JS Datasheet

OKI Semiconductor

OKI Semiconductor

MSM54V12222A

MSM54V12222A

REVISION-1 1997. 9 . 30

262,214 Words ¥ 12 Bits FIELD MEMORY

GENERAL DESCRIPTION

The OKI MSM54V12222A is a high performance 3M bits, 256K X 12 bits, Field Memory especially de­signed for high-speed serial access applications such as HDTVs, conventional NTSC TVs, VTRs, digital
movies and Multi-media systems. MSM54V12222A is a FRAM for wide or low end use as general com­modity TVs and VTRs, exclusively. MSM54V12222A is not designed for the other use or high end use as
medical systems, professional graphics systems require long time picture storage, data storage systems
and others. More than two MSM54V12222As can be cascaded directly without any delay devices among
the MSM54V12222As. ( Cascading of MSM54V12222A provides larger storage depth or a longer delay.)

Each of the 12-bits planes has separate serial write and read ports that employ independent control clocks
to support asynchronous read and write operations. Different clock rates are also supported that allow
alternate data rates between write and read data streams.

The MSM54V12222A provides high speed FIFO, First-In First-Out, operation without external refreshing:
MSM54V12222A refreshes its DRAM storage cells automatically, so that it appears fully static to the
users.
Moreover, fully static type memory cells and decoders for serial access enable the serial access operation
refresh free, so that serial read and/or write control clock can be halted high or low for any time as long as
the power is on. Internal conflicts of any memory access and refreshing operation are prevented by
special arbitration logic.

The MSM54V12222A's function is simple like that of a digital delay device whose delay-bit-length is easily
set by reset timing. The delay length, number of read delay clocks between write and read, is determined
by externally controlled write and read reset timings.

Additional SRAM serial registers, or line buffers, for the initial access of 256X12 bits enable high speed
first-bit-access with no clock delay just after the write or read reset timings.

In addition to cascade capability, MSM54V12222A has write mask function or input enable function (IE),
and read- data skipping function or output enable function(OE). The differences between write enable
(WE) and input enable (IE), and between read enable (RE) and output enable (OE) are that WE and RE
can stop serial write/read address increments but IE and OE can not stop the increment when write/read
clocking is continuously applied to MSM54V12222A. The input enable (IE) function allows the user to
write into selected locations of the memory only, leaving the rest of the memory contents unchanged. This
facilitates data processing as "picture in picture" on a TV screen simply.

The MSM54V12222A is similar in operation and functionality to OKI 1M bits Field memory MSM51V4222C
and 2M bits Field memory MSM51V8222A. Three MSM51V4222Cs or one MSM51V4222C plus one
MSM51V8222A can be replaced simply by one MSM54V12222A.

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MSM54V12222A

OKI Semiconductor

FEATURES

• Signale power supply : 3.3V±0.3V

• 512 Rows X 512 Column X 12 bits

• Fast FIFO (First-In First-Out) Operation

• High Speed Asynchronous Serial Access

• Read/Write Cycle Time 30 ns/40 ns

• Access Time 30 ns/35 ns

• Direct Cascading Capability

• Write Mask Function (Input Enable Control)

• Data Skipping Function (Output Enable Cotrol)

• Self Refresh (No refresh control is required)

• Packageoptions:

44Pin 400mil plastic TSOP (Type II ) (TSOP II 44-P-400-0.80-K) (Product:MSM54V12222A-xxTS-K)
40Pin 400mil Plastic SOJ (SOJ40-P-400-1.27) (Product:MSM54V12222A-xxJS)

xx indicates speed rank.

PRODUCT FAMILIES

Family Access Time (Max.) Cycle Time (Min.) Package

MSM54V12222A-30-TS-K
MSM54V12222A-40-TS-K
MSM54V12222A-30JS 30 ns30 ns
MSM54V12222A-40JS 40 ns35 ns

30 ns30 ns

400 mil 44-pin TSOP (II)

40 ns35 ns

400 mil 40-pin SOJ

2

OKI Semiconductor

PIN CONFIGURATION (TOP VIEW)

V

SS

1

D

IN11

2

D

IN10

3

NC

4

DIN9

5

DIN8

6

DIN7

7

DIN6

8

NC

9

DIN5

10
11

IN

4

D

IN

3

D

12

DIN2

13

NC

14

DIN1

15

DIN0

16

SWCK
RSTW

NC

VWE

IE

V

CC

17
18
19
20
21
22

44
43
42
41

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

V

SS

D

OUT

D

OUT

NC
D

OUT

D

OUT

D

OUT

D

OUT
CC

V
D

OUT

D

OUT
OUT

D
D

OUT

V

SS

D

OUT

D

OUT

SRCK
RSTR
NC
RE

OE
V

CC

11
10

9
8
7
6

5
4
3
2

1

SWCK

0

RSTW

MSM54V12222A

V

SS

1

NC

2

D

IN

11

3

IN

10

D

D
D
D
D

4

D

IN

9

5

D

IN

8

6

IN

7

D

7

D

IN

6

8

D

IN

5

9

D

IN

4

10

IN

3

11

IN

2

12

IN

1

13

IN

0

14

15
16

WE

17

IE

18 23

NC

19

V

CC

20

40
39
38
37
36
35
34
33
32
31
30
29
28

27
26

25

24

22
21

V

SS

V

CC

D

OUT
OUT

D
D

OUT

D

OUT
OUT

D
D

OUT

D

OUT

D

OUT

D

OUT
OUT

D
D

OUT

D

OUT

SRCK
RSTW
RE
OE
V

SS

V

CC

11
10
9
8
7
6

5
4
3

2
1
0

44PIN Plastic TSOP (II)

(K Type)

Pin Name Function
SRCK Serial Read Clock
SWCK Serial Write Clock
WE Write Enable
RE Read Enable
IE Input Enable
OE Output Enable
RSTW Write Reset Clock
RSTR Read Reset Clock
Din0-11 Data Input
Dout0-11 Data Output
Vcc Power Supply(3.3V)
Vss Ground (0V)
NC No Connection

40PIn Plastick SOJ

3

4

OKI Semiconductor

MSM54V12222A

Dout (X12)

Data - out

Buffer (X12)

OE RE

RSTR SRCK

Serial Read Controller

512 Word Serial Read Register (X12)

Read line buffer
Low-Half (X12)

Read line buffer
High-Half (X12)

256 (X12)

256K (X12)

Memory

Array

X
Deco­der

71Words

Sub-Register (X12)

Read/Write
and Refresh
Controller

Clock

Oscillator

Write line buffer
Low-Half (X12)

Write line Buffer
High-Half (X12)

512 Word Serial Write Register (X12)

Data-in

Buffer (X12)

Din (X12)

Serial Read Controller

IE WE RSTW

SWCK

71 Words

Sub-Register (X12)

256 (X12)

256 (X12) 256 (X12)

VBB

Generator

BLOCK DIAGRAM

OKI Semiconductor

OPERATION

Write Operation

The write operation is controlled by tree clocks, SWCK, RSTW, and WE. Write operation is accomplished
by cycling SWCK and holding WE high after write address pointer reset operation or RSTW.

Each write operation, which begins after RSTW, must contain at least 80 active write cycles, i.e. SWCK
cycles while WE is high. To transfer the last data, which at that time are stored in the serial data registers
attached to DRAM array, to the DRAM array, an RSTW operation is required after the last SWCK cycle.

Note that every write timing of MSM54V12222A is delayed by one clock compared wih read timings for
easy cascading without any interface delay devices.

Write Reset : RSTW

The first positive transition of SWCK after RSTW going high resets the write address counters to zero.
RSTW setup and hold times are referenced to the rising edge of SWCK. Because the write reset function
is solely controlled by SWCK rising edge after high level of RSTW, the states of WE and IE are don't care
in the write reset cycle.

MSM54V12222A

Before RSTW may be brought high again for a further reset operation, it must have been low for at least
two SWCK cycles.

Data Inputs : Din0-11
Write Clock : SWCK

The SWCK latches the input data on chip when WE is high and also increments the internal write address
pointer. Data-in setup time, tDS and hold time, tDH, are referenced to the rising edge of SWCK.

Write Enable : WE

WE is used for data write enable/disable control. WE high level enables the input, and WE low level
disables the input and holds the internal write address pointer. There are no WE disable time (low) and
WE enable time (high) restrictions because MSM54V12222A is fully static operation as long as power is
on. Note that WE setup and hold times are referenced to the rising edge of SWCK.

Input Enable : IE

IE is used to enable/disable writing into memory. IE high level enables writing. The internal write address
pointer is always incremented by cycling SWCK regardless of IE level. Note that IE setup and hold times
are referenced to the rising edge of SWCK.

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