OKI MSM548331TS-K Datasheet

E2L0037-17-Y1

¡ Semiconductor MSM548331

¡ Semiconductor

This version: Jan. 1998

Previous version: Dec. 1996

MSM548331

222,720-Word ¥ 12-Bit Field Memory

DESCRIPTION

The MSM548331 is a 2.7-Mbit, 768 bits ¥ 290 lines, Field Memory. Access is done line by line. The line address must be set each time a line is changed. More than two MSM548331s can be cascaded directly without any delay devices between them. Cascading MSM548331s provides larger capacity and longer delay. X serial address input enables random initial address setting of serial access in a page. Other than the random address setting, MSM548331 has several types of address set modes such as line hold, address jump to initial address and line increment. Self refresh function releases the MSM548331 from being applied external refresh control clocks even though it contains dynamic type memory cells. MSM548331 has write mask function or input enable function (IE), and read-data skipping function or output enable function (OE). The MSM548331 is especially designed for digital TVs and VTRs for consumer use and video cameras. The MSM548331 is not designed for high end use in such applications as medical systems, professional graphics systems which require long term picture storage, data storage systems and others.

FEATURES

• 768 ¥ 290 ¥ 12-bit configuration

• Line by line access

• X serial address inputs for random serial initial bit address

• Asynchronous operation

• Serial read and write cycle times Read cycle: 30 ns Write cycle: 30 ns

• Low operating supply voltage: 3.3 V ±0.3 V

• Self-refresh

• Various address reset mode for picture processing

• Write mask function (Input enable control)

• Data skipping function (Output enable control)

• Package:

44-pin 400 mil plastic TSOP (Type II)

(TSOPII44-P-400-0.80-K) (Product : MSM548331TS-K)

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¡ Semiconductor MSM548331

PIN CONFIGURATION (TOP VIEW)

DIN5 DIN4 DIN3 DIN2 DIN1 DIN0

RCLK

RXAD

RADE/RX

OE DO0 DO1

DO2 DO3

DO4 DO5

1 2 3 4 5 6 7 8 9

DIN6

DIN7

DIN8

DIN9

DIN10

DIN11

WCLK

WXAD

WADE/RX

WR/TR 11RR 34 WE 12RXINC 33 WXINC 13 14 15 16 17 18 19 20 21 22

32 31 30 29 28 27 26 25 24 23

DO11

DO10

DO9

DO8

DO7

DO6

44-Pin Plastic TSOP (

(K Type)

II)

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¡ Semiconductor MSM548331

Pin Name

RCLK Read Port, Serial Read ClockRead Port, X Serial Address Strobes

RE Read Port, Read Enable

DO0 - 11 Read Port, Data Output—

RR —Read Port, Address Reset Mode Enable

RXINC —Read Port, X Address Increment

RADE/RX —

RXAD —Read Port, X Serial Address Data

OE Output Enable—

WCLK Write Port, Serial Write ClockWrite Port, X Serial Address Strobes

WE Write Port, Write Enable

DIN0 - 11 Write Port, Input Data—

WR/TR Write Port, Write Data Transfer

WXINC —Write Port, X Address Increment

WADE/RX —

WXAD —Write Port, X Serial Address Data

IE Input Enable—

Read Port, X Address Input Enable

Read Port, X Address Reset

Write Port, Address Reset Mode Enable

Write Port, X Address Input Enable

Write Port, X Address Reset

—

Power Supply Voltage (3.3 V)

Function

Serial Read/Write CycleAddress Setting Cycle

Ground (0 V)

Note: Same power supply voltage level must be provided to every VCC pin.

Same ground voltage level must be provided to every VSS pin.

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BLOCK DIAGRAM

WCLK

Refresh Counter

Write Buffer

Write Register

Memory Cell Array

768 ¥ 290 ¥ 12 bits

Read Register

OUT

Buffer

RCLK RE OE

DIN0 to DIN11

DO0 to DO11

WE WCLK IE

Memory

Controller

Read

Address Control

Write

Address Control

RCLK

WADE/RX

RADE/RX

WXAD

RXAD

WR/TR

WXINC

RXINC

Generator

X-Address

Decoder

¡ Semiconductor MSM548331

PIN FUNCTION

READ RELATED

RCLK : Read Clock

RCLK is the read control clock input. Synchronized with RCLK's rising edge, serial read access from read ports is executed when both RE and OE are high. The internal counter for the serial read address is incremented automatically on the rising edge of RCLK. In a read address set cycle, all the read address bits which were input from RXAD pin are stored into internal address registers synchronized with RCLK. In this address set cycle, RADE/RX must be held high and RR must be held low. In the read address reset cycle, various read address reset modes can be set synchronously with RCLK. These reset cycles work to replace complicated serial address control which requires many RCLK clocks with a simple reset cycle control requiring only a single RCLK cycle. It greatly facilitates memory access.

RE : Read Enable

RE is a read enable clock input. RE enables or disables both internal read address pointers and dataout buffers. When RE is high, the internal read address pointer is incremented synchronously with RCLK. When RE is low, even if the RCLK is input, the internal read address pointer is not incremented.

OE : Output Enable

OE is an output enable clock input. OE enables or disables data-outs. OE high level enables the outputs. The internal read address pointer is always incremented by cycling RCLK regardless of OE level.

DO0-11 : Data-Outs

DO0-11 are serial data-outs. Data is output synchronously with RCLK when OE is high. The output enable/disable operation through OE input is performed synchronously with OE and asynchronously with RCLK.

RR : Read Reset

RR is a read reset control input. Read address reset modes are defined when RR level is high according to the "FUNCTION TABLE for read".

RXINC : Read X Address Increment

RXINC is a read X address (or line address) increment control input. In the read address reset cycle, defined by RR high, the X address (or line address) is incremented by 1 when RXINC is pulled high with RADE/RX low.

RADE/RX : Read Address Enable/Read X Address Reset Logic Function

RADE/RX is a dual function control input. RADE, one of the two functions of RADE/RX, is a read address enable input. In the read address set cycle, defined by RR high, X address (or line address) input from the RXAD pin are latched into internal read X address register synchronously with RCLK. RX, the second function of RADE/RX, works as an element to set read X address (or line address) reset mode. In an address reset mode cycle, defined by RR high, read X address is reset to 0 when RADE/RX is pulled high with RXINC low.

RXAD : Read X Address

RXAD is a read X address (or line address) input. RXAD specifies the line address. 9 bits of read X address data are input serially from RXAD.

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¡ Semiconductor MSM548331

WRITE RELATED

WCLK : Write Clock

WCLK is a write control clock input. Synchronized with WCLK's rising edge, serial write access into write ports is executed when WE is high and IE is high. According to WCLK clocks, the internal counter for the serial address is incremented automatically. In a write address set cycle, all the write addresses which were input from WXAD are stored into internal address registers synchronously with WCLK. In this address set cycle, WADE/RX must be held high and WR/TR must be held low. In the write address reset cycle, various write address reset modes can be set synchronously with WCLK. These reset cycles replace complicated serial address control with simple reset cycle control which requires only one WCLK cycle. It greatly facilitates memory access.

WE : Write Enable

WE is a write enable clock input. WE enables or disables both internal write address pointers and data-in buffers. When WE is high, the internal write address pointer is incremented synchronously with WCLK. When WE is low, even if WCLK is input, the internal write address pointer is not incremented.

DIN0-11 : Data-Ins

DIN0-11 are serial data-ins. Corresponding data-in-buffers are masked by IE.

WR/TR : Write Reset/Write Transfer

WR/TR is a write reset control input. Write address reset modes are defined when WR/TR level is high according to the "FUNCTION TABLE for write". When the write operation on a line is terminated, be sure to perform a write transfer operation by WR/TR in order to store the written data in the write register to corresponding memory cells.

WXINC : Write X Address Increment

WXINC is a write X address (or line address) increment control input. In the write address reset cycle, defined by WR/TR high, the write X address (or line address) is incremented when WXINC and WADE/RX are high.

WADE/RX : Write Address Enable/Write X Address Reset Logic Function

WADE/RX is a dual functional control input. WADE, one of the two functions of WADE/RX, is a write address enable input. In the write address reset cycle, defined by WR/TR high, X address (or line address) input from WXAD is latched into internal write X address register synchronously with WCLK.

WXAD : Write X Address

WXAD is a write X address (or line address) input. WXAD specifies line address. 9 bits of write X address data are input serially from WXAD.

IE : Input Enable

IE is an input enable which controls the write operation. When IE is high, the input operation is enabled. When IE is low, the write operation is masked. When WE signal is high, and IE low, the internal serial write address pointer is incremented on the rising edge of WCLK without actual write operations. This function facilitates picture in picture function in a TV system.

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OPERATION MODE

Write

1. Write operation Before the write operation begins, X address (or line address) must be input to set the initial bit address for the following serial write access. When WE and IE are high, a set of serial 12bit -width write data on DIN0-11 is written into write registers attached to the DRAM memory arrays temporarily on the rising edge of WCLK. Following 12-bit-width serial input data is written into the memory locations in the write register designated by an internal write address pointer which is advanced by WCLK. This enables continuous serial write on a line. When write clock WCLK and read clock RCLK are tied together and are controlled by a common clock or CLK, more than two MSM548331s can be cascaded directly without any delay devices between the MSM548331s because the read timing is delayed by one CLK cycle to the write timing. When the write operation on a line is terminated, be sure to perform a write transfer operation by WR/TR in order to store the written data in the write registers to the corresponding memory cells in the DRAM memory arrays.

2. Write address pointer increment operation The write address pointer is incremented synchronously with WCLK when WE is high.

When WE and IE are high, the write operation is enabled. If IE level goes low while WCLK is active, the write operation is halted but the write address pointer will continue to advance. That is, IE enables a write mask function. When WE goes low, the write address pointer stops without WCLK.

Read

1. Read operation Before the read operation begins, the X address (or line address) must be input for setting initial bit address for the following serial read access. When both RE and OE are high, a set of serial 12-bit-width read data on DO0-11 pins is read from read registers attached to DRAM memory arrays on the rising edge of RCLK. Each access time is specified by the rising edges of RCLK.

Relationship between the WE and IE input levels, Write Address pointer, and data input status

WCLK Rise

—

Internal Write Address Pointer

Incremented

Stopped

Data Input

Inputted

Not Inputted

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