OKI MR27V6466F Technical data

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PEDR27V6466F-01-08

1

Semiconducto

MR27V6466F

4,194,304-Word x 16-Bit or 2,097,152-Word x 32-Bit Synchronous One Time PROM

GENERAL DESCRIPTION

The MR27V6466F is a 64 Mbit One Time Programmable Synchronous Read Only Memory whose configuration
can be electrically switched between 4,194,304 x 16 bit (word mode) and 2,097,152 x 32 bit (double word mode)

by the state of the

3.3 V power supply.

FEATURES ON READ

• 3.3 V power supply

• LVTTL compatible with multiplexed address

• Dual electrically switchable configuration
4M x 16 (word mode) / 2M x 32 (double word mode)

• All inputs are sampled at the rising edge of the system clock.

• High speed read operation
100 MHz : CAS Latency = 5, 6 tRCD min: 2 clock cycles

66 MHz : CAS Latency = 5, 6 tRCD min: 2 clock cycles
50 MHz : CAS Latency = 4, 5, 6 tRCD min: 1 clock cycles

Burst length (4, 8)
Data scramble (sequential, interleave)

• DQM for data out masking

• No Precharge operation is required. No Refresh operation is required.

• No power on sequence is required.
Mode register is automatically initialized to the default state after power on.
“Row Active” or “Mode Register Set” command is applicable as the first command just after power on.

• Single Bank operation

• Package: TSOP(2)86-P-400-0.50-K (Product Name : MR27V6466FTA)

WORD pin. The MR27V6466F supports high speed synchronous read operation using a single

This version: Jul. 2001
Previous version: Jun. 2001

Preliminary

FEATURES ON PROGRAMMING

• 8.0 V programming power supply

• Programming algorithm is compatible with conventional asynchronous OTP.
MR27V6466F can be programmed with conventional EPROM programmers.
Synchronous Burst read or Static Programming Operation is selected by the state of STO pin.

High STO level enables full static programming. (Program, Program Verify, Asynchronous Read)
Low STO level enables synchronous burst read.

Exclusive 86-pin socket adapters are available from OKI to support programming requirements.

The socket adapter is used on a 48-DIP socket on the programmer.
The socket adapter for 64M synchronous OTP is distinguished from the socket adapter for 32M SOTP.
The socket adapter is designed with the STO pin connected to V
conventional OTP.

EPROM programmer must have the algorithm for MR27V6466F on the exclusive socket adapter.

*Device damage can occur if improper algorithm is used.

• Programming with address multiplexed input is also available.

• High speed programming
25 µs programming pulse per word allows high speed programming.

in order to program MR27V6466F as

CC

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1

r

r

r

r

R

C

C

AMPX

O

Semiconductor

BLOCK DIAGRAM

A0

|

A12

PEDR27V6466F-01-08

MR27V6466F

Memory Cell Array

Latch

Row Address

Row

Decode

2 M x 32 or 4 M x 16

Row Select

Column Select

CS

AS

AS

MR

WORD

Address Buffer

Command

Controller

Mode

Register

CLK Buffer

CKE

CLK

Latch

Column Address

Program Mode

Controller

E

E

Column

Decoder

Burst sequence

Controlle

DQ23 to DQ31

STO

CAP0 to CAP8

Sense Amplifier
& Program Bias

Data Output

Latch

Data Output

Selecto

Data Output / Input Buffer

& Data Output / Address Buffer

DQ16 to DQ22

Data Input

Buffe

DQ0 to DQ15

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1

MR

CAS

RAS

CS

CAS

RASDCWORD

CEO

Semiconductor

PIN CONFIGURATION

PEDR27V6466F-01-08

MR27V6466F

TOP VIEW

Programming in Static Operation (STO is high)

Synchronous Read (STO is VSS or open)

V

DQ0

V

CC

DC

DQ1

V

SS

DC

DQ2

VCCQ

DC

DQ3

VSSQ

DC
DC

V

DC
NC

A12
A11
A10

A0
A1
A2

NC

V

NC

DQ4

V

SS

DC

DQ5

V

CC

DC

DQ6

VSSQ

DC

DQ7

V

CC

CAP8

V

V

CC

CC

DQ0

V

Q

Q

CC

DQ16

DQ1

V

Q

Q

SS

DQ17

DQ2

V

Q

CC

DQ18

DQ3

VSSQ

DQ19

1
2
3
4
5
6
7
8

9
10
11
12
13
14

V

CC

CC

DQM

NC

15
16
17
18
19
20

WORD

A12
A11
A10

A0
A1
A2

NC

V

CC

CC

NC

DQ4

Q

Q

V

SS

DQ20

DQ5

Q

VCCQ

DQ21

DQ6

VSSQ

DQ22

DQ7

Q

Q

V

CC

DQ23

V

CC

CC

21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43

86
85
84
83
82
81

80

79

78

77
76

75

74
73
72
71

70

69
68
67

66

65

64
63
62

61

60

59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

V

SS

DQ31
V

Q

SS

DQ15
DQ30
V

Q

CC

DQ14
DQ29
V

Q

SS

DQ13
DQ28

Q

V

CC

DQ12
NC
V

SS

DC
DC
DC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DC
V

SS

DC
DQ27

Q

V

CC

DQ11
DQ26
V

Q

SS

DQ10
DQ25
V

Q

CC

DQ9
DQ24

V

Q

SS

DQ8
V

SS

V

SS

CAP0
V

Q

SS

DQ15
CAP1
V

Q

CC

DQ14
CAP2
V

Q

SS

DQ13
CAP3

Q

V

CC

DQ12
NC
V

SS

V

PP

E

DC
DC
A9
A8
A7
A6
A5
A4
A3
AMPX
V

SS

STO
CAP4

Q

V

CC

DQ11
CAP5
V

Q

SS

DQ10
CAP6
V

Q

CC

DQ9
CAP7
V

Q

SS

DQ8
V

SS

DC (Don’t Care) : Logical input level is ignored. However the pin is connected to the input

buffer of OTP.

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1

Semiconductor

PIN FUNCTION FOR SYNCHRONOUS READ OPERATION

(STO pin is low level or open)

Pin Name Function Description

Must be low for synchronous operation. Internal resistance

STO Static Operation

CLK System Clock All inputs are sampled at the rising edge.

CS Chip Select

CKE Clock Enable

A0 to A12 Address

RAS Row Address Strobe
CAS Column Address Strobe
MR Mode Register Set

DQ0 to DQ31 Data Output

DQM Data Output Masking

WORD x32/x16 Organization Selection

V

CC

V

SS

Power Supply 3.3 V Power supply

Ground

VCCQ Data Output Power Supply 3.3 V Power supply to DQ0-DQ31

VSSQ Data Output Ground

NC No Connection

DC Don't Care Logical input level is ignored.

(around 10k ohms) pulls the input level down to V
pin is open. High level STO enables programming operation
compatible with standard OTPs.

Enables command sampling by the CLK signal with a low level
on the CS input.

Masks internal system clock to freeze the CLK operation of
subsequent CLK cycle. CKE must be enabled for command
sampling cycles. CLK is disabled for two types of operations.

1) Clock Suspend

2) Power Down

Row and column addresses are multiplexed on the same pins.
Row address: RA0 to RA12
Column address: CA0 to CA7 (x32) /CA0 to CA8 (x16)

LSB:CA0(Both x32 and x16)

Functionality depends on the combination.
See the function table.

Data outputs are valid at the rising edge of CLK for read
cycles. Except for read cycles DQn is high-Z state.

Data outputs are masked after two cycles from when high level
DQM is applied.

The WORD pin defines the organization of each read
command to be x16 (word mode) or x32 (double word mode).
High = x32
Low = x16

When WORD is low (x16,word mode) ,DQ16 to DQ31 are

held on High-Z state.

PEDR27V6466F-01-08

MR27V6466F

when this

SS

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1

Semiconductor

PIN FUNCTION FOR PROGRAMMING OPERATION

(STO pin is high level)

Pin Name Function Description

Must be set high for programming operation. Internal

STO Static Operation

AMPX Address Multiplex

A0 to A12 Address Row address input.

RAS Row Address Strobe

CAS Column Address Atrobe

DQ0 to DQ15 Data Input/Output

WORD x32/x16 Organization Selection

CAP0 to
CAP8

Address Input

OE Output Enable

CE Chip Enable

VCC/V

SS

Power Supply/Ground Power and ground for the input buffers and the core logic.

VCCQ/VSSQ Data Output Power/Ground Power and ground for output.

V

pp

Program Power Supply

resistance (around 10 k ohms) pulls the input level down to V
for open state condition to be low level for synchronous read
operation.

When AMPX is low, the addresses are not multiplexed and all
address bits must be supplied to A0 to A12 (Row Address) and
CAP0 to CAP8 (Column Address) simultaneously.

When AMPX is high, multiplexed address inputs are enabled
on A0 to A12.

When AMPX is high, row address is latched at the rising egde
of RAS.

When AMPX is low, input is not used.

When AMPX is high, column address is latched at the rising
egde of CAS.

When AMPX is low, input is not used.

Input of data for programming and output for program verify
and read data.

The WORD pin defines the organization to be x16 (word
mode) or x32 (double word mode).
High = x32
Low = x16
This pin must be set low for programming operation.

When WORD is low, High-Z state on CAP0 to CAP8 is held to
be input pins.
When AMPX is low, column address input.

When AMPX is high, input is not used.

Control signal input for programming.
OE of conventional OTPs.

Control signal input for programming.
Function for programming is associated with conventional
OTPs.

High voltage program power is supplied through V
When V
between V
V

PP

be kept lower than V

is higher than a predetermined voltage level

PP

+ 0.5 V and VCC + 2 V, pin function alters to high

CC

mode. To keep stable static read operation VPP pin must

+ 0.5 V.

CC

PEDR27V6466F-01-08

MR27V6466F

SS

pin.

PP

The persons who design socket adapter or make programming algorithm on the condition of omitting socket adapter

provided with OKI study this table. Other persons can ignore this table.

The functionality of programming must be checked with the specification of socket adapter that will be supplied by
OKI. MR27V6466F on the socket adapter is the same programming functionality as conventional OTPs.

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PEDR27V6466F-01-08

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Semiconductor

MR27V6466F

FUNCTION COMMAND TABLE FOR SYNCHRONOUS READ

N

Command Name Function

Mode Register

Set

Row Active Row Address Latch H X L L H H X RA X L 2

Read Word

(x16)

Read Double

Word (x32)

Burst Stop Burst Stop H X L H H L X X X L 4

Precharge Burst Stop H X L L H L X X X L 4

Clock Suspend

(on Read)

Power Down

(on Active

Standby)

Read Output Output Enable H X X X X X L X X L

Mask Output High-Z Output H X X X X X H X X L

No Operation

Mode Register Set H X L L L L X

Column Address Latch

Trigger Burst Read

Column Address Latch

Trigger Burst Read

Entry HLHXXXX XXL 5

Exit LHXXXXXXXL5

Entry

Exit

Write on SDRAM H X L H L L X X X L

Illegal on SDRAM H H L L L H X X X L

( H = Logical high, L = Logical low, X = Don't Care, L of STO includes pin open due to internal pull down resistor)

expresses the logical level at the simultaneous cycle with a command. )

(CKE

N

N-1

CKE

HXLHLHXCALL3

HXLHLHXCAHL3

HLHXXXXXXL6

LHXXXXXXXL6

HXHXXXX XXL

HXL HHHX XXL

CS

CKE

RAS

CAS

MR

WORD

STO

Add.

DQM

Code XL 1

Note

Notes:

1. Refer to "Mode Register Field Table" for Address Codes, and Mode Transition Chart for operational state.
After power on, any command can be sampled at any cycle in Active Standby state. After "Mode Register

Set" command is sampled, no new command can be accepted for 3 CLK cycles. The

CS input must be

kept high for the 3 CLK cycles to prevent unexpected sampling of a command.

2. The "Row Active" command is effective till new "Row Active" command is implemented.

3. The

WORD input is sampled simultaneously with "Read" command to select data width. A Double Word

Burst (x32) or a Word Burst (x16) is selected by the
condition of constant voltage level on

WORD pin, the organization is fixed to either x16 or x32. "Read"

WORD input for each "Read" command. On

command ends it's implementation by itself at the finishing cycle of the burst read.

4. Since OTP technology uses static sense amplifiers, the "Precharge" command is not required. However,
due to customer request for the similarity of logical input code with SDRAM command, the name of
"Precharge" is adopted. The function of "Precharge" command and "Burst Stop" command is only to stop
the burst read cycles delayed by CAS Latency.

5. Sampled low level CKE disables CLK buffer to suspend internal clock signals at the next rising edge of
CLK. Sampled high level CKE enables internal clock at the next rising edge of CLK.
Low level CKE sampled in the period from the simultaneous cycle with a "Read" command till the end of
the burst read cycle is distinguished with internal command controller from the low level CKE sampled in
Active Standby state, then power is consumed because of data sensing and burst read operation.

6. Low level CKE sampled in Active Standby state cuts power dissipation to be in Power Down state. High
level CKE sampled in Power Down state enables internal CKE to be in Active Standby state with
preserved row address.

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Semiconductor

FUNCTION STATE TABLE FOR SYNCHRONOUS READ

PEDR27V6466F-01-08

MR27V6466F

Current

State

Active

Standby

Read

Power

Down

Clock

Suspend

CS

CKE

H L L L L Code Mode Register Set Mode Register Set Active Standby

H L L H H RA Row Active Row Address Latch Active Standby 1

HLHLHCARead

L H X X X X Power Down Entry Power Down Power Down 2

H L H H L X Burst Stop NOP Active Standby

H L L H L X Precharge NOP Active Standby

H L L L H X NOP NOP Active Standby

H L H L L X NOP NOP Active Standby

H L H H H X NOP NOP Active Standby

H H X X X X NOP NOP Active Standby

H L L L L Code Mode Register Set Illegal

H L L H H RA Row Active Row Address Latch Active Standby 3

HLHLHCARead

L X X X X X Clock Suspend Clock Suspend Entry Clock Suspend 5

HLHHL XBurst Stop

H L L H L X Precharge

H L L L H X NOP NOP Read

HLHLL XNOP NOP Read

HLHHH XNOP NOP Read

H H X X X X NOP NOP Read

H X X X X X Exit Power Down Exit Power Down Active Standby 2

L X X X X X Power Down Power Down Power Down 2

H X X X X X Exit Clock Suspend Exit Clock Suspend Read 5

L X X X X X Clock Suspend Clock Suspend Clock Suspend 5

RAS

CAS

MR

Add.

( H = Logical high, L = Logical low, X = Don't Care)

Command

Action at next clock

cycle or cycles

Column Address Latch

Trigger Burst Read

Column Address Latch

Trigger Burst Read

Stop the Burst Read Cycle

delayed by CAS Latency

Stop the Burst Read Cycle

delayed by CAS Latency

State after the

completion of

the command

Active Standby

after Burst Read

Active Standby

after Burst Read

Active Standby

Active Standby

Note

4

Notes:

1. The latched row address is preserved during any state except another “Row Active” command.

2. Low level CKE sampled in Active Standby state disables internal clock and cuts power dissipation to be in
Power Down state. High level CKE sampled in Power Down state enables internal clock to be in Active
Standby state.

3. To preserve previous “Read” command, the latest “Row Active” command must be implemented at CL­1 clock cycle or later after the previous “Read” command.

4. To preserve previous “Read” command, the latest “Read” command must be implemented at CL-1 clock

cycle or later after the previous “Read” command.

5. Sampled low level CKE in the period of Burst Read disables CLK buffer to suspend internal clock signals
at the next rising edge of CLK. Sampled high level CKE in the Clock Suspend enables internal clock at the
next rising edge of CLK.

7/39

PEDR27V6466F-01-08

1

Semiconductor

MODE REGISTER FIELD TABLE

Address A5 A4 A3 A2 A1 A0

Function CAS Latency Burst Type Burst Length

MR27V6466F

A5 A4 A3 CAS Latency

000 Reserved

001 Reserved

010 Reserved 10 8

0 1 1 4 1 1 Reserved

100 5

101 6

110 Reserved

111 Reserved

A2

0

1

Note:
A7 and A8 must be low during Mode Register Set cycle.
During power on, mode register is initialized to the default state when V
(less than 3.0 V).
The default state of Mode Register is as shown below.

CAS Latency = 5
Burst Type = Sequential
Burst Length = 4

BURST SEQUENCE (BURST LENGTH = 4)

Initial address

A1 A0

0 0 01230123

0 1 12301032

1 0 23012301

1 1 30123210

Sequential Interleave

Type A1 A0 Burst Length

Seq

uential

Interleave 01 4

reaches a specific voltage

CC

00 Reserved

BURST SEQUENCE (BURST LENGTH = 8)

Initial address

A2 A1 A0

0000123456701234567

0011234567010325476

0102345670123016745

0113456701232107654

1004567012345670123

1015670123454761032

1106701234567452301

1117012345676543210

Sequential Interleave

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1

Semiconductor

MR27V6466F

ADDRESSING MAP

(1) WORD = “H”: x32 Organization

Pin Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12

Row Address RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RA8 RA9 RA10 RA11 RA12

Column Address CA0CA1CA2CA3CA4CA5CA6CA7XXXXX

( X = Don’t Care)

(2) WORD = “L”: x16 Organization

Pin Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12

Row Address RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RA8 RA9 RA10 RA11 RA12

Column Address CA0CA1CA2CA3CA4CA5CA6CA7CA8XXXX

( X = Don’t Care)

(3) Programming

Address displayed on
programmer: x16

Device Address: x16
STO = “H”, AMPX = “L”

Address (STO = “L”)
WORD = “L”: x16

Address (STO = “L”)
WORD = “H”: x32

Address displayed on
programmer: x16

Device Address: x16
STO = “H”, AMPX = “L”

Address (STO = “L”)
WORD = “L”: x16

Address (STO = “L”)
WORD = “H”: x32

Ad0 Ad1 Ad2 Ad3 Ad4 Ad5 Ad6 Ad7 Ad8 Ad9 Ad10 Ad11 Ad12

CAP0 CAP1 CAP2 CAP3 CAP4 CAP5 CAP6 CAP7 CAP8 A 0 A 1 A 2 A 3

Note2

Note3

CA0

CA1

Note1 CA 0

Ad13 Ad14 Ad15 Ad16 Ad17 Ad18 Ad19 Ad20 Ad21

A4 A5 A6 A7 A8 A9 A10 A11 A12

RA4 RA5 RA6 RA7 RA8 RA9 RA10 RA11 RA12

RA4 RA5 RA6 RA7 RA8 RA9 RA10 RA11 RA12

CA3 CA4 CA5 CA6 CA7 CA8 RA0 RA1 RA2 RA3

CA2

Note4

Note5

CA1

CA3 CA4 CA5 CA6 CA7 RA0 RA1 RA2 RA3

CA2

Users of MR27V6466F are recommended to study the relationship between "Address displayed on programmer"
and "Address (STO = "L")" ignoring "Device Address: x16, STO = "H"".
The order of data on Synchronous Read operation (STO="L") is checked on this table.
"Device Address : x16, STO = "H"" will be utilized to design socket adapter on programmer or to check boards
designed to mount blank OTP and program OTP on board.
OKI will supply a socket adapter to program MR27V6466F as conventional x16 standard OTP. The users and the
venders of programmer who use the socket adapter can ignore "Device Address: x16, STO = "H"".
The persons who use 32Mbit SOTP and 64Mbit SOTP must be careful to distinguish the socket adapters for
64Mbit from one for 32Mbit. The difference is caused from the additional assignment of column address and 1 bit
shift of row address on 64Mbit SOTP
Note

1. A0 in programmer distinguishes upper word (x16) or lower word (x16) of Double word (x32).

On word (x16) organization the address of device corresponds to the address of programmer.
On double word (x32) organization the address numeral code of device is half of that in programmer, and
output on DQ0 to DQ15 is lower word (A0 = "0") and output on DQ16 to DQ31 is upper word (A0 = "1").

2. CA1 is MSB of burst read on condition of

3. CA2 is MSB of burst read on condition of

4. CA1 is MSB of burst read on condition of

5. CA2 is MSB of burst read on condition of

WORD = "L" and BL = 4.
WORD = "L" and BL = 8.
WORD = "H" and BL = 4.
WORD = "H" and BL = 8.

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PEDR27V6466F-01-08

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Semiconductor

MR27V6466F

READ OPERATIONS

Clock (CLK)

The clock input enables MR27V6466F to sample all the inputs, to control internal circuitry, and to turn on output
drivers. All timings are referred to the rising edge of the clock. All inputs with high level CKE and low level

should be valid at the rising edge of CLK for proper functionality.

Clock Enable (CKE)

The clock enable (CKE) turns on or switches off the admission of the clock input into the internal clock signal lines.
All internal circuits are controlled by the internal clock signal to implement each command. High level CKE
sampled at CKE
CKE

cycle. Low level CKE sampled at CKE

N

clock cycle enables the admission of the rising edge of clock input into internal clock line at

N-1

cycle suspends the rising edge of CLK at CKEN cycle. The

N-1

suspension of internal clock signal in all state ignores new input except CKE, and holds internal state and output
state. Low level CKE in Active Standby state, defined as Power Down state, cuts power dissipation. In Power
Down state, the contents of mode resister and Row Address are preserved. After recovering high level CKE to exit
from Power Down state, MR27V6466F is in Active Standby state. Low level CKE just after the sampling of
"Read" command till the completion of burst read, defined as Clock Suspend, makes read operation go on with
power dissipation. Any command operation does not interrupted by arbitrary low level CKE. Sampling command
with low level CKE preceded with high level CKE is illegal.

CS

Power On

Apply power and start clock considering following issues.

1. During power on, Mode Register is initialized into the default state.

(default state: CAS latency = 5, Burst Type = Sequential, Burst length = 4)

2. After power on, MR27V6466F is in Active Standby state and ready for "Mode Register set" command or

"Row Active" command. MR27V6466F requires neither command nor waiting time as power on sequence
after starting CLK input in order to start "Row Active" command to read data.

3. It is recommended in order to utilize default state of Mode Register that

MR and CKE inputs are maintained

to be pulled up during power on till the implementation of the first "Row Active" command. After above
power on, "Row Active" command and "Read" command can be started immediately on default Mode
Register state.

4. It is recommended that DQM input is maintained to be pulled up to prevent unexpected operation of output

buffers.

Organization Control

The organization of data output (DQ0~DQ31) depends on the logical level on
"Read" command. High level sampling of
of

WORD derives word mode (x16) output. Constant WORD level input brings consistent organization.

WORD derives double word mode (x32) output and low level sampling

WORD at the input timing of each

MODE Register

Mode register stores the operating mode of MR27V6466F. Operating modes are consisted with CAS latency,
Burst Type and Burst Length. Registration of RAS latency is not required, because RAS to CAS delay (tRCD) is
requested independently of system clock. When the contents of Mode register are required to be changed for the
next operation, "Mode Register Set" command can be sampled at any cycle in Active Standby state. After "Mode

Register Set" command is sampled,

CS must be fixed to logical high level to prevent sampling of new command

input during succeeding three clock cycles.
Refer to Mode Resister Field Table for the relation between Operation modes and input pin assignment

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Semiconductor

MR27V6466F

READ OPERATIONS

CAS Latency

After sampling "Read" command, MR27V6466F starts actual data read operation with sense amplifiers, and
transmits the data from sense amplifiers to data out buffers to start burst read. This flow of sequential functionality
takes time as clock cycles defined as CAS latency (CL). CAS latency can be set in Mode Register between from
four cycles to six cycles. In this sequence (from sampling "Read" command to start of driving data bus), sense
amplifiers consume maximum current flow. The detailed sequence is as shown below.

1. Fix the column address of memory matrix driver. Row address is already fixed with "Row Active" command.

(at 1st cycle)

2. Read the data of selected memory cells with sense amplifiers.

3. Deliver the data detected with sense amplifiers to the register for data output latch.

4. Couple selectively the section of the register storing each (double) word to output buffers.

5. Enable the output buffers to drive data bus (at CL-1 cycle).

6. Data the output on data bus can be sampled at the rising edge of system clock at CL cycle.

New "Row Active" command or new "Read" command can be sampled to perform gapless burst read at CL-1
clock cycle of the last "Read" command. New command preceeding CL-1 cycle interrupts sense amplifiers to read
the data at the selected memory cells of the last "Read" command. Interrupted "Read" command perishes or
outputs invalid data before the starting of the data burst of new "Read" command. Refer to the timing chart of
"Burst Read/Interrupt I" and "Burst Read/Interrupt II".

Burst Read

Data outputs are consecutive during the cycle number defined as Burst Length (BL). The latest burst read is
completed unless any interruption such as "Precharge" command stops the sequential data output. Burst Length is
set in Mode Register as either four or eight. After sampling of "Read" command, the first output can be read at the
cycle delayed by CAS latency. Burst Type is also stored in Mode register as either sequential or interleave. The
output buffers go into a high impedance state after burst read sequence is finished, unless a new "Read" command
has been sampled to perform gapless read or preemptive read. Burst read can be interrupted by "Burst Stop"
command or "Precharge" command at the cycle delayed by CAS latency from the command. On condition that
reading data with sense amplifiers of preceding "Read" command is not interrupted by new "Read" command or
"Row active" command, burst read of preceding "Read" command is continued regularly until the burst data
sequence of the new "Read" command starts. The new (latest) burst data sequence always starts regularly.

DQM

Input level on DQM is sampled at the rising edge of system clock to mask data at two cycles later. The output of
masked data is in a high-Z state.

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1

Semiconductor

Read Operation

Mode transfer chart

PEDR27V6466F-01-08

MR27V6466F

CKE = LCKE = H

Row Active

Note:

Mode Register Set

Entry

Active Standby

Exit

Entry

Read

DQM

Burst Stop

Precharge*

* All operation of “Precharge” command is to stop burst read.

Exit

: passing command

Power Down

Clock Suspend

: state can be kept for any duration

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