OKI ML87V5002 User Manual

OKI Semiconducto

FEDL87V5002-01

Issue Date: Sep. 1, 2005

ML87V5002

Audio Delay IC with Built-in 2-M bi t DRAM

GENERAL DES CRI PTIO N

The ML87V5002 has been developed for solving “Lip-sync problems” in DVD systems, hard disc recording devices, digital TVs and Home Theater Systems. The ML87V5002 can delay the digital audio signal of each of eight channels by setting each register. The ML87V5002 is suitable for synchronizing sounds with motions when loads are too heavy for DSP to control audio delay. The ML87V5002 do es not require a ny e xternal memo ry fo r the audio de lay bec ause the ML87V5002 has a built-i n 2-Mbit DRAM. The maximum delay time is, for example, 341.3 ms at 48 kHz in 8-ch mode and 1.365 sec at 48 kHz in 2-ch mode. Supporting two to eight audio channels; the ML87V5002 is suitable for applications ranging from simple stereo systems to multi-channel systems. The granularity of the delay time is the sampling period, or Ts. The delay time of each channel can be set in steps of Ts. The ML87V5002 i nterface s to mo st audio LS Is si nce the ML 87V5002 sup ports ge neral digi tal audio fo rmats, such

S, right justified, and left justified. In addition, suitable digital audio formats can be selected as each of the

as I input an d output formats.

FEATURES

• Digital audio delay control: The digital audio signals input from the DI0-DI3 pins are delayed for specific

delay times set by an external device and are output from the DO0-DO3 pins.

• No external memory: No external memory is required for the delay because the 2-Mbit DRAM is included.

• Three digital-audio formats: I

• Input/output format settings: I

and output formats.

• Data bit lengths: 16/20/24/32 bits

• Wide range sampling frequencies: 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, and 192 kHz

• Maximum audio delay time:

The maximum delay time (when the audio data length is 16 bits)

- 1.365 sec (48 kHz, 2-ch mode)

- 682.5 ms (96 kHz, 2-ch mode)

- 341.3 ms (192 kHz, 2-ch mode)

- 341.3 ms (48 kHz, 8-ch mode)

- 170.7 ms (96 kHz, 8-ch mode)

- 85.3 ms (192 kHz, 8-ch mode)

• Standard host interface: I

• Minimum delay time step: The granularity of delay time is Ts.

• Independent delay time setting: The delay time of each channel can be set.

• Genera l power supply voltage: 3.3 V ±0.3V

• 5V tolerant I/O: Audio interface inputs, I

• Package:

32-pin plastic TSOP type I (TSOP(1)32-P-0814-0.50-1K)

Note:

• System clock requirements

- Frequency The frequency of the system clock sh ould be 128 times the sampling frequen cy or more. When the sampling frequency is 192 kHz, be sure to set the system clock frequency at 128 times the sampling frequency.

- Phase The system clock should be synchronized with LRCK and the BCK. In synchronized condition, the phase vari ation is accep table.

S, right justified and left justified formats.

S, right justified, or left justified format can be selected as each of the input

C slave interface is supported.

C, and INT are tolerant to 5 V.

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BLOCK DIAG RAM

LRCKI0-3

BCKI0-3

DI0-3

Input Interface

Block

Input Timing

Control

SDA

SCL

INT

Host Interface

Block

(I2C)

PIN CONFIGURATION (TOP VIEW)

VSS

SYSCLK

LRCKI0

BCKI0

DI0

LRCKI1

BCKI1

DI1

VCC

LRCKI2

BCKI2

DI2

LRCKI3

BCKI3

DI3

VSS

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

32-Pin Plastic TSOP Type I

Through-Mode Setting

2-Mbit DRAM

DRAM

Control

Output Interface

Block

Output Timing

Control

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

ML87V5002

LRCKO BCKO DO0-3

SYSCLK RESET

VCC LRCK0 BCK0 DO0 DO1 DO2 DO3 VSS SDA SCL INT RESET MODE0 MODE1 MODE2 VCC

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PIN DESCRIPTION

Pin Symbol I/O Description

6 10 13

7 11 14

8 12 15 31 LRCKO O The LRCK output pin of the output interface

30 BCKO O The BCK output pin of the output interface

29 28 27 26 20 SCL I The clock i nput pi n of I2C (SCL) 24 SDA I/O The address data pin of I2C (SDA) 22 INT O The output pin for the interrupt signal to the host CPU

2 SYSCLK I The input pi n of syst em cl ock

21 RESET I The reset pin of the ML87V5002

20 19 18

9,17,32 VCC PW Power supply 1,16,25 VSS PW Ground

LRCKI0 LRCKI1 LRCKI2 LRCKI3

BCKI0 BCKI1 BCKI2 BCKI3

DI0 DI1 DI2 DI3

DO0 DO1 DO2 DO3

MODE0 MODE1 MODE2

Note:

The equal supply voltage should be applied to each VCC pin. The equal supply voltage should be applied to each VSS pin. The input pins and I/O pins are tolerant to 5 V. The output pins support 3.3 V and should not be connected to signal lines with voltages exceeding the supply voltage (VCC).

The LRCK inputs of the input interface In the 2-channel mode, LRCKI0 to LRCKI3 correspond to DI0 to DI3,

respectively. The polarity of LRCKI can be set by the internal register.

I The BCK inputs of the input interface

In the 2-channel mode, BCKI0 and BCKI3 correspond to DI0 to DI3, respectively.

The number of B CK pulses in the 1LRC K should be 2× the number of the input bits or more.

I The data input pins of the input i nterface

The data is latched in at the rising edges of BCKI0-3.

The polarity of LRCKO can be set by the internal register.

In the internal generation mode, the number of BCK pulses in 1LRCK can be set by the internal register.

O The data output pins of the output interface

The data is output at the fal ling edge of BCKO.

Open drain output

The system clock should be synchronized with LRCKI and BCKI and the frequency should be 128 times the sampling f r equency or more.

Reset is continued while this pin is low.

I I2C address setting pins

ML87V5002

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ML87V5002

ABSOLUT E MAXIMUM RATINGS

Parameter Symbol Condition Rating Value Unit Power Supply Voltage VCC Ta = 25°C −0.3 to +4.6 V Input Voltage VI Ta = 25°C −0.3 to +6.0 V Short Circuit Output Current IOS Ta = 25°C 50 mA Power Dissipation PD Ta = 25°C 1 W Operating Temperature T Storage Temperature T

Note: Stressing the device beyond the “ABSOLUTE MAXIMUM RATINGS”, even momentarily, may cause

permanent damage.

 0 to 70 °C

opr

 −50 to +150 °C

stg

RECOMMENDED OPERAT IN G CO NDI T I O NS

Parameter Symbol Min. Typ. Max. Unit Power Supply Voltage VCC 3.0 3.3 3.6 V Power Supply Voltage VSS 0 0 0 V Operating Temperature Ta 0  70 °C

PIN CAPACITANCE

(VCC = 3.3 V ±0.3V, f = 1 MHz, Ta = 25°C)

Parameter Symbol Min. Max. Unit Input Capacitance Ci  7 pF Input Output Capaci t ance Cio  7 pF Output Capacitance Co  7 pF

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40

16



6

8

6

8



OKI Semiconductor

ML87V5002

ELECTRICAL CHARACTERISTICS

DC Characte ristics

(Ta = 0 to 70°C, VCC = 3.3 V ±0.3V, VSS = 0 V)

Parameter Symbol Condition Min. Max. Unit High-level input voltage V Low-level input voltage V High-level input voltage (SDA, SCL) V Low-level input voltage (SDA, SCL) V High-level output voltage VOH I Low-level output voltage VOL I Low-level output voltage (SDA, INT) V Input Leakage Current ILI V Output Leakage Current ILO V Supply Current (during operati on) I Supply Current (during standby) I

AC Characte ristics

The SYSCLK (system clock) should be synchronized with inputs LRCK and BCK.

Parameter Symbol Condition Min. Max. Unit SYSCLK Cycle Time SYSCLK High-Level Ti me SYSCLK Low-Level Time BCKI Cycle Time BCKI High-Level Time BCKI Low-Level Time DI Setup Time (Ext. sync. / Int. gen.) DI Hold Time (Ext. sync. / Int. gen.) LRCKI Setup Time LRCKI Hold T ime BCKO Delay Time (Ext. sync. /

Through mode) DO Delay Time (Ext. sync. / Int. gen.)

DO Delay Time (Through Mode) LRCKO Delay Time (Int. gen.)

LRCKO Delay Time (Ext. sync. / Through mode)

Input Rise Time, I nput Fall Tim e Reset Pulse Time

Note: The input v ol tage le vel is measure d at VC C /0V . The confront level o f the output signal is measured at VCC/2.

 VCC×0.7 5.5 V

IH1

 −0.3 VCC×0.3 V

IL1

 VCC×0.75 5.5 V

IH2

 −0.3 VCC×0.25 V

IL2

= −4 mA 2.4  V

= 4 mA  0.4 V

OL2

SYSCLK = 24.576 MHz  30 mA

DD1

Input pin = 0 V  4.5 mA

DD2

= 4 mA  0.4 V

= VCC or VSS −10 +10 µA

OUT

(Ta = 0 to 70°C, VCC = 3.3 V ±0.3V, VSS = 0 V)

SYSCLK

SYSCKH

SYSCKL

BCLKI

BCKIH

BCKIL

DIS

DIH

LCKIS

LCKIH

  15 ns

BCKDT

ODD

LCKOD

LCKDT

RSTP

CL=20pF −7 12 ns CL=20pF CL=20pF −7 12 ns

= 20pF  15 ns

Except SDA and SCL 1 5 ns

80 ns 30 ns 30 ns

100

ns ns ns

ns ns ns ns

15 ns

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Input/Output Waveforms

SYSCLK

Through Mode

LRCKI 0-3

BCKI 0-3

DI 0-3

LRCKO 0-3

BCKO 0-3

DO 0-3

Figure 2 Through-Mode Input and Output Timing Diagram

External Synchronization Mode

LRCKI 0-3

BCKI 0-3

DI 0-3

LRCKO 0-3

BCKO 0-3

DO 0-3

Figure 3 External Sync. Mode Input and Output Timing Diagram

SYSCKH

SYSCKL

SYSCLK

Figure 1 S ystem Clock Diagram

BCKIHt BCKIL

BCKCYC

BCKIHt BCKIL

BCKCYC

ODT

ODH

BCKDT

LCKIS

LCKDT

LCKIH

LCKDT

LCKIH

ODD

LCKDT

DIS

LCKDT

DIH

VIH

VIL

ML87V5002

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VOH

VOL

VOH

VOL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VOH

VOL

VOH

VOL

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Internal Generation Mode

LRCKI 0-3

BCKI 0-3

DI 0-3

LRCKO 0-3

BCKO 0-3

DO 0-3

BCKIHt BCKIL

BCKCYC

BCKOHt BCKOL

BCKOCYC

LCKIS

LCKIH

LCKOH

ODH

DIS

DIH

ODD

Figure 4 Internal Sync. Mode Input and Output Timing Diagram

LCKOD

ML87V5002

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VOH

VOL

VOH

VOL

VIH VIL

Figur e 5 Rise Time, Fall T ime (t

)

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ML87V5002

C Interface Timing

The internal register setting is done via I frequency = 100 kHz). Fig. 6 sh ows th e bas ic t im ing. Ta ble 1 summar iz es th e A C Char act er i sti cs of th e st an dar d mod e I

C Interfa ce. Th e int er face i s ba sed on th e st an dar d mode I2C bus (SCL

C bus. Do not change the “SDA” level as long as the “SCL” is high except the stop or start condition. Refer to the “AC Characteristics” to know the values of timing parameters.

SDA

MSB

SCL

Start Condition

Reset Pulse Time t I2C Clock Cycle Time t I2C Clock Hi g h -Level Time t I2C Clock Lo w- L evel T ime t I2C Data Setup Time t I2C Data Holdup Tim e t

Tabl e 1 AC Charact eristics of Standard Mod e I

1 2 7 8 9 1 2 9

DSI2CtDHI2C

Figure 6 I

CCI2CtHI2C tLI2C

C Interface Basic Timing

ACK

C Bus (SCL Fr equency = 100 kHz)

Parameter Symbol Min. Max. Unit

100  ns

RSTP

10  µs

CCI2C

4  µs

HI2C

4.7  µs

LI2C

250  ns

DSI2C

0 3.45 µs

DHI2C

Stop Condition

Power-On

For the normal operation of the ML87V5002, the pins other than the RESET pin should be maintained at a low level until the VCC has reached the specified voltage level after powered on. Thereafter this LSI is reset by maintaining the RESET pin at a low level for 1 ms or more. The release of the RESET level leads to starting normal operation. To reset this LSI during normal operation, set the RESET pin at a “L” level for a time t

or more.

RSTP

To power on again a fter powered off, verify that VCC is 0 V.

Power-on

VCC min

VCC

RESET

1 ms (min.)

Figure 7 Power-On Sequence

RSTP

VCC

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ML87V5002

FUNCTIONAL OPERATION

Mode of Operation

The ML87V5002 has two modes, 2-cha nnel mode and 8-channel mode. Mo de s e tting is done by the hos t CPU via

the I

C interface. When internal register “NOF_CH” ( SUB:00h-bit[2] ) is set to “0”, the 2-channel mode is set.

When “NOF_CH” is set to “1”, the 8-channel mode is set.

• 2-channel mode

In the 2-channel mode, there are four input groups, group0-3. The inputs in group-0 are comprised of LRCK0,BCKI0 and DI0. The inputs in group-1 are LRCK1, BCK1 and DI1. The inputs in group-2 are LRCKI2, BCKI2 and DI2. T he inputs in group-3 a re L CRKI3, BCKI3 a nd DI3 . T hat is, i n the 2-channel mo de, it looks fo ur independent delay devices having a common 2-channel input can be provided. The common 2-channel input is connected to the output terminal of the selector that has four input as shown in Fig.7. One of the four inputs can be selected by the setting of the internal register “DI_SEL” ( SUB:00h-bit[1:0] ) as shown in the Table 2.

Table 2 Input Source Selection (SUB:00h-bit[1:0])

DI_SEL

[1] [0]

0 0 DI0 0 1 DI1 1 0 DI2 1 1 DI3

The 2-channel input audio data is selected and transferred to the four delay device s v ia the c ommon input te r minal and being delayed for certain periods. The delayed data are output from DO0 - DO3 controlled by LRCKO and BCKO. Each delay time for the DO0 - DO3 can be set independently by the setting of internal regisiter, “DLYx_L” ( x=0 - 7, SUB:10h-bit[7:0] - SUB:1fh-bit[7:0]) and “DLYx_H” ( x=0 - 7, SUB:10h-bit[7:0] SUB:1fh-bit[7:0]). The settings are shown in the Table 3.

Tabl e 3 Delay Time Setting o f E ach Outpu t

L/R Channel Register Name SUB

DO0 Delay Time

DELAY0

DO1 Delay Time

DELAY1

DO2 Delay Time

DELAY2

DO3 Delay Time

DELAY3

Lch CH0

Rch CH1

Lch CH2

Rch CH3

Lch CH4

Rch CH5

Lch CH6

Rch CH7

Selectable Input

Source

DLY0_L 10h-bit[7:0]

DLY0_H 11h-bit[7:0]

DLY1_L 12h-bit[7:0]

DLY1_H 13h-bit[7:0]

DLY2_L 14h-bit[7:0]

DLY2_H 15h-bit[7:0]

DLY3_L 16h-bit[7:0]

DLY3_H 17h-bit[7:0]

DLY4_L 18h-bit[7:0]

DLY4_H 19h-bit[7:0]

DLY5_L 1ah-bit[7:0]

DLY5_H 1bh-bit[7:0]

DLY6_L 1ch-bit[7:0]

DLY6_H 1dh-bit[7:0]

DLY7_L 1eh-bit[7:0]

DLY7_H 1fh-bit[7:0]

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ML87V5002

Figure 8 shows the con cept of th e 2 - channel mode.

DI0 DI1 DI2 DI3

Selector

DELAY0 (L/R)

DELAY1 (L/R)

DELAY2 (L/R)

DO0

DO1

DO2

DELAY3 (L/R)

DO3

*1. DELAY0 (L/R), DELAY1 ( L/R), DELAY2 (L/R), and DELAY3 (L/R) can be set independently. *2. The input format and sampling frequency for each of DI0 to DI3 can be set. *3. The output format and the input format can be set independently, however, the output format for DO0 to DO3

is equal.

Figure 8 Conceptual Diagram of 2-Channel Mode

• 8-channel mode

In the 8-channel mode the ML87V5002 operates as an 8-channel audio interface input. In this case, LRCKI0 and BCKI0 are used. N ote that LRCKI1, LRCKI2, LR CK I3, BCKI1, BCKI2 and BCKI3 a re not used in t he 8-channel mode. The dat a of each cha nne l is i nput to D I 0 to DI3 and is d elaye d f or the se t delay time. The da ta input to DI0 to DI3 are output from DO0 to DO3 having certain delay times, respectively. The delay time of each input can be set by the inte rnal registers “DL Yx_L” (x =0 to 7, SU B :10h-bit[7:0] to SU B :1fh-bit[7:0]) a nd “DL Yx_H ” (x=0 to 7 , SUB:10h-bit[7:0] to SUB:1fh-bit[7:0]).

Figure 9 shows the con cept of 8-ch annel mode

DO0

DELAY0 (L/R)

DO0

DO1

DELAY1 (L/R)

DO1

DO2

DELAY2 (L/R)

DO2

DO3

DELAY3 (L/R)

DO3

*4. DELAY0 (L/R), DELAY1 ( L/R), DELAY2 (L/R), and DELAY3 (L/R) can be set independently. *5. The output format and the input format can be set independently.

Figure 9 Conceptual Diagram of 8-Channel Mode

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ML87V5002

Operation Sequence

When reset is released, the internal register INIT( SUB:08h-bit[0] ) is set to “1” and the ML87V5002 starts the initial sequence and then starts its normal operation. The ML87 V5 002 keeps th e comman d-wa it s tat e (wai tin g for th e regi ster set tin g of the host CPU) aft er th e init ial sequence. In this command-wait state, the delay operation is not started and the output keeps mute states. The delay operation is started by writing each parameter from the host CPU to the internal register and setting internal register “ENBL” ( SUB:07h-bit[7] ) to “1”. When internal register “ENBL” ( SUB:07h-bit[7] ) is set to “1”, the ML87V5002 starts to investigate the validity of the settings. If the settings are prop er, in ternal re gister “RUN” ( SUB:08h-bit[7] ) is s et to “1”, the mute state is released, and the delay operation is started.

• Suspension of the delay operation

This LSI set s the EN BL and RUN bit s to “0” an d susp end s the del ay oper ati on wh en any of th e followin g even t s occurs:

1. “0” is written to internal register ENBL (SUB:07h-bit[7]).

2. The s ignal s of L RCKI a nd BC K become out of syn c hr onizat ion.

3. The setting of the audio format except the delay parameters is changed.

4. Input source channel is changed.

5. Operation m ode is changed.

6. The operation is started on condition that parameters at settings are not proper.

7. The BCK pulses less than the data length are input.

8. Overrun or underrun occurs due to a mismatch in clock between the in put a nd output.

When th e suspension i s caused by event 2, 6, 7 , or 8 above, the LSI mut es the output imm ediatel y and sets the corresponding error bits in the internal registers shown in Table 4 to “1”.

Tabl e 4 E rror Status Registers

Name

TMG_ERR

CFG_ERR

BCK_ERR

OVRN

UDRN

Set when any change is detected in the input timing after resuming the operation and the LSI suspends the delay operation.

Indicates the delay operation is suspended due to inconsistency of the setting values.

Set when the number of BCK pulses in LRCK is less than the input data length or the output data length in external synchronization mode after starting the ope ration. The dela y operation is susp e nded.

Set when the output data cyc le is slower than the input cycle and the delay buffer overflows, and the delay operation is suspended.

Set when the output data cycle is faster than the input cycle and the delay buffer becomes empty, and the delay operation is suspended.

Error Description SUB

09h-bit[7]

09h-bit[6]

09h-bit[5]

09h-bit[4]

09h-bit[3]

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OKI ML87V5002 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

GENERAL DES CRI PTIO N

FEATURES

BLOCK DIAG RAM

PIN CONFIGURATION (TOP VIEW)

PIN DESCRIPTION

ABSOLUT E MAXIMUM RATINGS

RECOMMENDED OPERAT IN G CO NDI T I O NS

PIN CAPACITANCE

ELECTRICAL CHARACTERISTICS

DC Characte ristics

AC Characte ristics

Input/Output Waveforms

Power-On

FUNCTIONAL OPERATION

Mode of Operation

Operation Sequence