OKI ML87V User Manual
OKI Semiconductor
PEDL87V2103DIGEST-01
Issue Date: Jan. 20, 2003
ML87V2103
Video Signal Noise Reduction and Rate Conversion IC with a Built-in 3.9 Mbit Field Memory
Preliminary
GENERAL DESCRIPTION
The ML87V2103 comprises a 3.9 Mbi t field m emory and lo gic circuits f or signal processing a nd m emory contr ol.
The device can reduce field-recursive noise and double the conversion speed.
There is an automatic noise reduction mode that detects the noise level in the input video data to set the optimum
noise reduction.
There are two ways to double the conversion speed: progressive conversion that doubles the number of lines by
doubling the horizontal direction frequency and flicker-free conversion that doubles both the vertical and
horizontal direction frequencies.
FEATURES
• Built-in memory:
3.9 Mbit filed memory × 1 unit
• Maximum input operating frequencies (16 bits/8 bits, ITU-R BT.656):
14.75/29.5 MHz
• Maximum output operating frequency:
29.5 MHz (double-speed conversion)
• Power supply voltage :
3.3 V ± 0.3 V
• Input pin:
TTL-5V tolerant (5 V withstand voltage)
• Input/output pins:
Input TTL- output LVCMOS-5V tolerant (5 V withstand voltage)
• Output pin:
LVCMOS (3.3 V)
• Input data format:
YCbCr (8 bits (Y) + 8 bits (CbCr)) (4:2:2)
YCbCr (8 bits (YCbCr)) (4:2:2)
ITU-R BT.656 (8 bits (YCbCr))
• Output data format:
YCbCr (8 bits (Y) + 8 bits (CbCr)) (4:2:2)
• Serial bus:
2
C-bus interface: (Standard mode: 100 kbps/Fast mode: 400 kbps)
I
• Internal memory controller:
Input: Compatible with 625/50 Hz 2:1, 525/60 Hz 2:1
Output: Compatible with 625/50 Hz 2:1, 525/60 Hz 2:1,
625/50 Hz 1:1, 525/60 Hz 1:1,
625/100 Hz 2:1, 525/120 Hz 2:1
Compatible horizontal effective pixels: 640 (525 line mode only), 720, 768
• Sync generator (for output):
Can generate sync signals of 625/50 Hz 2:1, 525/60 Hz 2:1,
625/50 Hz 1:1, 525/60 Hz 1:1,
625/100 Hz 2:1, 525/120 Hz 2:1.
Compatible horizontal effective pixels: 640 (525 line mode only), 720, 768
• Field-recursive noise reduction:
Noise detection and subtraction (with horizontal motion compensation)
Automatic noise reduction mode
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PEDL87V2103DIGEST-01
OKI Semiconductor
• Double-speed conversion data interpolation:
2-line linear filter (progressive, flicker-free)
Inter-field stationary compensation (progressive *with I/O phase control applied)
• Package:
100 pin QFP (QFP100-P-1420-0.65-BK4)
ML87V2103
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PEDL87V2103DIGEST-01
R
OKI Semiconductor
BLOCK DIAGRAM
YI0-7
CI0-7
MODE0-3
SSG
TEST1-6
x16
ICLK
IVS OVS
IHS
SCL
SDA
SLA1
SLA2
ESET
I2C-bus
I/F
Register
Input
Process
Block
+
3D NR
Control
Signals
x16
x16
IICLK
W_Port
R_Port1
7ports
Field Memory
(3.9Mbits)
Control
signals
Memory
Controller
+
NR
Controller
+
Line Filter
Controller
IF
IV
Output Sync.
Generator
R_Port2
x16
R_Port3 x16
x16R_Port4
R_Port5 x16
R_Port6 x16
Output
Process
Block
+
Line
Filter
ML87V2103
x16
YO0-7
CO0-7
OCLK
OE
OHS
HREF
CLKO
INT
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PEDL87V2103DIGEST-01
OKI Semiconductor
PIN CONFIGURATION (TOP VIEW)
V
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
TEST5
V
TEST4
TEST3
TEST2
TEST1
N.C.
N.C.
TEST6
MTEST
SELF
V
OE
DD
N.C.
N.C.
78
3
N.C.
N.C.
76
77
5
4
SS
V
SDA
V
RESET
79
80
81
SS
82
83
84
85
86
87
88
89
90
DD
91
92
93
94
95
96
97
98
99
100
SS
2
1
DD
V
N.C.
N.C.
75
6
SCL
N.C.
74
7
SLA1
SS
V
73
8
SLA2
YO7
72
9
YI7
DD
V
YO4
YO3
YO6
71
YO5
70
69
YO2
66
67
68
ML87V2103
(QFP100-P-1420-0.65-BK4)
15
14
13
12
11
10
YI3
YI2
YI6
YI5
YI4
YI1
YO1
65
16
YI0
YO0
64
17
DD
V
SS
V
63
18
ICLK
OCLK
62
19
SS
V
DD
V
61
20
CI7
CO7
60
21
CI6
CO6
59
22
CI5
CO5
58
23
CI4
CO4
57
24
CI3
56
25
SS
V
CI2
CO3
55
26
CI1
ML87V2103
CO2
CO1
CO0
52
53
54
29
28
27
CI0
N.C.
N.C.
DD
V
51
50
V
SS
49
HREF
48
OVS
47
OHS
46
INT
45
SSG
44
N.C.
43
TEST7
42
V
DD
41
N.C.
40
V
SS
39
DD
V
38
CLKO
37
MODE3
36
MODE2
35
MODE1
34
MODE0
33
IHS
32
IVS
31
V
SS
30
DD
V
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PEDL87V2103DIGEST-01
OKI Semiconductor
PIN DESCRIPTIONS
No. Symbol I/O Pad Remarks Pin Description
1 VDD — IO&CORE Power supply 3.3 V
2 N.C. — Unused pin
3 N.C. — Unused pin
4 VSS — IO&CORE Ground
5 SDA I/O
6 SCL I Schmitt I2C-bus clock pin
7 SLA1 I pull-down 50k Slave address setting pin
8 SLA2 I pull-down 50k Slave address setting pin
9 YI7 I Luminance signal input pin bit 7 (MSB)
10 YI6 I Luminance signal input pin bit 6
11 YI5 I Luminance signal input pin bit 5
12 YI4 I Luminance signal input pin bit 4
13 YI3 I Luminance signal input pin bit 3
14 YI2 I Luminance signal input pin bit 2
15 YI1 I Luminance signal input pin bit 1
16 YI0 I Luminance signal input pin bit 0 (LSB)
17 VDD — IO&CORE Power supply 3.3 V
18 ICLK I Input system clock pin
19 VSS — IO&CORE Ground
20 CI7 I pull-down 50k Color difference signal input pin bit 7 (MSB)
21 CI6 I pull-down 50k Color difference signal input pin bit 6
22 CI5 I pull-down 50k Color difference signal input pin bit 5
23 CI4 I pull-down 50k Color difference signal input pin bit 4
24 CI3 I pull-down 50k Color difference signal input pin bit 3
25 CI2 I pull-down 50k Color difference signal input pin bit 2
26 CI1 I pull-down 50k Color difference signal input pin bit 1
27 CI0 I pull-down 50k Color difference signal input pin bit 0 (LSB)
28 N.C. — Unused pin
29 N.C. — Unused pin
30 VDD — IO&CORE Power supply 3.3 V
31 VSS — IO&CORE Ground
32 IVS I
33 IHS I
34 MODE0 I pull-down 50k Mode setting pin – bit 0
35 MODE1 I pull-down 50k Mode setting pin – bit 1
36 MODE2 I pull-down 50k Mode setting pin – bit 2
37 MODE3 I pull-down 50k Mode setting pin – bit 3
38 CLKO O Clock output (I2C-bus control possible)
39 VDD — IO&CORE Power supply 3.3 V
40 VSS — IO&CORE Ground
41 N.C. — Unused pin
Schmitt(IN)/
OpenDrain(OUT)
Schmitt
pull-down 50k
Schmitt
pull-down 50k
I2C-bus data pin
Input system vertical sync signal input pin
Input system horizontal sync signal input pin
ML87V2103
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