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ML7074
User Manual
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OKI ML7074 User Manual

OKI Semiconductor
FEDL7074-004DIGEST-01
Issue Date: Nov. 12, 2003
ML7074-004GA
VoIP CODEC
representative.

GENERAL DESCRIPTION

The ML7074-004GA is a speech CODEC for VoIP. This LSI allows selection of G.729 .A, or G.711 standard as a
speech CODEC. The LSI is optimum for adding VoIP functions to TAs, routers, etc., since it has the functions of an echo canceller for 32 ms delay, DTMF detection, tone detection, tone generation, etc.

FEATURES

• Single 3.3 V power supply operation (DV
• Speech CODEC:
Selectable among G.729.A (8 kbps), G.711 (64 kbps) µ-law, and A-law Supports PLC (Packet Loss Concealment) function conforming to ITU-T G.711 Appendix I
• Echo canceller for 32 ms delay
• DTMF detect function
• Tone detect function: 2 systems (1650 Hz, 2100 Hz: Detect frequency can be changed.)
• Tone generate function: 2 systems
• FSK generation function
• Dial pulse detect function
• Dial pulse transmit function
• Internal 1-channel 16-bit timer
• Built-in FIFO buffers (640 bytes) for transferring transmit and receive data
Frame/DMA (slave) interface selectable.
• Master clock frequency: 4.096 MHz (crystal oscillation or external input)
• Hardware or software power down operation possible.
• Analog input/output type:
Two built-in input amplifiers Two built-in output amplifiers, 10 kΩ driving
• Package: 64-pin plastic QFP (QFP64-P-1414-0.80-BK)
0, 1, 2, AVDD: 3.0 to 3.6 V)
DD
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FEDL7074-003DIGEST-01
OKI Semiconductor

BLOCK DIAGRAM

TONE0_DET
TONE_DET0
TONE1_DET
TONE_DET1
DTMF_DET
DTMF_CODE[3:0]
DTMF_REC
Bus Control Unit
Speech Codec
Linear PCM
10kΩ
GSX0
ML7074-004GA
CKGN
PLL
P/S
PCMO
INTB
GPO1 GPO0
INT
DP_DET
DTMF_DET
TONE0_DET
TONE1_DET
FGEN_FLAG
DTMF_CODE[3:0]
SYNC(8kHz)
OSC Power
r
G.711
BCLK
SYNC
GPI1 GPI0
TST3 TST2 TST1 TST0
PDNB
AVDD
AGND
DGND2
DVDD2
DGND1
DGND0 DVDD0 DVDD1
XO
XI
Serial I/F
CLKSEL
A0-A7
D0-D15
CSB
RDB
WRB
FR0B
FR1B
ACK0B
ACK1B
8b
16b
TX
TX
Buffer0
Buffer1
G.711
G.729.A
Encoder
TXGAIN
(TONEA/B)
TONE_GEN0
Sout
Clip
Center
ATTs
Echo Canceller
Codec
AIN0N
-
+
LPAD GPAD
Sin
A/D BPF
10kΩ
AMP0
GSX1
AIN0P
AIN1N
RX
RX
Buffer0
Buffer1
G.711
G.729.A
Decoder
RXGAIN
(TONEC/D)
TONE_GEN1
Rin
ATTr
AFF
Rout
STGAIN
D/A LPF
AMP1
AMP2
10kΩ
10kΩ
VFRO0
Controller
Frame/DMA
FGEN_FLAG
FSK_GEN
Codec
Decoder
F
VRE
AMP3
VFRO1
AVREF
TIMER
G.711
S/P
PCMI
Control
Register
DP_DET
CR16-B0(GPI0)
CR17-B0(GPO0)
DPDET
DPGEN
MCK
Encode
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FEDL7074-003DIGEST-01
OKI Semiconductor

PIN ASSIGNMENT (TOP VIEW)

AVDD AIN0P AIN0N
GSX0 GSX1
AIN1N
AVREF VFRO0 VFRO1
AGND
DGND2
DVDD2
XI
XO
TST3 TST2
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
GPO1
48
1
TST1
GPO0
47
2
TST0
GPI1
46
3
PCMO
GPI0
DGND1
45
44
CLKSEL
43
PDNB
42
L7074-004
4
5
6
7
PCMI
BCLK
SYNC
DVDD0
64-pin plastic QFP
A7
41
8
ACK0B
A6
40
9
ACK1B
A5
39
10
FR0B
A4
38
11
FR1B
A3
37
12
INTB
A2
36
13
CSB
A1
35
14
RDB
A0
34
15
WRB
ML7074-004GA
DVDD1
33
32
D15
31
D14
30
D13
29
D12
28
D11
27
D10
26
D9
25
D8
24
D7
23
D6
22
D5
21
D4
20
D3
19
D2
18
D1
17
D0
16
DGND0
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FEDL7074-003DIGEST-01
OKI Semiconductor

PIN DESCRIPTIONS

Pin No.
1 TST1 I “0” Test control input 1: Normally input “0”. 2 TST0 I “0” Test control input 0: Normally input “0”. 3 PCMO O “Hi-z” PCM data output 4 PCMI I I PCM data input
5 BCLK I/O
6 SYNC I/O
7 DVDD0 8 ACK0B I I Transmit buffer DMA access acknowledge signal input 9 ACK1B I I Receive buffer DMA access acknowledge signal input
10
11
12 INTB O “H” 13 CSB I I Chip select control input
14 RDB I I Read control input 15 WRB I I Write control input 16 17 D0 I/O I Data input/output 18 D1 I/O I Data input/output 19 D2 I/O I Data input/output 20 D3 I/O I Data input/output 21 D4 I/O I Data input/output 22 D5 I/O I Data input/output 23 D6 I/O I Data input/output 24 D7 I/O I Data input/output
25 D8 I/O I 26 D9 I/O I 27 D10 I/O I 28 D11 I/O I 29 D12 I/O I 30 D13 I/O I 31 D14 I/O I 32 D15 I/O I
Symbol I/O PDNB = “0” Description
CLKSEL = “0”
I
PCM shift clock input CLKSEL = “1” PCM shift clock output CLKSEL = “0”
I
PCM sync signal 8 kHz input CLKSEL = “1” PCM sync signal 8 kHz output Digital power supply
FR0B: (CR11-B7 = “0”) Transmit buffer frame signal output DMARQ0B: (CR11-B7 = “1”) Transmit buffer DMA access request signal output FR1B: (CR11-B7 = “0”) Receive buffer frame signal output DMARQ1B: (CR11-B7 = “1”) Receive buffer DMA access request signal output Interrupt request output “L” level is output for about 1.0 µs when an interrupt is generated.
I Digital ground (0.0 V)
Data input/output Fix to input state when using in 8-bit bus access (CR11-B5 = “1”). Data input/output Fix to input state when using in 8-bit bus access (CR11-B5 = “1”). Data input/output Fix to input state when using in 8-bit bus access (CR11-B5 = “1”). Data input/output Fix to input state when using in 8-bit bus access (CR11-B5 = “1”). Data input/output Fix to input state when using in 8-bit bus access (CR11-B5 = “1”). Data input/output Fix to input state when using in 8-bit bus access (CR11-B5 = “1”). Data input/output Fix to input state when using in 8-bit bus access (CR11-B5 = “1”). Data input/output Fix to input state when using in 8-bit bus access (CR11-B5 = “1”).
FR0B
(DMARQ0B)
FR1B
(DMARQ1B)
DGND0
“L”
“L”
O “H”
O “H”
ML7074-004GA
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FEDL7074-003DIGEST-01
OKI Semiconductor
Pin No.
33 DVDD1 34 A0 I I Address input 35 A1 I I Address input 36 A2 I I Address input 37 A3 I I Address input 38 A4 I I Address input 39 A5 I I Address input 40 A6 I I Address input 41 A7 I I Address input
42 PDNB I “0”
43 CLKSEL I I 44 DGND1
45 GPI0 I I 46 GPI1 I I General-purpose input pin 1 (5 V tolerant input)
47 GPO0 O “L”
48 GPO1 O “L” 49 AVDD
50 AIN0P I I AMP0 non-inverted input 51 AIN0N I I AMP0 inverted input 52 GSX0 O “Hi-z” 53 GSX1 O “Hi-z” 54 AIN1N I I AMP1 inverted input 55 AVREF O “L” Analog signal ground (1.4 V) 56 VFRO0 O “Hi-z” 57 VFRO1 O “Hi-z” 58 AGND 59 DGND2 60 XI I I 4.096 MHz crystal oscillator I/F, 4.096 MHz clock input 61 XO O “H” 4.096 MHz crystal oscillator I/F 62 DVDD2 63 TST3 I “0” Test control input 3: Normally input “0”. 64 TST2 I “0” Test control input 2: Normally input “0”.
Symbol I/O PDNB = “0” Description
 
Digital power supply
Power down input “0”: Power down reset “1”: Normal operation SYNC and BCLK I/O control input “0”: SYNC and BCLK become inputs “1”: SYNC and BCLK become outputs Digital ground (0.0 V)
General-purpose input pin 0 (5 V tolerant input) /Secondary function: Dial pulse detect input pin
General-purpose output pin 0 (5 V tolerant output, can be pulled up externally) /Secondary function: Dial pulse transmit pin General-purpose output pin 1 (5 V tolerant output, can be pulled up externally) Analog power supply
AMP0 output (10 kΩ driving) AMP1 output (10 kΩ driving)
AMP2 Output (10 kΩ driving)
AMP3 Output (10 kΩ driving) Analog ground (0.0 V) Digital ground (0.0 V)
Digital power supply
ML7074-004GA
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FEDL7074-003DIGEST-01
OKI Semiconductor
ML7074-004GA

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Conditions Rating Unit Analog power supply voltage Digital power supply voltage VDD Analog input voltage VAIN Analog pins
Digital input voltage Storage temperature range Tstg
VDA
VDIN1 Normal digital pins VDIN2 5 V tolerant pins
−0.3 to 5.0  −0.3 to 5.0
−55 to +150 °C
−0.3 to V
−0.3 to V
−0.3 to 6.0
+ 0.3
DD
+ 0.3
DD

RECOMMENDED OPERATING CONDITIONS

(Unless otherwise specified, AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V, Ta = −20 to +60°C)
Parameter Symbol Conditions Min. Typ. Max. Unit Analog power supply voltage VDA Digital power supply voltage VDD Operating temperature range Ta
Digital high level input voltage Digital low level input voltage VIL Digital pins
Digital input rise time tIR Digital pins Digital input fall time tIF Digital pins Digital output load capacitance CDL Digital pins Capacitance of bypass capacitor
for AVREF Master clock frequency Fmck MCK PCM shift clock frequency Fbclk BCLK (at input) 64 PCM sync signal frequency Fsync SYNC (at input) Clock duty ratio DRCLK MCK, BCLK (at input) 40 50 60 %
PCM sync timing
PCM sync signal width tWS SYNC (at input) 1BCLK
VIH1 Digital input pins 2.0 VIH2 GPI0 and GPI1 pins 2.0
Cvref Between AVREF and AGND 2.2+0.1
tBS tSB
   −20
BCLK to SYNC
(at input)
SYNC to BCLK
(at input)
3.0 3.3 3.6 V
3.0 3.3 3.6 V 60
V
+
DD
0.3
5.5 V
0.8 V
50 pF
4.7+0.1
2048 kHz
100
−0.3    
−0.01%
100 100
 
2 20 ns 2 20 ns
4.096 +0.01% MHz
8.0
 
V V
V V V
°C
V
µF
kHz
ns ns
µs
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FEDL7074-003DIGEST-01
OKI Semiconductor
ML7074-004GA

ELECTRICAL CHARACTERISTICS

DC Characteristics

(Unless otherwise specified, AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V, Ta = −20 to +60°C)
Parameter Symbol Conditions Min. Typ. Max. Unit
ISS
IDD1
Power supply current
IDD2
Digital input pin input leakage current
Digital I/O pin output leakage current
High level output voltage
Low level output voltage
Input capacitance *1 CIN Input pins
IIH Vin = DVDD IIL Vin = DGND
IOZH Vout = DVDD
IOZL Vout = DGND VOH
VOL
(PDNB = “0”, V
(SC_EN = “1”, PCMIF_EN = “1”,
Connect a 4.096 MHz crystal oscillator
When operating the whole system
(SC_EN = “1”, PCMIF_EN = “0”,
Connect a 4.096 MHz crystal oscillator
Note: *1 Guaranteed design value
Standby state
= 3.3 V, Ta = 25°C)
DD
Operating state 1
In the PCM/IF mode
AFE_EN = “1”)
between XI and XO.
Operating state 2
AFE_EN = “0”)
between XI and XO.
Digital output pins, I/O pins
IOH = 4.0 mA
IOH = 1.0 mA (XO pin)
Digital output pins, I/O pins
IOL = −4.0 mA
IOL = −1.0 mA (XO pin)
−1.0 −0.01 µA 
−1.0 −0.01 µA
2.2
5.0 20.0
45.0 55.0 mA
50.0 65.0 mA
0.01 1.0
0.01 1.0
0.4 V
8 12 pF
µA
µA
µA
V
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FEDL7074-003DIGEST-01
OKI Semiconductor
ML7074-004GA

Analog Interface

(Unless otherwise specified, AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V, Ta = −20 to +60°C)
Parameter Symbol Conditions Min. Typ. Max. Unit Input resistance *1 RIN AIN0N, AIN0P, AIN1N 10 Output load resistance RL GSX0, GSX1, VFRO0, VFRO1 10 Output load capacitance CL Analog output pins Offset voltage VOF VFRO0, VFRO1
Output voltage level *2 VO
GSX0, GSX1, VFRO0, VFRO1
RL = 10 kΩ
−40  
 MΩ   kΩ
50 pF 40 mV
1.3 Vpp
Notes: *1 Guaranteed design value *2 −7.7 dBm (600Ω) = 0 dBm0, +3.17 dBm0 = 1.3 Vpp
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FEDL7074-003DIGEST-01
OKI Semiconductor
ML7074-004GA

AC Characteristics

CODEC (Speech CODEC in G.711 (µ-law) Mode)
(Unless otherwise specified, AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V, Ta = −20 to +60°C)
Parameter Symbol
Transmit frequency characteristics
LR2
Receive frequency characteristics
Transmit signal to noise ratio [*1]
Receive signal to noise ratio [*1]
Transmit inter-level loss error
Receive inter-level loss error
Idle channel noise [*1]
Transmit absolute level [*2] Receive absolute level [*2]
Power supply noise reject ratio
LR3 LR4 LR5
LR6 SDT1 SDT2 SDT3 SDT4 SDT5
SDR1 SDR2 SDR3 SDR4 SDR5
GTT1 GTT2 GTT3 GTT4 GTT5
GTR1 GTR2 GTR3 GTR4
GTR5 NIDLT NIDLR
AVT 1020 0 0.285 0.320 0.359 Vrms
AVR 1020 0 0.285 0.320 0.359 Vrms PSRRT PSRRR
LT1 LT2 LT3 LT4 LT5 LT6
Frequency (Hz) Level (dBm0)
0 to 60 25
300 to 3000
3968.75
0 to 3000
3968.75
Noise frequency
range: 0 to 50 kHz
Noise level: 50mVpp
Conditions
1020 Reference value 3300 3400 0
1020 Reference value 3300 3400 0
1020
1020
1020
1020
 
0
0
3 35 0 35
−30
−40
−45
3 35 0 35
−30
−40
−45
3
−10
−40 −0.2
−50 −0.6
−55 −1.2
3
−10
−40 −0.2
−50 −0.6
−55 −1.2
Analog input =
AVREF
PCMI = “1”
 
Min. Typ. Max. Unit
−0.15
−0.15
13
−0.15
−0.15
13
35 28 23
35 28 23
−0.2 Reference value
−0.2 Reference value
−68  −72
30 30
0.20 dB
0.80 dB
0.80 dB
 
0.20 dB
0.80 dB
0.80 dB
                     
0.2 dB
0.2 dB
0.6 dB
1.2 dB
0.2 dB
0.2 dB
0.6 dB
1.2 dB
 
dBm0p dBm0p
Notes: *1 Using P-message filter *2 0.320 Vrms = 0 dBm0 = −7.7 dBm (600Ω)
dB
dB
dB dBp dBp dBp dBp dBp dBp dBp dBp dBp dBp
dB
dB
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