How it Works
OKI
Loading...
ML7051LA
User Manual
24 pgs165.41 Kb0
Table of contents
Loading...

OKI ML7051LA User Manual

Download
FEDL7051LA-02
1
Semiconductor
This version: Sept. 2000
ML7051LA
Bluetooth Baseband Controller IC

GENERAL DESCRIPTION

FEATURES

• Conforms to the Bluetooth Specification (Ver1.0B)
• The ARM7TDMI is installed as the CPU (operation at a maximum of 32 MHz in this LSI)
• 1-Ch, 16-bit auto-reload timer
• Interrupt controller (17 causes)
• Built-in 8 kbyte, 4-Way Copy Back Unified Cache
• Built-in 24 kbyte RAM (supports 16-byte burst access)
• Up to a total of 2 Mbyte of SRAM, ROM, and Flash ROM can be connected to the external memory bus.
• PCM-CVSD transcoder is installed.
• Installed interfaces:
- UART
-USB
- UART synchronous serial port interface
- General-purpose I/O interface (programmable interrupts)
- PCM interface (PCMLinear/A-law/µ-law can be selected)
- JTAG interface
(*)
• Power supply voltages: For I/O: 3.0 to 3.6 V; for internal core: 2.25 to 2.75 V
• Package: 144-pin BGA (P-LFBGA144-1111-0.80)
(Dimensions: 11 mm × 11 mm × 1.5 mm; pin pitch: 0.8 mm)
(*)
interface (up to 921.6 kbps)
(*)
interface (conforms to USB1.1)
This mark indicates interfaces that support the HCI command.
ARM and the ARM POWERED logo are registered trademarks of ARM Ltd., UK. ARM7TDMI and Thumb are trademarks of ARM Ltd., UK. The informa t ion contained herein c an change without notice owing to the product being unde r development.
1/24
FEDL7051LA-02
1
Semiconductor
ML7051LA

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Conditions Rating Unit Power supply voltage V Input voltage V Allowable power dissipation P Storage temperature T
DD
I
d
stg
— –0.3 to +4.5 V — –0.3 to +4.5 V —1.35W — –55 to 150 °C

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Conditions Min. Typ. Max. Unit Power supply voltage (for I/O) Vdd_io — 3.0 3.3 3.6 V Power supply voltage (for th e internal core) Vdd_c ore — 2.25 2.5 2.75 V “H” level input voltage Vih — 2.2 — 3.6 V “L” level input voltage Vil — 0 — 0.8 V Operating temperature Ta — –40 — 85 °C

ELECTRICAL CHARACTERISTICS

DC Characteristics

(Vdd_io = 3.3 V ±0.3V, Vdd_core = 2.5 V ±10%, Ta = 0 to 70°C)
Parameter Symbol Conditions Min. Typ. Max. Unit “H” level output voltage Voh Ioh = –4 mA 2.4 — — V “L” level output voltage Vol Iol = 4 mA — — 0.4 V Input leak current Ii Vi = GND to 3.6 V –10 — 10 µA Output leak current Io Vo = GND to Vdd –10 — 10 µA
Power supply current (during operation) Iddo
During 32 MHz
operation
Power supply current (during stand-by) Idds CLK Stopped — 50 500 µA
05070mA
2/24
1
Semiconductor

PIN PLACEMENT

12345678910111213
NC CIO14 PCMIN
A
CIO13 CIO15
B
CIO11 GND CIO12 PCMCLK RXC GND
C
CORE_
D
CIO7 CIO5 CIO9 CIO6 A_GND RXD SCLK12 XCLK
E
CIO4 CIO3 CIO1 CIO2 GND PUCTL VDD A_VDD
F
GND VDD CIO0 GND GND DP VDD DM
G
MA15 MA17 MA19 MA18 SVCO0
H
MA12 MA16 MA11 MA14
J
MA10 MA13
K
GND MA9 MA4 MA2 MA0 VDD GND ND7
L
M
N
CIO8 CIO10 PCMOUT
VDD
MA6 MA7 MA1 GND MD13 MD11 MD10 MD5 MD4 MD1 MREn MBSn1 GND
NC MA5 MA3
PCM
SYNC
CORE_
PLL_PS GND PLL_CLK
VDD
CORE_
MA8 MD14 GND MD9 MD6 MD2 MCSn0 MOEn0 TMS CLK
VDD
CORE_
VDD
FEDL7051LA-02
ML7051LA
PLL_ POW
TEST_L
TEST_L
TX_POW
TXD PLL_LE VDD
RX_POW
PLL_OF
PLL_
PLLLOCK
DATA
MD15 MD12 MD8 MD3 GND MWEn MCSn1 MBSn0 NC
TEST1
TEST0
RSSI_
CLK
TEST_L
TEST3
TEST_L
TEST2
TEST_L
TEST5
CORE_
VDD
CORE_
VDD
VTM
SCLKSEL
TEST_L
TEST4
BBWSEL TXCSEL
RSSI GND VDD TXC_IN
CORE_
TEST_L PLLSEL
nTRST
MD0 MOEn1 TDO
REMAP0
GND TDI
CORE_
VDD
SVCO1
VDD
TEST_L
PLLEN
REMAP1
RESETn
TEST_O DPLOUT
CORE_
NC
TCK
VDD
TOP VIEW
3/24
1
Semiconductor

PIN DESCRIPTIONS

RF I/F
Pin Name I/O
TXD O — — A5
RXD I — — E11
PLL_DATA O — L D5
PLL_CLK O — L B6
PLL_LE O — L A6
PLL_OFF O — L C7
RSSI I Pull down — D10
RSSI_CLK O — — D8
PLL_POW O — H D7
TX_POW O — H C8
RX_POW O — H B7
PLL_PS O — L B4 PLL power control signal output
PLLLOCK I Pull down L D6 PLL lock signal input
RXC O — L C5 Bluetooth receive clock output (1 MHz)
TXC_IN I Pull down L D13
TXCSEL I Pull down L C11
Internal
Pull Up/Down
Initial Value
Pin
Placement
Description
Transmit data output (To ML7050LA Pin# A8)
Receive data input (To ML7050LA Pin# H5)
PLL setting data output (To ML7050LA Pin# H3)
PLL setting clock output (To ML7050LA Pin# G3) PLL setting load enable output (To ML7050LA Pin# H4) PLL Open-loop/Closed-loop control signal
output (To ML7050LA Pin# G8) Receive field strength data input
(To ML7050LA Pin# G6) RSSI transfer clock
(To ML7050LA Pin# H8) Local transmit circuit power control signal
output (To ML7050LA Pin# A7) Transmit power control signal output (To ML7050LA Pin# B6) Receive power control signal output (To ML7050LA Pin# B3)
Bluetooth transmit clock input (1 MHz) When the transmit clock is used by a clock
(RXC) that is generated from the receive data, set TXCSEL(Pin# C11) to H and connect to RXC(Pin# C5).
Bluetooth transmit clock setting pin L: Select 1 MHz divided by internal PLL. H: Select TXC_IN input signal.
FEDL7051LA-02
ML7051LA
4/24
1
Semiconductor
CLK and Configuration
Pin Name I/O
SCLK12 I — — E12
XCLK I — — E13 User clock input pin
SCLKSEL I Pull down — A11
RESETn I — — C13 Hardware reset pin (Reset = L)
BBWSEL I — — C10
REMAP0 I — — A12
REMAP1 I B13
Internal
Pull Up/Down
Initial
Value
Pin
Placement
Description
Master clock (12 MHz) input pin (Power level: CMOS level)
System clock select pin L: Select CLK divided by internal PLL H: Select XCLK input signal
BANK0 region bit width select pin L: 8-bit H: 16-bit REMAP select pin during boot up REMAP[1:0] = “00” Reserved
“01” Stacked Flash ROM “10” External MCS[1] device “11” External MCS[0] device
FEDL7051LA-02
ML7051LA
Memory I/F
Pin Name I/O
MA[19:0] O — L [*1] External address bus
MD[15:0] I/O — Z [*2] External data bus
MWEn O — H N10 External write enable signal output
MREn O — H M11 External read enable signal output MCSn0 O — H K10 External RAM space chip select MCSn1 O — H N11 External I/O space chip select
MBSn0 O — H N12 External lower byte select MBSn1 O — H M12 External upper byte select
MOEn0 O — H K11
MOEn1 O — H L11
MWAIT I — — F3
Internal
Pull Up/Down
Initial
Value
Pin
Placement
Description
External MCS[0] device output enable (MCSn0 and WREn OR output)
External MCS[1] device output enable (MCSn1 and WREn OR output)
External wait signal input (Pin shared with GPIO1)
[*1] MA19: H3; MA18: H4; MA17: H2; MA16: J2; MA15: H1; MA14: J4
MA13: K2; MA12: J1; MA11: J3; MA10: K1; MA9: L2; MA8: K4; MA7: M2 MA6: M1; MA5: N2; MA4: L3; MA3: N3; MA2: L4; MA1: M3; MA0: L5
[*2] MD15: N5; MD14: K5; MD13: M5; MD12: N6; MD11: M6; MD10: M7
MD9: K7; MD8: N7; MD7: L8; MD6: K8; MD5: M8; MD4: M9; MD3: N8; MD2: K9; MD1: M10; MD0: L10
5/24
1
Semiconductor
USB I/F
Pin Name I/O
DP I/O — Z G11 USB data
DM I/O — Z G13 USB data
PUCTL O — L F11 Pull-up control pin
VBUS
(GPIO0)
I — — G3 USB detection pin
Internal
Pull Up/Down
Initial
Value
Pin
Placement
UART I/F
Pin Name I/O
SOUT O — H B2
SIN I — — A2
DCD I — — B1
RTS O — H C3
CTS I — — C1
DSR I — — D3
DTR O — H E3
RI I — — D2
Internal
Pull Up/Down
Initial
Value
Pin
Placement
ACE transmit serial data (Pin shared with GPIO15)
ACE receive serial data (Pin shared with GPIO14)
Data carrier detection (Pin shared with GPIO13)
ACE transmit data ready (Pin shared with GPIO12)
ACE transmit ready (Pin shared with GPIO11)
Receive data ready (Pin shared with GPIO10)
Receive ready (Pin shared with GPIO9)
Ring indicator (Pin shared with GPIO8)
FEDL7051LA-02
ML7051LA
Description
Description
SIO I/F
Pin Name I/O
STXD O — H E1
SRXD I — — E4
STDCLK I/O — — E2
SRDCLK I/O — — F1
Internal
Pull Up/Down
Initial
Value
Pin
Placement
Description
Serial data output (Pin shared with GPIO7)
Serial data input (Pin shared with GPIO6)
Clock for serial data output, in the input state after initialization (Pin shared with GPIO5)
Clock for serial data input, in the input state after initialization (Pin shared with GPIO4)
6/24
FEDL7051LA-02
1
Semiconductor
µPLAT_SIO I/F
Pin Name I/O
UTXD O — H F2 Serial data output (Pin shared with GPIO3)
URXD I — — F4 Serial data input (Pin shared with GPIO2)
Internal
Pull Up/Down
Initial
Value
Pin
Placement
Description
GPIO I/F
Pin Name I/O
GPIO[15:0] I/O — — [*3]
Internal
Pull Up/Down
Initial
Value
Pin
Placement
Description
Parallel I/O data (in the input state after initialization)
JTAG I/F
Pin Name I/O
TDI I Pull down — B12 Serial data input
TDO O — L L12 Serial data output
nTRST I Pull down — J11 Reset pin
TMS I Pull down — K12 Mode setting pin
TCK I Pull down — J13 Serial data clock
Internal
Pull Up/Down
Initial
Value
Pin
Placement
Description
ML7051LA
PCM I/F
Pin Name I/O
PCMOUT O — L D4 PCM data output
PCMIN I Pull down — A3 PCM data input
PCMSYNC I/O Pull down — A4
PCMCLK I/O Pull down — C4
Internal
Pull Up/Down
Initial Value
Pin
Placement
PCM sync signal (8 kHz), in the input state after initialization (can be switched by an internal register)
PCM clock (64 kHz/128 kHz), in the input state after initializati on (can be sw itched by an internal register)
[*3] CIO15: B2 GPIO15/SOUT (UART I/F)
CIO14: A2 GPIO14/SIN (UART I/F) CIO13: B1 GPIO13/DCD (UART I/F) CIO12: C3 GPIO12/RTS (UART I/F) CIO11: C1 GPIO11/CTS (UART I/F) CIO10: D3 GPIO10/DSR (UART I/F) CIO9: E3 GPIO9/DTR (UART I/F) CIO8: D2 GPIO8/RI (UART I/F) CIO7: E1 GPIO7/STXD (SIO I/F) CIO6: E4 GPIO6/SRXD (SIO I/F) CIO5: E2 GPIO5/STXDCLK (SIIO I/F) CIO4: F1 GPIO4/SRXDCLK (SIO I/F) CIO3: F2 GPIO3/UTXD (UPLAT_SIO I/F) CIO2: F4 GPIO2/URXD (UPLAT_SIO I/F) CIO1: F3 GPIO1/NWAIT (Memory I/F) CIO0: G3 GPIO0/VBUS (USB I/F)
Description
7/24
1
Semiconductor
TEST I/F
Pin Name I/O
TEST_L I — — [*4] Test pin (input)
TEST_O O — L H13 Test pin (output)
SVCO0 I — — H10 Built-in PLL characteristics setting pin SVCO1 I — — H12 Built-in PLL characteristics setting pin
VTM I — — A10 Built-in Flash ROM test pin
CLK O — — K13 Built-in Flash ROM test pin
NC — — —
Internal
Pull Up/Down
Initial
Value
Pin
Placement
A1, A13 N1, N13
Description
No Connection
Power, GND
Pin Name I/O
V
DD
CORE_V
GND — — — [*7] Digital block ground pin
A_V
DD
A_GND — — — E10 Analog block ground pin
— — — [*5] I/O power pin 3.3 V ±0.3 V — — — [*6] Core power pin 2.5 V ±10%
DD
— — — F13 Analog block power pin 2.5 V ±10%
Internal
Pull Up/Down
Initial
Value
Pin
Placement
Description
FEDL7051LA-02
ML7051LA
[*4] TEST_L (TEST5): C9
TEST_L (TEST4): B10 TEST_L (TEST3): A9 TEST_L (TEST2): B9 TEST_L (TEST1): A8 TEST_L (TEST0): B8 TEST_L (PLLSEL): J10
TSET_L (PLLEN): J12 [*5] A7, D12, F12, G2, G12, L6 [*6] B3, C12, D1, D9, H11, K3, L9, L13, N4 [*7] B5, B11, C2, C6, D11, F10, G1, G4, G10, K6, L1, L7, M4, M13, N9
8/24
Loading...
+ 16 hidden pages
Buy Points How it Works FAQ Contact Us Questions and Suggestions Privacy Policy Cookie Policy Terms of Use