OKI ML7037 User Manual

OKI Semiconductor

ML7037-003

Dual Echo Canceler & Noise Canceler with Dual Codec for Hands-Free

GENERAL DESCRIPTION

The ML7037-003 is an IC device developed for portable, handsfree communication with built-in line echo canceler, acoustic echo canceler, and transmission signal noise canceler. Built-in to the voice signal interface is a PCM CODEC for the analog interface on the acoustic-side, and another PCM CODEC for the analog interface on

the line-side. On the line-side, in addition to the analog interface, there is also a -law PCM/16-bit linear digital interface.

Equipped with gain and mute controls for data transmission and reception, a -law PCM/16-bit linear digital interface for memo recording and message output, and transfer clock and sync clock generators for digital communication, this device is ideally suited for a handsfree system.

FEATURES

• Single 3.3 V Power Supply Operation (3.0 to 3.6 V) [with built-in regulator to generate internal power supply]

• Built-in 2-channel (line and acoustic) echo canceler Echo attenuation : 35 dB (typ.) for white noise Cancelable echo delay time :

Single echo canceler mode (only an acoustic echo canceler is enabled) Tacoud= 64 ms (max) Dual echo canceler mode (both of an acoustic and line echo cancelers are enabled) Tacoud = 64 ms Tlined = 20 ms

• Built-in transmission signal noise canceler Noise attenuation : 13 dB (typ.) for white noise

• Built-in 2-channel CODEC’s

• Analog input gain amp’s (Acoustic side = 2 stages; Line-side = 1 stage)

• Analog output configuration : Push-pull drive (can drive a 2.0 k load)

• Receive-side ALC (Auto Level Controler)

• Programmable Gain/Mute

• A slope filter on transmit side

• 16 GPI’s and 8 GPO’s

• Speech digital interface coding formats : µ-law PCM (G.711 [64kbps]), 16-bit linear (2's complement)

• Speech digital interface sync formats : Long-frame-sync, short-frame-sync

• PCM shift clocks (BCLK) Clock slave mode : 64kHz to 2.048MHz (µ-law PCM) / 128kHz to 2.048MHz (16bit Linear PCM) Clock master mode : 64kHz (µ-law PCM) / 128kHz (16bit Linear PCM)

• Master clock frequency : 12.288 MHz (crystal unit the ML7037’s built-in driving circuit for a crystal unit or a crystal oscillator)

• Transmission signal equalizer

• Package : 64-pin plastic TQFP (TQFP64-P-1010-0.50-K) (ML7037-003TB)

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* This is a digest version of the ML7037-003 datasheet. Ask an OKI sales for a full version before you start actual designing

Not for Publication

activities.

PEDL7037-003-05Zz_Digest

Issue Date: May. 21, 2007

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SYNCSEL

OKI Semiconductor ML7037-003

BLOCK DIAGRAM

CLKSEL

PCMO

PCMI

CLKSEL

PCMSEL

XO

TSTI0

TSTI1

TSTI2

XO

TSTI0

TSTI1

SYNC

BCLK

XI/MCK

SYNC

BCLK

XI/MCK

TSTI2

P/S

S/P

Timing

Generator

Test

OSC

Control

G.711

Encoder

G.711

Decoder

[μ-law]

PLL

TPAD

Echo

Canceller

(Line Side)

[Line Side]

Echo Canceller

Filter

Slope

(Line Side)

RALC

er

Equaliz-

Noise

Canceller

RPAD

Echo

Side)

(Acoustic

Canceller

[Acoustic Side]

Echo Canceller

Canceller

DA

AD

DA

AD

DA

PGA

Linear Codec [Line Side]

Linear Codec [Acoustic Side]

Linear Codec [Line Side]

LINN

LGSX

AIN0P

AIN0N

AIN1N

AGSX1

AGSX0

AVFRO

LGSX

LVFRO

Not for Publication

Figure 1

AGND0,1

DVDD0,1

DGND0,1

DVDD0,1

DGND0,1

AVDD

REGOUT0, 1

&

Regulator

Power Control

MCU

Interface

EC / NC / SLP / ALC Control

AVREF

REGOUT0, 1 VBG

VBG

PDN

DOUT

DOUT DIN

DIN EXCK

EXCK

DEN

MCUSEL

GPOC7

GPOC7 GPOC6

GPOC6 GPOC5

GPOC5 GPOC4

GPOC4 GPOC3

GPOC3 GPOC2

GPOC2 GPOC1

GPOC1 GPOC0

GPOC0

RST

GPIA7 (RPAD3)

GPIA7 (RPAD3) GPIA6 (RPAD2)

GPIA6 (RPAD2) GPIA5 (RPAD1)

GPIA5 (RPAD1) GPIA4 (RPAD0)

GPIA4 (RPAD0) GPIA3 (TPAD3)

GPIA3 (TPAD3)

GPIAGPIB GPOC

GPIA2 (TPAD2)

GPIA2 (TPAD2) GPIA1 (TPAD1)

GPIA1 (TPAD1) GPIA0 (TPAD0)

GPIA0 (TPAD0)

GPIB7 (ECEN)

GPIB7 (ECEN) GPIB6 (ECSEL)

GPIB6 (ECSEL) GPIB5 (SLPTHR)

GPIB5 (SLPTHR) GPIB4 (ALCTHR)

GPIB4 (ALCTHR) GPIB3 (NCTHR)

GPIB3 (NCTHR) GPIB2 (VFROSEL)

GPIB2 (VFROSEL) GPIB1 (LINEEN)

GPIB1 (LINEEN) GPIB0

GPIB0

AVREFEN

AVREFEN AVREF

AVREF

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DE N

GPOC 0

GPOC 1

GPOC 2

GPOC 3

GPOC 4

GPOC 5

GPOC 6

GPOC 7

CLKSEL

RST

PD N

XO

MCK/XI

TST I1

TST I2

PCMO

PCMI

SYNC

BCLK

SYNCSEL

GPIB7 (ECEN)

GPIB6 (ECSEL)

GPIB5 (SLPTHR)

GPIB4 (ALCTHR )

GPIB3 (NCTH R)

GPIB2 (VFROSEL)

GPIB1 (

GPIB0

DVDD1

REGOUT1

DGND1

OKI Semiconductor ML7037-003

PIN CONFIGURATION (TOP VIEW)

64-Pin Plastic TQFP

)

LINEEN

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

PCMSEL

MCU SEL

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

VBG

LINN

TST I0

DVDD 0

REGOUT0

LGSX

DG ND0

LVFRO

AIN1N

AGSX1

AVFRO

AIN0P

AIN0N

AGSX0

AVREF

32

31

EXCK

30

DIN

29

DOU T

28

GPIA7 (R PAD 3)

27

GPIA6 (R PAD 2)

26

GPIA5 (R PAD 1)

25

GPIA4 (R PAD 0)

24

GPIA3 (T PAD 3)

23

GPIA2 (T PAD 2)

22

GPIA1 (T PAD 1)

21

GPIA0 (T PAD 0)

20

AVREF EN

19

AVDD

18

AGND1

17

16

AGND0

Figure 2

Not for Publication

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OKI Semiconductor ML7037-003

PIN OVERVIEW

Number

1 TSTI0 I I Test pin0

2 DVDD0 - - Digital power supply pin

3 REGOUT0 - - Regulatoroutput pin

4 VBG - - Regulatorreference voltage output pin

5 DGND0 - - Digital ground pin

6 LINN I I

7 LGSX O Hi-Z

8 LVFRO O

9 AVFRO O

10 AGSX1 O Hi-Z

11 AIN1N I I

12 AGSX0 O Hi-Z

13 AIN0N I I

14 AIN0P I I

15 AVREF O

16 AGND0 - - Analog ground pin

17 AGND1 - - Analog ground pin

18 AVDD - - Analog power supply pin

19 AVREFEN I I Input pin to switch enabling/dis abling AVREF during power-down

20

21

22

（Note）

(*1):Shows the output state when the AVREFEN pin is logic ‘0’. (*2):Shows the output state when the AVREFEN pin is logic ‘1’.

Pin Name I/O

GPIA0 (TPAD0)

GPIA1 (TPAD1)

GPIA2 (TPAD2)

PDN=”0”

L (*1)

1.4V apporx(*2)

L (*1)

1.4V apporx(*2)

L (*1)

1.4V apporx(*2)

I I

Descriptions

Line-sideanalog input pin

(reversed input pin for an analog input amplifier)

Line-sideanalog output pin

(output pin from an analog input amplifier)

Line-sideanalog output pin

Acoustic-sideanalog output pin

(output pin from an analog input amplifier)

Acoustic-sideanalog input pin

(reversed input pin f or an analog input amplifier)

Acoustic-sideanalog output pin

(output pin from an analog input amplifier)

Acoustic-sideanalog input pin

(reversed input pin f or an analog input amplifier)

Acoustic-sideanalog input pin

(reversed input pin f or an analog input amplifier)

Output pin for analog signal ground level

General-purpose input port pin ＜Primary function＞ General-purpose input port pin ＜Secondary function＞ Input pin to tune volume of transmit speech signals General-purpose input port pin ＜Primary function＞ General-purpose input port pin ＜Secondary function＞ Input pin to tune volume of transmit speech signals General-purpose input port pin ＜Primary function＞ General-purpose input port pin ＜Secondary function＞ Input pin to tune volume of transmit speech signals

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DEN

side analog

rmal mode and through

OKI Semiconductor ML7037-003

Number

23

24

25

26

27

28 DOUT O Hi-Z Data output pin for MCU interface

29 DIN I I Data input pin for MCU interface

30 EXCK I I Clock input pin for MCU interface

31

32 MCUSEL I I Input pin to switch between MCU interface enabled and disabled

33 DGND1 - - Digital ground pin

34 REGOUT1 - - Regulatoroutput pin

35 DVDD1 - - Digital power supply pin

36 GPIB0 I I General-purpose input port pin

37

38

39

Pin Name I/O

GPIA3 (TPAD3)

GPIA4 (RPAD0)

GPIA5 (RPAD1)

GPIA6 (RPAD2)

GPIA7 (RPAD3)

GPIB1 (

LINEEN)

GPIB2 (VFROSE L)

GPIB3 (NCTHR)

PDN=”0”

General-purpose input port pin ＜Primary function＞

I I

I I Data enable input pin for MCU interface

I I

General-purpose input port pin ＜Secondary function＞ Input pin to tune volume of transmit speech signals General-purpose input port pin ＜Primary function＞ General-purpose input port pin ＜Secondary function＞ Input pin to tune volume of receive speech signals General-purpose input port pin ＜Primary function＞ General-purpose input port pin ＜Secondary function＞ Input pin to tune volume of receive speech signals General-purpose input port pin ＜Primary function＞ General-purpose input port pin ＜Secondary function＞ Input pin to tune volume of receive speech signals General-purpose input port pin ＜Primary function＞ General-purpose input port pin ＜Secondary function＞ Input pin to tune volume of receive speech signals

General-purpose input port pin ＜Primary function＞ General-purpose input port pin ＜Secondary function＞ Input pin to switc h between enabling and disabling of line- interface General-purpos e input port pin ＜Primary function＞ General-purpose input port pin ＜Secondary function＞ Input pin to select output signals from AVFRO/LVFRO General-purpose input port pin ＜Primary function＞ General-purpose input port pin ＜Secondary function＞ Input pin to select noise canceler mode between no

mode

Descriptions

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Input pin to select echo canceler mode between single echo canceler mode

）

6bit

OKI Semiconductor ML7037-003

Number

40

41

42

43

44 SYNCSEL I I Input pin to select between long frame sync and short frame sync

45 BCLK I/O

46 SYNC I/O

47 PCMI I I line-side PCM data input pin

48 PCMO O Hi-Z line-side PCMdata output pin

49 PCMSEL I I

50 GPOC0 O L General-purpose output port pin

51 GPOC1 O L General-purpose output port pin

52 GPOC2 O L General-purpose output port pin

53 GPOC3 O L General-purpose output port pin

Pin Name I/O

GPIB4 (ALCTHR)

GPIB5 (SLPTHR)

GPIB6 (ECSEL)

GPIB7 (ECEN)

PDN=”0”

I I

Descriptions

General-purpose input port pin ＜Primary function＞ General-purpose input port pin ＜Secondary function＞ Input pin to select ALC mode between normal mode and through mode General-purpose input port pin ＜Primary function＞ General-purpose input port pin ＜Secondary function＞ Input pin to select slope filter mode between normal mode and through mode General-purpose input port pin ＜Primary function＞ General-purpose input port pin ＜Secondary function＞

and dual echo canceler mode General-purpose input port pin ＜Primary function＞ General-purpose input port pin ＜Secondary function＞ Input pin to switch between disabling and enabling echo canceler

L （*1

Shift clock input pin for PCM interface

I （*2

L （*1

Sync clock input pin for PCM interface

I （*2

Input pin to select speech digital interface coding format between 1 Linear PCM and -law PCM

（Note）

(*1):Shows the output state when the CLKSEL-pin is logic ‘0’. (*2):Shows the output state when the CLKSEL-pin is logic ‘1’.

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Input pin to select between clock slave mode and clock master mode for

RST

PDN

OKI Semiconductor ML7037-003

Number

54 GPOC4 O L General-purpose output port pin

55 GPOC5 O L General-purpose output port pin

56 GPOC6 O L General-purpose output port pin

57 GPOC7 O L General-purpose output port pin

58 CLKSEL I I

59

60

61 XO O H Ouput pin to connect a crystal unit for master clock

62 MCK/XI I I

63 TSTI1 I I Test pin1

64 TSTI2 I I Test pin2

Pin Name I/O

PDN=”0”

PCM interface

I I Reset pin

I I Power-down pin

Input pin to connect a crystal unit for master clock Master clock input pin

Descriptions

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Buffer Amp

F

Gain= (R2/R 1) x ( R4/R 3)

1.3Vpp

OKI Semiconductor ML7037-003

PIN FUNCTIONAL DESCRIPTION

AIN0N, AIN0P, AGSX0, AIN1N, AGSX1

These are the acoustic analog input and level tuning pins. The AIN0N pin and the AIN1N pin are connected to the inverting input of the internal amp (AMP2、AMP1), and the AIN0P pin is connected to the non-inverting input of the internal amp (AMP2). The AGSX0 pin and the AGSX1 pin are connected to the internal amp (AMP2、AMP1). For the way to tune the level, refer to Figure 3 Analog Interface. During power-down mode ( pin go to a high impedance state.

(Note) When the acoustic side LSI-internal amplifier (AMP2) is not used, connect the AIN0P pin and the

AVREF pin and short the AIN0N pin and the AGSX0 pin.

(Note) Please refer to the application circuit example when the acoustic side LSI-internal amplifier (AMP2) is

used as a single-end input.

VAGSX1,0 ≦ 1.3Vp p 10k ≦ R2 ≦ 510k 10k ≦ R4 ≦ 510k

PDN pin = logic ‘0’ or SPDN-bit [CR0-B7] = ‘1’), the AGSX0 pin and the AGSX1

R4

C2

R3

AGSX1

AIN1N

AGSX0

Gain-Max（AMP1）≦5 times (+13.97dB)

(AMP1)

A/D

C1

10

C3

≦

VAVFRO

C4

Gain=R6/R5 10k ≦ R6 ≦ 510k VLGSX ≦ 1.3Vpp

C4

VLVFRO ≦ 1.3Vpp

R2

R1

R2

R5

R6

0.1F

AIN0N

AIN0P

AVREF

AVFRO

LGSX

LINN

LVFRO

(AMP2)

Gain-Max（AMP2）≦10 times(+20dB)

(AMP4)

(AMP3)

Gain-Max（AMP3）≦10 times(+20dB)

(AMP5)

AVREF

D/APGA

A/D

D/APGA

Figure 3 Analog Interface

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OKI Semiconductor ML7037-003

LINN, LGSX

These are the line analog input and level tuning pins. The LINN pin is connected to the inverting input of the internal amp (AMP3) and the LGSX pin is connected to the output of the amp (AMP3). For level tuning, refer to Figure 3 Analog Interface.

During power-down mode ( impedance state.

(Note) When the line side analog interface is not used, set the secondary function of the GPIB1 pin (

logic ‘1’ or set the

AVFRO, LVFRO

These are analog output pins respectively for acoustic-side and line-side. The AVFRO is connected to the output of the internal amp (AMP4), and the LVFRO is connected to the output of the internal amp (AMP5). The output state of the AVFRO pin and the LVFRO pin can be selected between speech signal output and the AVREF level output (1.4V approx.) by the VFROSEL pin or by the AVFROSEL-bit [CR16-B1] and the LVFROSEL-bit [CR16-B0]. When the concerned pin or the concerned bit is logic ‘1’, the AVFRO and/or the LVFRO pin outputs speech signals; when the concerned pin and the concerned bit is logic ‘0’, the AVFRO pin and/or the LVFRO pin outputs the AVREF level (1.4V approx.).

During power-down mode ( AVREFEN-bit [CR16-B7] are logic ‘0’, the AVFRO pin and the LVFRO pin go to a high impedance state; and, if the AVREFEN pin or the AVREFEN-bit [CR16-B7] are logic ‘1’, the pins output 1.4V approx.. (Note) If the AVREFEN pin and the AVREFEN-bit [CR16-B7] are logic ‘0’, pop noises may occur on release

and execution of power-down. If the AVREFEN pin and the AVREFEN-bit [CR16-B7] need to be logic ‘0’ and still the pop noises have to be eliminated, it has to be fixed outside of this LSI.

To avoid the pop noises, set the AVREFEN pin or the AVREFEN-bit [CR16-B7] to logic ‘1’ and let the

AVREF and the analog output amps alive. Furthermore, the power-down should be released and executed having the output state of the AVFRO pin and the LVFRO pin the AVREF level.

In concrete, the power-down should be released while keeping the VFROSEL pin and by the

AVFROSEL-bit [CR16-B1] and the LVFROSEL-bit [CR16-B0] to logic ‘0’, and then change the VFROSEL pin or the AVFROSEL-bit [CR16-B1] and the LVFROSEL-bit [CR16-B0] to logic ‘1’.

And, the VFROSEL pin and the AVFROSEL-bit [CR16-B1] and the LVFROSEL-bit [CR16-B0] should

be changed to logic ‘0’ before the power-down execution.

Please note that the power supply current during the power-down would be I

the specification under the DC Characteristics to come in a later section.) if the AVREFEN pin or the AVREFEN-bit [CR16-B7] are logic ‘1’.

AVREF

This is the output pin for the analog signal ground level. The output voltage is approximately 1.4 V. Insert a 10 µF bypass capacitor (a tantalum capacitor [recommendation] or an aluminum electrolytic capacitor) and a 0.1 µF capacitor (laminating ceramic type) in parallel between this pin and the AGND0 pin.

During power-down mode ( AVREFEN-bit [CR16-B7] to be logic ‘0’, the AVREF pin outputs 0.0V.

During power-down mode ( AVREFEN-bit [CR16-B7] to be logic ‘1’, the AVREF pin outputs 1.4V approx.. (Note) If you make use of the AVREF pin output externally in your system, it must be via a buffer amp.

AVREFEN

This is to select disabling and enabling the AVREF output during power-down mode ( SPDN-bit [CR0-B7] = ‘1’).

When this is logic ‘0’, the AVREF pin is disabled (power-down state). When this is logic ‘1’, the AVREF pin is enabled, and the outputs of the AVREF, the AVFRO and the LVFRO become 1.4V approx.. This pin control is valid only during power-down.

Not for Publication

PDN pin = logic ‘0’ or SPDN-bit [CR0-B7] = ‘1’), the LGSX pin goes to a high

LINEEN) to

LINEEN-bit [CR0-B5] to ‘1’, and short the LINN pin and the LGSX pin.

PDN pin = logic ‘0’ or SPDN-bit [CR0-B7] = ‘1’), if the AVREFEN pin and the

compliant (Please refer to

SS2

PDN pin = logic ‘0’ or SPDN-bit [CR0-B7] = ‘1’) with the AVREFEN pin and the

PDN pin = logic ‘0’ or SPDN-bit [CR0-B7] = ‘1’) with the AVREFEN pin or the

PDN pin = logic ‘0’ or

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C2

Floating

12.288MHz

OKI Semiconductor ML7037-003

GPIB1 (

This is a general-purpose input port pin. This also works as a power-down control over the line-side analog interface as the secondary function. When this pin is logic ‘0’, the line-side analog interface is enabled; and, when this pin is logic ‘1’, the line-side analog interface is powered-down (excluding the LVFRO output amp). During power-down, the LVFRO outputs 1.4V approx.. When the MCUSEL pin is logic ‘1’, this pin is automatically assigned with its secondary function. When the MCUSEL pin is logic ‘0’, this pin’s function assignment follows the state of GPFB1-bit [GPCR1-B1]. (Note) The change of the input state to this pin is detected at the rising edge of the SYNC clock so that the change

(Note) In an application where the line-side codec is never enabled, the LINN pin and the LGSX pin must be

(Note) The change of the enabled/disabled state of the line-side codec must be made during power-down state

GPIB2 (VFROSEL)

This is a general-purpose input port pin. This also works as the output state control over the AVFRO pin and the LVFRO pin as the secondary function. When this pin is logic ‘0’, they output the AVREF level (1.4V apporx.); and, when this pin is logic ‘1’, they output speech signals. When the MCUSEL pin is logic ‘1’, this pin is automatically assigned with its secondary function. When the MCUSEL pin is logic ‘0’, this pin’s function assignment follows the state of GPFB2-bit [GPCR1-B2]. (Note) When, during a call, the output state is changed or the reset is made, minor noises could happen due to an

(Note) The power-down execution and its release are recommended to be made when the AVFRO pin and the

(Note) When this pin is not used, set this pin to logic ‘0’.

MCK/X1, XO

These are pins to connect a crystal unit, and the former is used as the master clock input pin as well. The clock frequency is 12.288 MHz.

During power-down mode ( crystal unit is stopped. After the release of the power-down, the connected crystal unit starts being oscillated, but the master clocks start being utilized within this LSI only after the steady oscillation waiting time (28ms approx.). Refer to Figure 4 for an example application with an external clock and that with a crystal unit.

LINEEN)

of the input state to this pin less than 250 s may not be reflected as the LSI behavior.

shorted.

(

PDN pin = logic ‘0’ or SPDN-bit [CR0-B7] = ‘1’) or during initial mode.

interruption at an arbitrary point in a sequence of PCM codes so that this output state selection and the reset are recommended to be made before a call as long as it is application-wise allowed.

LVFRO pin are selected to output the AVREF level.

PDN pin = logic ‘0’ or SPDN-bit [CR0-B7] = ‘1’), oscillation of the connected

MCK/XI XO

MCK/XI

C1

X'tal

XO

R

X’tal

(12.288MHz)

HC-49/U-S 1M 10pF 10pF

R C1 C2

ex) External Clock ex) Crystal Unit

Figure 4 Examples of external clock and crystal unit as a master clock

(Note) When a crystal unit is used, connect the unit and a feedback resistor of 1M (R) between the MCK/XI

and the XO. The appropriate values of capacitors (C1, C2) to be connected between the MCK/XI and GND and between the XO and GND are influenced by load capacitance of a crystal unit and PCB patterns so that they are recommended to be determined by asking a crystal unit vendor for a matching test.

Not for Publication

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OKI Semiconductor ML7037-003

SYNC

This is the 8 kHz sync clcok I/O pin for PCM interface. When the internal clock mode is selected by the CLKSEL pin = logic ‘0’, this pin outputs 8kHz sync clocks synchronizing with the BCLK. When the external clock mode is selected by the CLKSEL pin = logic ‘1’, input 8kHz clocks to this pin in synchronization with the BCLK. When the SYNCSEL pin is logic ‘0’, this pin outputs/expects to have sync clocks in a long frame sync timing; whereas, when the SYNCSEL pin is logic ‘1’, this pin outputs/expects to have sync clocks in a short frame sync timing.

BCLK

This is the shift clock I/O pin for PCM interface. When the internal clock mode is selected by the CLKSEL pin = logic ‘0’, this pin outputs 64kHz in µ-law PCM mode or 128kHz in 16-bit linear PCM mode. When the external clock mode is selected by the CLKSEL pin = logic ‘1’, input shift clocks to this pin in synchronization with the SYNC. The input frequency must be between 64 kHz and 2048 kHz in µ-law PCM mode and 128 kHz and 2048 kHz in 16-bit linear PCM mode.

CLKSEL

This pin selects internal or external clock modes for PCM interface. A logic ‘0’ selects the internal clock mode where the SYNC pin and the BCLK pin output clocks so that this LSI could works as a clock master device in your system. A logic ‘1’ selects the external clock mode where this LSI needs the SYNC and the BCLK externally so that this LSI could works as a clock slave device in your system. If PCM digital interface is not used, set this pin to a logic ‘0’ to select internal clock mode. (Note) The change of the input state of this pin must be made during power-down state (

SPDN-bit [CR0-B7] = ‘1’) or during initial mode.

SYNCSEL

This is the frame sync timing selection pin for PCM interface. A logic “0” selects long frame sync timing, and a logic “1” selects short frame sync timing. Refer Figure 5 to Figure8 for the timing. (Note) The change of the input state of this pin must be made during power-down state (

SPDN-bit [CR0-B7] = ‘1’) or during initial mode.

PCMSEL

This is the coding format selection pin for PCM interface for the PCMO-pin output and the PCMI-pin input signal. A logic ‘0’ selects 16-bit linear PCM (2’s complement) coding format, and a logic ‘1’ selects µ-law PCM coding format. The full scale table for both formats are shown below;

16bit Linear PCM (2’s complement) Full Scale Table

Level MSB

+ Full Scale 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

+1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

-1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

- Full Scale 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

-law PCM Full Scale Table

Level MSB

+ Full Scale 1 0 0 0 0 0 0 0

+0 1 1 1 1 1 1 1 1

-0 0 1 1 1 1 1 1 1

- Full Scale 0 0 0 0 0 0 0 0

(Note) If PCM interface is not used, set this pin to a logic ‘0’. (Note) The change of the input state of this pin must be made during power-down state (

Not for Publication

SPDN-bit [CR0-B7] = ‘1’) or during initial mode.

LSB

PDN pin = logic ‘0’ or

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PEDL7037-003-05Zz_Digest

OKI Semiconductor ML7037-003

PCMI

This is the receive PCM data input pin on the line-side. This input data is shifted at the falling edge of the BCLK. The PCM coding format can be selected between 16-bit linear PCM (2’s complement) coding format and µ-law PCM coding format with the PCMSEL pin or the PCMSEL-bit [CR0-B4]. The PCM frame sync timing can be selected between a long frame sync and a short frame sync with the SYNCSEL pin. Refer Figure 5 to Figure8 for the timing. (Note) If this pin is not used, set this pin to a logic ‘0’.

(Note) The change of the input state of this pin must be made during power-down state (

SPDN-bit [CR0-B7] = ‘1’) or during initial mode.

PCMO

This is the receive PCM data output pin on the line-side. This output data is shifted at the rising edge of the BCLK. During power-down mode (

PCM data bits are not being output, this pin goes to a high impedance state. The PCM coding format can be selected between 16-bit linear PCM (2’s complement) coding format and -law

PCM coding format with the PCMSEL pin or the PCMSEL-bit [CR0-B4]. The PCM frame sync timing can be selected between a long frame sync and a short frame sync with the SYNCSEL pin. Refer Figure 5 to Figure8 for the timing.

PDN pin = logic ‘0’ or SPDN-bit [CR0-B7] = ‘1’) and initial mode or while effective

PDN pin = logic ‘0’ or

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PEDL7037-003-05Zz_Digest

BCLK

PCMI

BCLK

OKI Semiconductor ML7037-003

SYNC

1 2 3 4 5 6 13 14 15 16 17 18 1 2 3 4 5

D10

PCMO

D15 D14 D 13 D12 D 11 D3 D 2 D1 D0 D15 D14 D 13 D12 D 11

Hi -Z Hi -Z

D15 D14 D 13 D12 D 11 D3 D 2 D1 D0 D15 D14 D 13 D12 D 11

Figure 5 16-bit linear PCM timing chart (long frame sync)

SYNC

1 2 3 4 5 6 13 14 15 16 17 18 1 2 3 4 5

PCMI

PCMO

Hi -Z Hi -Z

D15 D14 D13 D12 D 11 D3 D2 D1 D0 D15 D14 D13 D12D4

Figure 6 16-bit linear PCM timing chart (short frame sync)

SYNC

1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 513

PCMI

D7 D6 D5 D 3 D2 D 0 D7 D6 D5 D4 D3D 1D4

Hi -Z Hi -Z

PCMO

D7 D6 D5 D 3 D2 D 0 D7 D6 D5 D4 D3D 1D4

Figure 7 µ-law PCM timing chart (long frame sync)

SYNC

1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 513

PCMI

PCMO

Hi-Z Hi-Z

D7 D6 D5 D3 D2 D0 D7 D6 D5 D4D1D4

Figure 8 µ-law PCM timing chart (short frame sync)

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OKI ML7037 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual