OKI ML7029 User Manual

OKI Semiconductor

FEDL7029-03

Issue Date: Feb. 18, 2004

ML7029

Multifunction ADPCM CODEC

GENERAL DESCRIPTION

The ML7029 is a single channel ADPCM CODEC IC which performs mutual transcoding between the analog voice band signal and 32 kbps ADPCM serial data.

FEATURES

• Single 3 V Power Supply Operation (V

• ADPCM Algorithm: ITU-T G.726 (32 kbps, 24 kbps, 16 kbps)

• Full-Duplex Transmit/Receive Operation

• Transmit/Receive Synchronous Mode Only

• PCM Data Format: µ-law

• Serial PCM/ADPCM Transmission Data Rate: 64 kbps to 2048 kbps (when SYNC = 8 kHz)

• Low Power Consumption

Operating Mode: 18 mW Typ. (V Power-Down Mode: 0.03 mW Typ. (V

• Sampling Frequency: 6 kHz to 21 kHz selectable (However, there are

• Master Clock Frequency: Sampling frequency × 1296

When SYNC = 8 kHz: 10.368 MHz

• Transmit/Receive Mute, Transmit/Receive Programmable Gain Control

• Side Tone Path with Programmable Attenuation (8-Step Level Adjustment)

• Serial MCU Interface Control

• Package:

30-pin plastic SSOP (SSOP30-P-56-0.65-K) (ML7029)

: 2.7 to 3.6 V)

DD

= 3.0 V, SYNC = 8 kHz)

DD

= 3.0 V, SYNC = 8 kHz)

DD

limitations to 16 kHz or higher frequencies)

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–GSX

A

K

N

K

A

OKI Semiconductor

BLOCK DIAGRAM

AIN

VFRO

SG

20 kΩ

A/D

Conv.

VREF

CR2-B7

D/A

Conv.

V

TXON/ OFF

D

V

DG

LPF

AG

BPF/ LPF

MC

CR2-B6 to B4

CR3-B7 to B5

CR2-B2 to B0

PD

CR2-B3

RXON/

OFF

MCU I/F

DIN

DOUT

PCM

Compander

DPCM

PCM

Expander

DEN

EXC

ML7029

PCMSO

PCMSI IS IR

PCMRO

PCMRI

BCLK SYNC

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PIN CONFIGURATION (TOP VIEW)

1

GSX

NC

2

AIN–

VFRO

PD

NC

SG

NC

V

NC

AG

NC

NC NC

DG

3 4 5 6 7

A

8 9 10 11 12 13 14 15

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

VD BCLK SYNC PCMSO PCMSI IS IR PCMRO PCMRI

NC

MCK DEN EXCK DIN DOUT

ML7029

NC: No Connection

30-Pin Plastic SSOP

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ML7029

PIN FUNCTIONAL DESCRIPTIONS

AIN–, GEX

Transmit analog input and transmit level adjustment. AIN– is connected to the inverting input of the transmit amplifier. GSX is connected to th e transmit amplifier output. During power-down mode, the GSX output is a high impedance state.

VFRO

Receive analog output. During power-down mode, the VFRO output is in a high impedance state.

SG

Analog signal ground. The output voltage of this pin is approximately 1.4 V. Put 10 µF plus 0.1 µF (ceramic type) bypass capacitors between this pin and AG. During power-down, this output voltage is 0 V. This pin should be used via a buffer if used externally.

AG

Analog ground.

DG

Digital ground. This ground is separated from the analog signal ground pin (AG). The DG pin must be kept as close as possible to AG on the PCB.

Va

Analog +3 V power supply.

V

D

Digital +3 V power supply. This power supply is separated from the analog signal power supply pin (V as possible to V

on the PCB.

A

PDN

Power-down and reset control input. A “0” level makes the IC enter a power-down state. At the same time, all control register data are reset to the initial state. Set this pin to “1” during normal operating mode. The power-down state is controlled b y a logical

OR with CR0-B5 of the control register. When using PDN for power-down and reset control, set CR0-B5 to digital “0”. The reset width (a “L” level period) should be 200 ns or more. Be sure to reset the control registers by executing this power down to keep this pin to digital “0”level for 200 ns or longer after the power is turned on and V

exceeds 2.7 V.

DD

). The VD pin must be kept as close

A

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ML7029

MCK

Master clock input. The frequency is 1296 times the SYNC signal. For example, it is 10.368 MHz when the SYNC signal is 8 kHz. The master clock signal may be asynchronous with BCLK and SYNC.

PCMSO

Transmit PCM data output. PCM is output from MSB in synchronization with the rising edge of BCLK and XSYNC. Refer to Figure 1. During power-down, the PCMSO output is at “L” level.

PCMSI

Transmit PCM data input. This signal is converted to the transmit ADPCM data, PCM is shifted in synchronization with the falling edge of BCLK. Normally, this pin is connected to PCMSO. Refer to Figure 1.

PCMRO

Receive PCM data output. PCM is the output signal after ADPCM decoder processing. This signal is output serially from MSB in synchronization with the rising edge of BCLK and RSYNC. Refer to Figure 1. During power-down, the PCMRO output is at “L” level.

PCMRI

Receive PCM data input. PCM is shifted on the rising edge of the BCLK and input from MSB. Normally, this p in is connected to PCMRO. Refer to Figure 1.

IS

Transmit ADPCM signal output. After having encoded PCM with ADPCM, the signal is output from MSB in synchronization with the rising edge of BCLK and XSYNC. Refer to Figure 1. This pin is at “H” level during power-down.

IR

Receive ADPCM signal input. This input signal is shifted serially on the falling edge of BCLK and SYNC and input from MSB. Refer to Figure

1.

BCLK

Shift clock input for the PCM and ADPCM data. The frequency is set in the range of 8 to 256 times the SYNC frequency. Refer to Figure 1.

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SYMC

Sampling input for the PCM and ADPCM data. The frequency is 8 kHz or 11.025 kHz and is selected by the control register data CR3-B1. Synchronize this signal with BCLK signal. SYNC is used to indicate the MSB of the PCM data stream. Refer to Figure 1.

SYNC

BCLK

125 µs (SYNC = 8 kHz)

ML7029

PCMSO/PCMSI/ PCMRO/PCMRI

IS/IR

MSB

LSB

Figure 1 PCM and ADPCM Interface Basic Timing

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ML7029

DEN, EXCK, DIN, DOUT

Serial control ports for MCU interface. Reading and writing data are performed by an external MCU through these pins. The 8-byte cotrol registers (CR0 to 7) are provided on the device. DEN is the “Enable” control signal input, EXCK is the data shift clock input, DIN is the address and data inpu t, and DOUT is the data output. Figures 2-1 and 2-2 show the input/output timing diagram. During power-down, the DOUT output is in a high impedance state.

DEN

EXCK

DIN

DOUT

W B7 B6 B5 B4 B3 B2 B1 B0

2 A1 A0

High Impedance

(a) Data Write Timing Diagram

DEN

EXCK

DIN DOUT

High Impedance

R

2 A1 A0

B7 B6 B5 B4 B3 B2 B1 B0

(b) Data Read Timing Diagram

Figure 2-1 MCU Interface Input/Output Timing (DIN = 12 bits)

DEN

EXCK

DIN

DOUT

W

2 A1 A0

B7 B6 B5 B4 B3 B2 B1 B0

High Impedance

(a) Data Write Timing Diagram

DEN

EXCK

DIN

DOUT

R

2 A1 A0

High Impedance

B7 B6 B5 B4 B3 B2 B1 B0

Figure 2-2 MCU Interface Input/Output Timing (DIN = 16 bits)

(b) Data Read Timing Diagram

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Table 1 shows the register map.

Name

CR0 0 0 0

CR1 0 0 1 MODE 1 MODE 0

CR2 0 1 0

CR3 0 1 1

R/W : Read/Write enable

Address Control and Detect Data

A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0

— —

TX

ON/OFF

Side Tone

GAIN2

TX

GAIN2

Side Tone

GAIN1

Table 1 Control Register Map

PDN

ALL

TX

RESET

TX

GAIN1

Side Tone

GAIN0

— — — — —

RX

RESET

TX

GAIN0

— — —

TX

MUTE

RX

ON/OFF

RX

MUTE

RX

GAIN2

—

RX

GAIN1

HPF

8k/11k

RX

PAD

RX

GAIN0

HPF

ON/OFF

ML7029

R/W

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ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Condition Rating Unit Power Supply Voltage VDD — –.3 to +5.0 V Analog Input Voltage V Digital Input Voltage V Storage Temperature T

— –0.3 to VDD+0.3 V

AIN

— –0.3 to VDD+0.3 V

DIN

— –55 to +150 °C

stg

RECOMMENDED OPERATION CONDITIONS

Parameter Symbol Condition Min. Typ. Max. Unit Power Supply Voltage VDD Voltage must be fixed +2.7 3.0 +3.6 V Operating Temperature

Range Digital Input High Voltage VIH Digital Input Pins 0.45 × V Digital Input Low Voltage VIL Digital Input Pins 0 — 0.16 × VDD V Master Clock Frequency f Master Clock Frequency

Accuracy Bit Clock Duty f Sampling Frequency (*1) f

Master Clock Duty Ratio D Clock Duty Ratio D Digital Input Rise Time tir Digital Input Pins — — 50 ns Digital Input Fall Time tif Digital Input Pins — — 50 ns PCM Sync Signal Setting

Time (Continuous BCLK) PCM Sync Signal Setting

Time (Burst Mode Clock) SYNC Signal Width

(Continuous BCLK) SYNC Signal Width

(Burst Mode Clock) PCM, ADPCM Setup Time PCM, ADPCM Hold Time tDH — 100 — — ns Digital Output Load CDL Digital Output Pins — — 100 pF Bypass Capacitors for SG CSG SG to AG 10+0.1 — — µF

*1: Refer to the Appendix.

Ta —

MCK

MCK1

f

MCK

MCK2

BCLK SYNC × 8—

BCK

SYNC 6.0 8.0 16 kHz

SYNC

MCK (≤20.736 MHz) 30 50 70 %

MCK

BCLK, EXCK 30 50 70 %

CLK

t

BS

t

SB

t

SYNC (see Fig. 3-1) 1BCLK —

WS

SYNC (see Fig. 3-2) 1BCLK —

t

WSB

t

DS

BCLK ↔ SYNC

(see Fig. 3-1)

BCLK ↔ SYNC

(see Fig. 3-2)

— 100 — — ns

–25 +25 +70 °C

DD

7.776

–0.01%

— VDD V

10.368

SYNC ×

1296

20.736

+0.01%

SYNC ×

256

MHz MHz

kHz

100 — — ns

0 — 20 µs

SYNC –1

BCLK

Burst

Clock –1

µs

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