OKI ML7020 User Manual

FEDL7020-02

This version: Nov. 2000

1

Semiconductor

Previous version: Feb. 2000

ML7020

1200 bps MODEM for Remote Control Systems

GENERAL DESCRIPTION

The ML7020 is a 1200 bps modem LSI developed for remote control systems. The functions incorporated are
those of a 1200 bps FSK modem conforming to ITU-T Recommendations V.23, DTMF signal generation and
detection, call progress tone (CPT) generation and detection. Each functional block can be controlled via a 4-bit
processor interface.

FEATURES

•

Single 5 V power supply operation (V

•

Low power consumption: During operation: 5 mA typ.

During the power down mode: 7 µA typ.

•

Built-in 1200 bps modem conforming to ITU-T V.23 recommendations

•

Built-in DTMF signal generator with a switchable 6-dB attenuator

•

Built-in DTMF detector (the input can be selected from either the line or the terminal)

•

Built-in call progress tone generator. The output frequency can be selected from 400 Hz and 800 Hz.

•

Built-in call progress tone detector

•

Three analog input systems (switchable)

•

Analog output for the line is of the differential type and can drive a 600 Ω line transformer.

•

Analog output for the terminal is of the single-ended type and can drive a 1.2 kΩ load.

•

Built-in switch for selecting the 600 Ω termination

•

4-Bit processor interface

•

Built-in oscillator circuit for a 3.579545 MHz crystal

•

Package: 32-Pin plastic SSOP (SSOP32-P-430-1.00-K) (Product name: ML7020MB)

: 4.5 to 5.5 V)

DD

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BLOCK DIAGRAM

FEDL7020-02

ML7020

TI–
TI+

TIO

LI1–
LI1+
LI1O

LI2–

LI2O

TO

LO+

Input Amplifier 1

Input Amplifier 2

Input Amplifier 3

Output Amplifier 1

1.2 k

Ω

Output Amplifier 2

–1LO–

1.2 k

Ω

+1

Output Amplifier 3

Post­LPF

SW1

SW2

SW4

SW5

ATT

DTMF

Reception

CPT

Detection

Modem

Reception

Transmission

Modem

Transmission

Transmission

SP

DETB

RD

CPT

XD

DTMF

SWI

SW3

SGO
SGC

SG

DD

GND

CSB

MCU I/F

RDB

WRB

Oscillator

Circuit

A1, A0

D3 to D0

* CPT: Call progress tone
* The state shown of each switch is that when the register is set to “0”.

X1
X2
CLKO

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PIN CONFIGURATION (TOP VIEW)

32-Pin plastic SSOP

1

V

DD

2

TIO

3

TI–

4

TI+

5

LI1O

6

LI1–

7

LI1+

32

31

30

29

28

27

26

FEDL7020-02

ML7020

SP

DETB

RD

XD

X1

X2

CLKO

SWI

SGO

LI2O

LI2–

TO

LO+

LO–

SGC

GND

8

9

10

11

12

13

14

15

16

25

24

23

22

21

20

19

18

17

D3

D2

D1

D0

A1

A0

WRB

RDB

CSB

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PIN DESCRIPTIONS

Pin No. Symbol I/O Description

1VDDPower supply pin. Connect a +5 V power supply to this pin.

The output pin of the input amplifier 1. See Figure 1. For the sake of noise

2TIOO

3TI–I
4 TI+ I The non-inverting input pin for the input amplifier 1.

5LI1OO

6LI1–I
7 LI1+ I The non-inverting input pin for the input amplifier 2.
8SWII

9SGOO

10 LI2O O

11 LI2– I

12 TO O

13 LO+ O

14 LO– O

15 SGC O

16 GND The ground pin for the LSI. Connect a 0 V input to this pin.

17 CSB I

18 RDB I

19 WRB I
20 A0 I The address input pin A0 for the processor interface.

reduction, connect a capacitor between this pin and TI– (3) so as to attenuate
high frequency components above 10 kHz.

The inverting input pin for the input a mp lifi er 1. When the input amplifier 1 is not
used, connect pin TIO (2) to pin TI– (3), and connect pin TI+ (4) to pin SGO.

The output pin for the input amplifier 2. See Figure 1. For the sake of noise
reduction, connect a capacitor between this pin and LI1– (6) so as to attenuate
high frequency components above 10 kHz.

The inverting input pin for the input a mp lifi er 2. When the input amplifier 2 is not
used, connect pin LI1O (5) and LI1– (6), and connect pin LI+ (7) to pin SGO.

The input pin for SW3. This pin is connected internally to SGO (9) when SW3 is
to be made ON.

The signal ground output pin for external circuits. A voltage of about VDD/2 is
output from this pin.

The output pin for the input amplifier 3. See Figure 1. For the sake of noise
reduction, connect a capacitor between this pin and LI2– (10) so as to attenuate
high frequency components above 10 kHz.

The inverting input pin for the input amplifier 3.
When the input amplifier 3 is not used, connect pin LI2O (10) and LI2– (11).
The output pin of the output amplifier 1.
Can drive a load of 1.2 kΩ or more.
The non-inverting output pin for the output amplifier 2. See Figure 2 for details

of connecting a peripheral circuit.
The inverting output pin of the output amplifier 2. See Figure 2 for details of

connecting a peripheral circuit.
The signal ground output pin for internal circuits. A voltage of about VDD/2 is

output from this pin.
Connect a 1 µF capacitor between SGC (15) and GND (16).

The chip select pin for the processor interface.
Reading and writing are possibl e when th is inpu t i s “0”. Reading and writing are

disabled when this input is “1”.
The read control pin for the processor interface.
Data can be read from the LSI when this pin is “0”.
The write control pin for the processor interface.
Data is written into this LSI at the rising edge of the WR signal.

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ML7020

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Pin No. Symbol I/O Description

21 A1 I The address input pin A1 for the processor interface.
22 D0 IO The data input/output pin D0 for the processor interface.
23 D1 IO The data input/output pin D1 for the processor interface.
24 D2 IO The data input/output pin D2 for the processor interface.
25 D3 IO The data input/output pin D3 for the processor interface.
26 CLKOUT O The 3.579545 MHz oscillator circuit output pin.
27 X2 O

28 X1 I

29 XD I

30 RD O

31 DETB O

32 SP O

The pins for connecting a 3.579545 MHz crystal. The capacitors and the
feedback resistor are internally connected to these pins. When inputting an
external clock, connect the input to the X1 pin via a 1000 pF capacitor and leave
the pin X2 open.

The modem transmit data input pin.
The “1” level corresponds to the mark data and the “0” level corresponds to the

space data.
The modem receive data output pin. The mark and space data are the same as

for XD. A mark is output when no carrier is detected.
The pin for outputting the carrier detect signal of the modem or the call progress

tone detector output.
The detection result corresponding to the respective operating mode is output

from this pin. A “0” indicates detection and a “1” indicates non-detection.
The DTMF reception detection output pin.
A “0” indicates detection and a “1” indicates non-detection.

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FEDL7020-02

ML7020

TIO

Terminal→

Line 1→

Line 2→

R1

R3

R5

C1

C2

C3

R2

Input amplifier 1

R4

Input amplifier 2

R6

Input amplifier 3

TI–

TI+

SGO

LI1O

LI1–

LI2O

LI2–

Example: The cutoff
frequency is fc = 10 kHz,
when R1 = R2 = 30 kΩ
(gain = 1), and C1 is 500 pF

VREF

Example: The cutoff
frequency is fc = 10 kHz,
when R3 = R4 = 30 kΩ
(gain = 1), and C2 is 500 pF

Example: The cutoff
frequency is fc = 10 kHz,
when R5 = R6 = 30 kΩ
(gain = 1), and C3 is 500 pF

Output amplifier 2

Figure 1 Input amplifier 1 to 3 interface

600 Ω 600 Ω: 600 Ω
LO–
(–10.0 dBm)

0.022 µF

(–10.0 dBm)
LO+

Output amplifier 3

(When the transformer loss is 0 dB)

Figure 2 Output amplifier 2, 3 interface example

–10.0 dBm

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